arch/mips/kernel/perf_event_mipsxx.c

   1 /*
   2  * Linux performance counter support for MIPS.
   3  *
   4  * Copyright (C) 2010 MIPS Technologies, Inc.
   5  * Copyright (C) 2011 Cavium Networks, Inc.
   6  * Author: Deng-Cheng Zhu
   7  *
   8  * This code is based on the implementation for ARM, which is in turn
   9  * based on the sparc64 perf event code and the x86 code. Performance
  10  * counter access is based on the MIPS Oprofile code. And the callchain
  11  * support references the code of MIPS stacktrace.c.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/cpumask.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/smp.h>
  21 #include <linux/kernel.h>
  22 #include <linux/perf_event.h>
  23 #include <linux/uaccess.h>
  24
  25 #include <asm/irq.h>
  26 #include <asm/irq_regs.h>
  27 #include <asm/stacktrace.h>
  28 #include <asm/time.h> /* For perf_irq */
  29
  30 #define MIPS_MAX_HWEVENTS 4
  31 #define MIPS_TCS_PER_COUNTER 2
  32 #define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1)
  33
  34 struct cpu_hw_events {
  35         /* Array of events on this cpu. */
  36         struct perf_event       *events[MIPS_MAX_HWEVENTS];
  37
  38         /*
  39          * Set the bit (indexed by the counter number) when the counter
  40          * is used for an event.
  41          */
  42         unsigned long           used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
  43
  44         /*
  45          * Software copy of the control register for each performance counter.
  46          * MIPS CPUs vary in performance counters. They use this differently,
  47          * and even may not use it.
  48          */
  49         unsigned int            saved_ctrl[MIPS_MAX_HWEVENTS];
  50 };
  51 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
  52         .saved_ctrl = {0},
  53 };
  54
  55 /* The description of MIPS performance events. */
  56 struct mips_perf_event {
  57         unsigned int event_id;
  58         /*
  59          * MIPS performance counters are indexed starting from 0.
  60          * CNTR_EVEN indicates the indexes of the counters to be used are
  61          * even numbers.
  62          */
  63         unsigned int cntr_mask;
  64         #define CNTR_EVEN       0x55555555
  65         #define CNTR_ODD        0xaaaaaaaa
  66         #define CNTR_ALL        0xffffffff
  67 #ifdef CONFIG_MIPS_MT_SMP
  68         enum {
  69                 T  = 0,
  70                 V  = 1,
  71                 P  = 2,
  72         } range;
  73 #else
  74         #define T
  75         #define V
  76         #define P
  77 #endif
  78 };
  79
  80 static struct mips_perf_event raw_event;
  81 static DEFINE_MUTEX(raw_event_mutex);
  82
  83 #define C(x) PERF_COUNT_HW_CACHE_##x
  84
  85 struct mips_pmu {
  86         u64             max_period;
  87         u64             valid_count;
  88         u64             overflow;
  89         const char      *name;
  90         int             irq;
  91         u64             (*read_counter)(unsigned int idx);
  92         void            (*write_counter)(unsigned int idx, u64 val);
  93         const struct mips_perf_event *(*map_raw_event)(u64 config);
  94         const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
  95         const struct mips_perf_event (*cache_event_map)
  96                                 [PERF_COUNT_HW_CACHE_MAX]
  97                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  98                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
  99         unsigned int    num_counters;
 100 };
 101
 102 static struct mips_pmu mipspmu;
 103
 104 #define M_CONFIG1_PC    (1 << 4)
 105
 106 #define M_PERFCTL_EXL                   (1      <<  0)
 107 #define M_PERFCTL_KERNEL                (1      <<  1)
 108 #define M_PERFCTL_SUPERVISOR            (1      <<  2)
 109 #define M_PERFCTL_USER                  (1      <<  3)
 110 #define M_PERFCTL_INTERRUPT_ENABLE      (1      <<  4)
 111 #define M_PERFCTL_EVENT(event)          (((event) & 0x3ff)  << 5)
 112 #define M_PERFCTL_VPEID(vpe)            ((vpe)    << 16)
 113
 114 #ifdef CONFIG_CPU_BMIPS5000
 115 #define M_PERFCTL_MT_EN(filter)         0
 116 #else /* !CONFIG_CPU_BMIPS5000 */
 117 #define M_PERFCTL_MT_EN(filter)         ((filter) << 20)
 118 #endif /* CONFIG_CPU_BMIPS5000 */
 119
 120 #define    M_TC_EN_ALL                  M_PERFCTL_MT_EN(0)
 121 #define    M_TC_EN_VPE                  M_PERFCTL_MT_EN(1)
 122 #define    M_TC_EN_TC                   M_PERFCTL_MT_EN(2)
 123 #define M_PERFCTL_TCID(tcid)            ((tcid)   << 22)
 124 #define M_PERFCTL_WIDE                  (1      << 30)
 125 #define M_PERFCTL_MORE                  (1      << 31)
 126 #define M_PERFCTL_TC                    (1      << 30)
 127
 128 #define M_PERFCTL_COUNT_EVENT_WHENEVER  (M_PERFCTL_EXL |                \
 129                                         M_PERFCTL_KERNEL |              \
 130                                         M_PERFCTL_USER |                \
 131                                         M_PERFCTL_SUPERVISOR |          \
 132                                         M_PERFCTL_INTERRUPT_ENABLE)
 133
 134 #ifdef CONFIG_MIPS_MT_SMP
 135 #define M_PERFCTL_CONFIG_MASK           0x3fff801f
 136 #else
 137 #define M_PERFCTL_CONFIG_MASK           0x1f
 138 #endif
 139 #define M_PERFCTL_EVENT_MASK            0xfe0
 140
 141
 142 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 143 static int cpu_has_mipsmt_pertccounters;
 144
 145 static DEFINE_RWLOCK(pmuint_rwlock);
 146
 147 #if defined(CONFIG_CPU_BMIPS5000)
 148 #define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
 149                          0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
 150 #else
 151 /*
 152  * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
 153  * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
 154  */
 155 #define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
 156                          0 : smp_processor_id())
 157 #endif
 158
 159 /* Copied from op_model_mipsxx.c */
 160 static unsigned int vpe_shift(void)
 161 {
 162         if (num_possible_cpus() > 1)
 163                 return 1;
 164
 165         return 0;
 166 }
 167
 168 static unsigned int counters_total_to_per_cpu(unsigned int counters)
 169 {
 170         return counters >> vpe_shift();
 171 }
 172
 173 #else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
 174 #define vpe_id()        0
 175
 176 #endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
 177
 178 static void resume_local_counters(void);
 179 static void pause_local_counters(void);
 180 static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
 181 static int mipsxx_pmu_handle_shared_irq(void);
 182
 183 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
 184 {
 185         if (vpe_id() == 1)
 186                 idx = (idx + 2) & 3;
 187         return idx;
 188 }
 189
 190 static u64 mipsxx_pmu_read_counter(unsigned int idx)
 191 {
 192         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 193
 194         switch (idx) {
 195         case 0:
 196                 /*
 197                  * The counters are unsigned, we must cast to truncate
 198                  * off the high bits.
 199                  */
 200                 return (u32)read_c0_perfcntr0();
 201         case 1:
 202                 return (u32)read_c0_perfcntr1();
 203         case 2:
 204                 return (u32)read_c0_perfcntr2();
 205         case 3:
 206                 return (u32)read_c0_perfcntr3();
 207         default:
 208                 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 209                 return 0;
 210         }
 211 }
 212
 213 static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
 214 {
 215         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 216
 217         switch (idx) {
 218         case 0:
 219                 return read_c0_perfcntr0_64();
 220         case 1:
 221                 return read_c0_perfcntr1_64();
 222         case 2:
 223                 return read_c0_perfcntr2_64();
 224         case 3:
 225                 return read_c0_perfcntr3_64();
 226         default:
 227                 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 228                 return 0;
 229         }
 230 }
 231
 232 static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
 233 {
 234         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 235
 236         switch (idx) {
 237         case 0:
 238                 write_c0_perfcntr0(val);
 239                 return;
 240         case 1:
 241                 write_c0_perfcntr1(val);
 242                 return;
 243         case 2:
 244                 write_c0_perfcntr2(val);
 245                 return;
 246         case 3:
 247                 write_c0_perfcntr3(val);
 248                 return;
 249         }
 250 }
 251
 252 static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
 253 {
 254         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 255
 256         switch (idx) {
 257         case 0:
 258                 write_c0_perfcntr0_64(val);
 259                 return;
 260         case 1:
 261                 write_c0_perfcntr1_64(val);
 262                 return;
 263         case 2:
 264                 write_c0_perfcntr2_64(val);
 265                 return;
 266         case 3:
 267                 write_c0_perfcntr3_64(val);
 268                 return;
 269         }
 270 }
 271
 272 static unsigned int mipsxx_pmu_read_control(unsigned int idx)
 273 {
 274         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 275
 276         switch (idx) {
 277         case 0:
 278                 return read_c0_perfctrl0();
 279         case 1:
 280                 return read_c0_perfctrl1();
 281         case 2:
 282                 return read_c0_perfctrl2();
 283         case 3:
 284                 return read_c0_perfctrl3();
 285         default:
 286                 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
 287                 return 0;
 288         }
 289 }
 290
 291 static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
 292 {
 293         idx = mipsxx_pmu_swizzle_perf_idx(idx);
 294
 295         switch (idx) {
 296         case 0:
 297                 write_c0_perfctrl0(val);
 298                 return;
 299         case 1:
 300                 write_c0_perfctrl1(val);
 301                 return;
 302         case 2:
 303                 write_c0_perfctrl2(val);
 304                 return;
 305         case 3:
 306                 write_c0_perfctrl3(val);
 307                 return;
 308         }
 309 }
 310
 311 static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
 312                                     struct hw_perf_event *hwc)
 313 {
 314         int i;
 315
 316         /*
 317          * We only need to care the counter mask. The range has been
 318          * checked definitely.
 319          */
 320         unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
 321
 322         for (i = mipspmu.num_counters - 1; i >= 0; i--) {
 323                 /*
 324                  * Note that some MIPS perf events can be counted by both
 325                  * even and odd counters, wheresas many other are only by
 326                  * even _or_ odd counters. This introduces an issue that
 327                  * when the former kind of event takes the counter the
 328                  * latter kind of event wants to use, then the "counter
 329                  * allocation" for the latter event will fail. In fact if
 330                  * they can be dynamically swapped, they both feel happy.
 331                  * But here we leave this issue alone for now.
 332                  */
 333                 if (test_bit(i, &cntr_mask) &&
 334                         !test_and_set_bit(i, cpuc->used_mask))
 335                         return i;
 336         }
 337
 338         return -EAGAIN;
 339 }
 340
 341 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
 342 {
 343         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 344
 345         WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 346
 347         cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
 348                 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
 349                 /* Make sure interrupt enabled. */
 350                 M_PERFCTL_INTERRUPT_ENABLE;
 351         if (IS_ENABLED(CONFIG_CPU_BMIPS5000))
 352                 /* enable the counter for the calling thread */
 353                 cpuc->saved_ctrl[idx] |=
 354                         (1 << (12 + vpe_id())) | M_PERFCTL_TC;
 355
 356         /*
 357          * We do not actually let the counter run. Leave it until start().
 358          */
 359 }
 360
 361 static void mipsxx_pmu_disable_event(int idx)
 362 {
 363         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 364         unsigned long flags;
 365
 366         WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 367
 368         local_irq_save(flags);
 369         cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
 370                 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
 371         mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
 372         local_irq_restore(flags);
 373 }
 374
 375 static int mipspmu_event_set_period(struct perf_event *event,
 376                                     struct hw_perf_event *hwc,
 377                                     int idx)
 378 {
 379         u64 left = local64_read(&hwc->period_left);
 380         u64 period = hwc->sample_period;
 381         int ret = 0;
 382
 383         if (unlikely((left + period) & (1ULL << 63))) {
 384                 /* left underflowed by more than period. */
 385                 left = period;
 386                 local64_set(&hwc->period_left, left);
 387                 hwc->last_period = period;
 388                 ret = 1;
 389         } else  if (unlikely((left + period) <= period)) {
 390                 /* left underflowed by less than period. */
 391                 left += period;
 392                 local64_set(&hwc->period_left, left);
 393                 hwc->last_period = period;
 394                 ret = 1;
 395         }
 396
 397         if (left > mipspmu.max_period) {
 398                 left = mipspmu.max_period;
 399                 local64_set(&hwc->period_left, left);
 400         }
 401
 402         local64_set(&hwc->prev_count, mipspmu.overflow - left);
 403
 404         mipspmu.write_counter(idx, mipspmu.overflow - left);
 405
 406         perf_event_update_userpage(event);
 407
 408         return ret;
 409 }
 410
 411 static void mipspmu_event_update(struct perf_event *event,
 412                                  struct hw_perf_event *hwc,
 413                                  int idx)
 414 {
 415         u64 prev_raw_count, new_raw_count;
 416         u64 delta;
 417
 418 again:
 419         prev_raw_count = local64_read(&hwc->prev_count);
 420         new_raw_count = mipspmu.read_counter(idx);
 421
 422         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 423                                 new_raw_count) != prev_raw_count)
 424                 goto again;
 425
 426         delta = new_raw_count - prev_raw_count;
 427
 428         local64_add(delta, &event->count);
 429         local64_sub(delta, &hwc->period_left);
 430 }
 431
 432 static void mipspmu_start(struct perf_event *event, int flags)
 433 {
 434         struct hw_perf_event *hwc = &event->hw;
 435
 436         if (flags & PERF_EF_RELOAD)
 437                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 438
 439         hwc->state = 0;
 440
 441         /* Set the period for the event. */
 442         mipspmu_event_set_period(event, hwc, hwc->idx);
 443
 444         /* Enable the event. */
 445         mipsxx_pmu_enable_event(hwc, hwc->idx);
 446 }
 447
 448 static void mipspmu_stop(struct perf_event *event, int flags)
 449 {
 450         struct hw_perf_event *hwc = &event->hw;
 451
 452         if (!(hwc->state & PERF_HES_STOPPED)) {
 453                 /* We are working on a local event. */
 454                 mipsxx_pmu_disable_event(hwc->idx);
 455                 barrier();
 456                 mipspmu_event_update(event, hwc, hwc->idx);
 457                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 458         }
 459 }
 460
 461 static int mipspmu_add(struct perf_event *event, int flags)
 462 {
 463         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 464         struct hw_perf_event *hwc = &event->hw;
 465         int idx;
 466         int err = 0;
 467
 468         perf_pmu_disable(event->pmu);
 469
 470         /* To look for a free counter for this event. */
 471         idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
 472         if (idx < 0) {
 473                 err = idx;
 474                 goto out;
 475         }
 476
 477         /*
 478          * If there is an event in the counter we are going to use then
 479          * make sure it is disabled.
 480          */
 481         event->hw.idx = idx;
 482         mipsxx_pmu_disable_event(idx);
 483         cpuc->events[idx] = event;
 484
 485         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 486         if (flags & PERF_EF_START)
 487                 mipspmu_start(event, PERF_EF_RELOAD);
 488
 489         /* Propagate our changes to the userspace mapping. */
 490         perf_event_update_userpage(event);
 491
 492 out:
 493         perf_pmu_enable(event->pmu);
 494         return err;
 495 }
 496
 497 static void mipspmu_del(struct perf_event *event, int flags)
 498 {
 499         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 500         struct hw_perf_event *hwc = &event->hw;
 501         int idx = hwc->idx;
 502
 503         WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
 504
 505         mipspmu_stop(event, PERF_EF_UPDATE);
 506         cpuc->events[idx] = NULL;
 507         clear_bit(idx, cpuc->used_mask);
 508
 509         perf_event_update_userpage(event);
 510 }
 511
 512 static void mipspmu_read(struct perf_event *event)
 513 {
 514         struct hw_perf_event *hwc = &event->hw;
 515
 516         /* Don't read disabled counters! */
 517         if (hwc->idx < 0)
 518                 return;
 519
 520         mipspmu_event_update(event, hwc, hwc->idx);
 521 }
 522
 523 static void mipspmu_enable(struct pmu *pmu)
 524 {
 525 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 526         write_unlock(&pmuint_rwlock);
 527 #endif
 528         resume_local_counters();
 529 }
 530
 531 /*
 532  * MIPS performance counters can be per-TC. The control registers can
 533  * not be directly accessed accross CPUs. Hence if we want to do global
 534  * control, we need cross CPU calls. on_each_cpu() can help us, but we
 535  * can not make sure this function is called with interrupts enabled. So
 536  * here we pause local counters and then grab a rwlock and leave the
 537  * counters on other CPUs alone. If any counter interrupt raises while
 538  * we own the write lock, simply pause local counters on that CPU and
 539  * spin in the handler. Also we know we won't be switched to another
 540  * CPU after pausing local counters and before grabbing the lock.
 541  */
 542 static void mipspmu_disable(struct pmu *pmu)
 543 {
 544         pause_local_counters();
 545 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
 546         write_lock(&pmuint_rwlock);
 547 #endif
 548 }
 549
 550 static atomic_t active_events = ATOMIC_INIT(0);
 551 static DEFINE_MUTEX(pmu_reserve_mutex);
 552 static int (*save_perf_irq)(void);
 553
 554 static int mipspmu_get_irq(void)
 555 {
 556         int err;
 557
 558         if (mipspmu.irq >= 0) {
 559                 /* Request my own irq handler. */
 560                 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
 561                         IRQF_PERCPU | IRQF_NOBALANCING,
 562                         "mips_perf_pmu", NULL);
 563                 if (err) {
 564                         pr_warning("Unable to request IRQ%d for MIPS "
 565                            "performance counters!\n", mipspmu.irq);
 566                 }
 567         } else if (cp0_perfcount_irq < 0) {
 568                 /*
 569                  * We are sharing the irq number with the timer interrupt.
 570                  */
 571                 save_perf_irq = perf_irq;
 572                 perf_irq = mipsxx_pmu_handle_shared_irq;
 573                 err = 0;
 574         } else {
 575                 pr_warning("The platform hasn't properly defined its "
 576                         "interrupt controller.\n");
 577                 err = -ENOENT;
 578         }
 579
 580         return err;
 581 }
 582
 583 static void mipspmu_free_irq(void)
 584 {
 585         if (mipspmu.irq >= 0)
 586                 free_irq(mipspmu.irq, NULL);
 587         else if (cp0_perfcount_irq < 0)
 588                 perf_irq = save_perf_irq;
 589 }
 590
 591 /*
 592  * mipsxx/rm9000/loongson2 have different performance counters, they have
 593  * specific low-level init routines.
 594  */
 595 static void reset_counters(void *arg);
 596 static int __hw_perf_event_init(struct perf_event *event);
 597
 598 static void hw_perf_event_destroy(struct perf_event *event)
 599 {
 600         if (atomic_dec_and_mutex_lock(&active_events,
 601                                 &pmu_reserve_mutex)) {
 602                 /*
 603                  * We must not call the destroy function with interrupts
 604                  * disabled.
 605                  */
 606                 on_each_cpu(reset_counters,
 607                         (void *)(long)mipspmu.num_counters, 1);
 608                 mipspmu_free_irq();
 609                 mutex_unlock(&pmu_reserve_mutex);
 610         }
 611 }
 612
 613 static int mipspmu_event_init(struct perf_event *event)
 614 {
 615         int err = 0;
 616
 617         /* does not support taken branch sampling */
 618         if (has_branch_stack(event))
 619                 return -EOPNOTSUPP;
 620
 621         switch (event->attr.type) {
 622         case PERF_TYPE_RAW:
 623         case PERF_TYPE_HARDWARE:
 624         case PERF_TYPE_HW_CACHE:
 625                 break;
 626
 627         default:
 628                 return -ENOENT;
 629         }
 630
 631         if (event->cpu >= nr_cpumask_bits ||
 632             (event->cpu >= 0 && !cpu_online(event->cpu)))
 633                 return -ENODEV;
 634
 635         if (!atomic_inc_not_zero(&active_events)) {
 636                 mutex_lock(&pmu_reserve_mutex);
 637                 if (atomic_read(&active_events) == 0)
 638                         err = mipspmu_get_irq();
 639
 640                 if (!err)
 641                         atomic_inc(&active_events);
 642                 mutex_unlock(&pmu_reserve_mutex);
 643         }
 644
 645         if (err)
 646                 return err;
 647
 648         return __hw_perf_event_init(event);
 649 }
 650
 651 static struct pmu pmu = {
 652         .pmu_enable     = mipspmu_enable,
 653         .pmu_disable    = mipspmu_disable,
 654         .event_init     = mipspmu_event_init,
 655         .add            = mipspmu_add,
 656         .del            = mipspmu_del,
 657         .start          = mipspmu_start,
 658         .stop           = mipspmu_stop,
 659         .read           = mipspmu_read,
 660 };
 661
 662 static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
 663 {
 664 /*
 665  * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
 666  * event_id.
 667  */
 668 #ifdef CONFIG_MIPS_MT_SMP
 669         return ((unsigned int)pev->range << 24) |
 670                 (pev->cntr_mask & 0xffff00) |
 671                 (pev->event_id & 0xff);
 672 #else
 673         return (pev->cntr_mask & 0xffff00) |
 674                 (pev->event_id & 0xff);
 675 #endif
 676 }
 677
 678 static const struct mips_perf_event *mipspmu_map_general_event(int idx)
 679 {
 680
 681         if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
 682                 return ERR_PTR(-EOPNOTSUPP);
 683         return &(*mipspmu.general_event_map)[idx];
 684 }
 685
 686 static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
 687 {
 688         unsigned int cache_type, cache_op, cache_result;
 689         const struct mips_perf_event *pev;
 690
 691         cache_type = (config >> 0) & 0xff;
 692         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 693                 return ERR_PTR(-EINVAL);
 694
 695         cache_op = (config >> 8) & 0xff;
 696         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 697                 return ERR_PTR(-EINVAL);
 698
 699         cache_result = (config >> 16) & 0xff;
 700         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 701                 return ERR_PTR(-EINVAL);
 702
 703         pev = &((*mipspmu.cache_event_map)
 704                                         [cache_type]
 705                                         [cache_op]
 706                                         [cache_result]);
 707
 708         if (pev->cntr_mask == 0)
 709                 return ERR_PTR(-EOPNOTSUPP);
 710
 711         return pev;
 712
 713 }
 714
 715 static int validate_group(struct perf_event *event)
 716 {
 717         struct perf_event *sibling, *leader = event->group_leader;
 718         struct cpu_hw_events fake_cpuc;
 719
 720         memset(&fake_cpuc, 0, sizeof(fake_cpuc));
 721
 722         if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
 723                 return -EINVAL;
 724
 725         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 726                 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
 727                         return -EINVAL;
 728         }
 729
 730         if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
 731                 return -EINVAL;
 732
 733         return 0;
 734 }
 735
 736 /* This is needed by specific irq handlers in perf_event_*.c */
 737 static void handle_associated_event(struct cpu_hw_events *cpuc,
 738                                     int idx, struct perf_sample_data *data,
 739                                     struct pt_regs *regs)
 740 {
 741         struct perf_event *event = cpuc->events[idx];
 742         struct hw_perf_event *hwc = &event->hw;
 743
 744         mipspmu_event_update(event, hwc, idx);
 745         data->period = event->hw.last_period;
 746         if (!mipspmu_event_set_period(event, hwc, idx))
 747                 return;
 748
 749         if (perf_event_overflow(event, data, regs))
 750                 mipsxx_pmu_disable_event(idx);
 751 }
 752
 753
 754 static int __n_counters(void)
 755 {
 756         if (!(read_c0_config1() & M_CONFIG1_PC))
 757                 return 0;
 758         if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
 759                 return 1;
 760         if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
 761                 return 2;
 762         if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
 763                 return 3;
 764
 765         return 4;
 766 }
 767
 768 static int n_counters(void)
 769 {
 770         int counters;
 771
 772         switch (current_cpu_type()) {
 773         case CPU_R10000:
 774                 counters = 2;
 775                 break;
 776
 777         case CPU_R12000:
 778         case CPU_R14000:
 779                 counters = 4;
 780                 break;
 781
 782         default:
 783                 counters = __n_counters();
 784         }
 785
 786         return counters;
 787 }
 788
 789 static void reset_counters(void *arg)
 790 {
 791         int counters = (int)(long)arg;
 792         switch (counters) {
 793         case 4:
 794                 mipsxx_pmu_write_control(3, 0);
 795                 mipspmu.write_counter(3, 0);
 796         case 3:
 797                 mipsxx_pmu_write_control(2, 0);
 798                 mipspmu.write_counter(2, 0);
 799         case 2:
 800                 mipsxx_pmu_write_control(1, 0);
 801                 mipspmu.write_counter(1, 0);
 802         case 1:
 803                 mipsxx_pmu_write_control(0, 0);
 804                 mipspmu.write_counter(0, 0);
 805         }
 806 }
 807
 808 /* 24K/34K/1004K cores can share the same event map. */
 809 static const struct mips_perf_event mipsxxcore_event_map
 810                                 [PERF_COUNT_HW_MAX] = {
 811         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 812         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 813         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
 814         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
 815 };
 816
 817 /* 74K core has different branch event code. */
 818 static const struct mips_perf_event mipsxx74Kcore_event_map
 819                                 [PERF_COUNT_HW_MAX] = {
 820         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
 821         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 822         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
 823         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
 824 };
 825
 826 static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
 827         [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
 828         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
 829         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
 830         [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL  },
 831         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
 832         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
 833         [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
 834 };
 835
 836 static const struct mips_perf_event bmips5000_event_map
 837                                 [PERF_COUNT_HW_MAX] = {
 838         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
 839         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
 840         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
 841 };
 842
 843 static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
 844         [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
 845         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
 846         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
 847         [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
 848         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
 849         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
 850         [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
 851 };
 852
 853 /* 24K/34K/1004K cores can share the same cache event map. */
 854 static const struct mips_perf_event mipsxxcore_cache_map
 855                                 [PERF_COUNT_HW_CACHE_MAX]
 856                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 857                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 858 [C(L1D)] = {
 859         /*
 860          * Like some other architectures (e.g. ARM), the performance
 861          * counters don't differentiate between read and write
 862          * accesses/misses, so this isn't strictly correct, but it's the
 863          * best we can do. Writes and reads get combined.
 864          */
 865         [C(OP_READ)] = {
 866                 [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
 867                 [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
 868         },
 869         [C(OP_WRITE)] = {
 870                 [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
 871                 [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
 872         },
 873 },
 874 [C(L1I)] = {
 875         [C(OP_READ)] = {
 876                 [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
 877                 [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
 878         },
 879         [C(OP_WRITE)] = {
 880                 [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
 881                 [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
 882         },
 883         [C(OP_PREFETCH)] = {
 884                 [C(RESULT_ACCESS)]      = { 0x14, CNTR_EVEN, T },
 885                 /*
 886                  * Note that MIPS has only "hit" events countable for
 887                  * the prefetch operation.
 888                  */
 889         },
 890 },
 891 [C(LL)] = {
 892         [C(OP_READ)] = {
 893                 [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
 894                 [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
 895         },
 896         [C(OP_WRITE)] = {
 897                 [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
 898                 [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
 899         },
 900 },
 901 [C(DTLB)] = {
 902         [C(OP_READ)] = {
 903                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 904                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 905         },
 906         [C(OP_WRITE)] = {
 907                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 908                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 909         },
 910 },
 911 [C(ITLB)] = {
 912         [C(OP_READ)] = {
 913                 [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
 914                 [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
 915         },
 916         [C(OP_WRITE)] = {
 917                 [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
 918                 [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
 919         },
 920 },
 921 [C(BPU)] = {
 922         /* Using the same code for *HW_BRANCH* */
 923         [C(OP_READ)] = {
 924                 [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
 925                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
 926         },
 927         [C(OP_WRITE)] = {
 928                 [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
 929                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
 930         },
 931 },
 932 };
 933
 934 /* 74K core has completely different cache event map. */
 935 static const struct mips_perf_event mipsxx74Kcore_cache_map
 936                                 [PERF_COUNT_HW_CACHE_MAX]
 937                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 938                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 939 [C(L1D)] = {
 940         /*
 941          * Like some other architectures (e.g. ARM), the performance
 942          * counters don't differentiate between read and write
 943          * accesses/misses, so this isn't strictly correct, but it's the
 944          * best we can do. Writes and reads get combined.
 945          */
 946         [C(OP_READ)] = {
 947                 [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
 948                 [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
 949         },
 950         [C(OP_WRITE)] = {
 951                 [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
 952                 [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
 953         },
 954 },
 955 [C(L1I)] = {
 956         [C(OP_READ)] = {
 957                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 958                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 959         },
 960         [C(OP_WRITE)] = {
 961                 [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
 962                 [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
 963         },
 964         [C(OP_PREFETCH)] = {
 965                 [C(RESULT_ACCESS)]      = { 0x34, CNTR_EVEN, T },
 966                 /*
 967                  * Note that MIPS has only "hit" events countable for
 968                  * the prefetch operation.
 969                  */
 970         },
 971 },
 972 [C(LL)] = {
 973         [C(OP_READ)] = {
 974                 [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
 975                 [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
 976         },
 977         [C(OP_WRITE)] = {
 978                 [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
 979                 [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
 980         },
 981 },
 982 [C(ITLB)] = {
 983         [C(OP_READ)] = {
 984                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
 985                 [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
 986         },
 987         [C(OP_WRITE)] = {
 988                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
 989                 [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
 990         },
 991 },
 992 [C(BPU)] = {
 993         /* Using the same code for *HW_BRANCH* */
 994         [C(OP_READ)] = {
 995                 [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
 996                 [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
 997         },
 998         [C(OP_WRITE)] = {
 999                 [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
1000                 [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
1001         },
1002 },
1003 };
1004
1005 /* BMIPS5000 */
1006 static const struct mips_perf_event bmips5000_cache_map
1007                                 [PERF_COUNT_HW_CACHE_MAX]
1008                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1009                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1010 [C(L1D)] = {
1011         /*
1012          * Like some other architectures (e.g. ARM), the performance
1013          * counters don't differentiate between read and write
1014          * accesses/misses, so this isn't strictly correct, but it's the
1015          * best we can do. Writes and reads get combined.
1016          */
1017         [C(OP_READ)] = {
1018                 [C(RESULT_ACCESS)]      = { 12, CNTR_EVEN, T },
1019                 [C(RESULT_MISS)]        = { 12, CNTR_ODD, T },
1020         },
1021         [C(OP_WRITE)] = {
1022                 [C(RESULT_ACCESS)]      = { 12, CNTR_EVEN, T },
1023                 [C(RESULT_MISS)]        = { 12, CNTR_ODD, T },
1024         },
1025 },
1026 [C(L1I)] = {
1027         [C(OP_READ)] = {
1028                 [C(RESULT_ACCESS)]      = { 10, CNTR_EVEN, T },
1029                 [C(RESULT_MISS)]        = { 10, CNTR_ODD, T },
1030         },
1031         [C(OP_WRITE)] = {
1032                 [C(RESULT_ACCESS)]      = { 10, CNTR_EVEN, T },
1033                 [C(RESULT_MISS)]        = { 10, CNTR_ODD, T },
1034         },
1035         [C(OP_PREFETCH)] = {
1036                 [C(RESULT_ACCESS)]      = { 23, CNTR_EVEN, T },
1037                 /*
1038                  * Note that MIPS has only "hit" events countable for
1039                  * the prefetch operation.
1040                  */
1041         },
1042 },
1043 [C(LL)] = {
1044         [C(OP_READ)] = {
1045                 [C(RESULT_ACCESS)]      = { 28, CNTR_EVEN, P },
1046                 [C(RESULT_MISS)]        = { 28, CNTR_ODD, P },
1047         },
1048         [C(OP_WRITE)] = {
1049                 [C(RESULT_ACCESS)]      = { 28, CNTR_EVEN, P },
1050                 [C(RESULT_MISS)]        = { 28, CNTR_ODD, P },
1051         },
1052 },
1053 [C(BPU)] = {
1054         /* Using the same code for *HW_BRANCH* */
1055         [C(OP_READ)] = {
1056                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
1057         },
1058         [C(OP_WRITE)] = {
1059                 [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
1060         },
1061 },
1062 };
1063
1064
1065 static const struct mips_perf_event octeon_cache_map
1066                                 [PERF_COUNT_HW_CACHE_MAX]
1067                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1068                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1069 [C(L1D)] = {
1070         [C(OP_READ)] = {
1071                 [C(RESULT_ACCESS)]      = { 0x2b, CNTR_ALL },
1072                 [C(RESULT_MISS)]        = { 0x2e, CNTR_ALL },
1073         },
1074         [C(OP_WRITE)] = {
1075                 [C(RESULT_ACCESS)]      = { 0x30, CNTR_ALL },
1076         },
1077 },
1078 [C(L1I)] = {
1079         [C(OP_READ)] = {
1080                 [C(RESULT_ACCESS)]      = { 0x18, CNTR_ALL },
1081         },
1082         [C(OP_PREFETCH)] = {
1083                 [C(RESULT_ACCESS)]      = { 0x19, CNTR_ALL },
1084         },
1085 },
1086 [C(DTLB)] = {
1087         /*
1088          * Only general DTLB misses are counted use the same event for
1089          * read and write.
1090          */
1091         [C(OP_READ)] = {
1092                 [C(RESULT_MISS)]        = { 0x35, CNTR_ALL },
1093         },
1094         [C(OP_WRITE)] = {
1095                 [C(RESULT_MISS)]        = { 0x35, CNTR_ALL },
1096         },
1097 },
1098 [C(ITLB)] = {
1099         [C(OP_READ)] = {
1100                 [C(RESULT_MISS)]        = { 0x37, CNTR_ALL },
1101         },
1102 },
1103 };
1104
1105 static const struct mips_perf_event xlp_cache_map
1106                                 [PERF_COUNT_HW_CACHE_MAX]
1107                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1108                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1109 [C(L1D)] = {
1110         [C(OP_READ)] = {
1111                 [C(RESULT_ACCESS)]      = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1112                 [C(RESULT_MISS)]        = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1113         },
1114         [C(OP_WRITE)] = {
1115                 [C(RESULT_ACCESS)]      = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1116                 [C(RESULT_MISS)]        = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1117         },
1118         [C(OP_PREFETCH)] = {
1119                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1120                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1121         },
1122 },
1123 [C(L1I)] = {
1124         [C(OP_READ)] = {
1125                 [C(RESULT_ACCESS)]      = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1126                 [C(RESULT_MISS)]        = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1127         },
1128         [C(OP_WRITE)] = {
1129                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1130                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1131         },
1132         [C(OP_PREFETCH)] = {
1133                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1134                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1135         },
1136 },
1137 [C(LL)] = {
1138         [C(OP_READ)] = {
1139                 [C(RESULT_ACCESS)]      = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1140                 [C(RESULT_MISS)]        = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1141         },
1142         [C(OP_WRITE)] = {
1143                 [C(RESULT_ACCESS)]      = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1144                 [C(RESULT_MISS)]        = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1145         },
1146         [C(OP_PREFETCH)] = {
1147                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1148                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1149         },
1150 },
1151 [C(DTLB)] = {
1152         /*
1153          * Only general DTLB misses are counted use the same event for
1154          * read and write.
1155          */
1156         [C(OP_READ)] = {
1157                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1158                 [C(RESULT_MISS)]        = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1159         },
1160         [C(OP_WRITE)] = {
1161                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1162                 [C(RESULT_MISS)]        = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1163         },
1164         [C(OP_PREFETCH)] = {
1165                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1166                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1167         },
1168 },
1169 [C(ITLB)] = {
1170         [C(OP_READ)] = {
1171                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1172                 [C(RESULT_MISS)]        = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1173         },
1174         [C(OP_WRITE)] = {
1175                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1176                 [C(RESULT_MISS)]        = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1177         },
1178         [C(OP_PREFETCH)] = {
1179                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1180                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1181         },
1182 },
1183 [C(BPU)] = {
1184         [C(OP_READ)] = {
1185                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1186                 [C(RESULT_MISS)]        = { 0x25, CNTR_ALL },
1187         },
1188         [C(OP_WRITE)] = {
1189                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1190                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1191         },
1192         [C(OP_PREFETCH)] = {
1193                 [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
1194                 [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
1195         },
1196 },
1197 };
1198
1199 #ifdef CONFIG_MIPS_MT_SMP
1200 static void check_and_calc_range(struct perf_event *event,
1201                                  const struct mips_perf_event *pev)
1202 {
1203         struct hw_perf_event *hwc = &event->hw;
1204
1205         if (event->cpu >= 0) {
1206                 if (pev->range > V) {
1207                         /*
1208                          * The user selected an event that is processor
1209                          * wide, while expecting it to be VPE wide.
1210                          */
1211                         hwc->config_base |= M_TC_EN_ALL;
1212                 } else {
1213                         /*
1214                          * FIXME: cpu_data[event->cpu].vpe_id reports 0
1215                          * for both CPUs.
1216                          */
1217                         hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
1218                         hwc->config_base |= M_TC_EN_VPE;
1219                 }
1220         } else
1221                 hwc->config_base |= M_TC_EN_ALL;
1222 }
1223 #else
1224 static void check_and_calc_range(struct perf_event *event,
1225                                  const struct mips_perf_event *pev)
1226 {
1227 }
1228 #endif
1229
1230 static int __hw_perf_event_init(struct perf_event *event)
1231 {
1232         struct perf_event_attr *attr = &event->attr;
1233         struct hw_perf_event *hwc = &event->hw;
1234         const struct mips_perf_event *pev;
1235         int err;
1236
1237         /* Returning MIPS event descriptor for generic perf event. */
1238         if (PERF_TYPE_HARDWARE == event->attr.type) {
1239                 if (event->attr.config >= PERF_COUNT_HW_MAX)
1240                         return -EINVAL;
1241                 pev = mipspmu_map_general_event(event->attr.config);
1242         } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1243                 pev = mipspmu_map_cache_event(event->attr.config);
1244         } else if (PERF_TYPE_RAW == event->attr.type) {
1245                 /* We are working on the global raw event. */
1246                 mutex_lock(&raw_event_mutex);
1247                 pev = mipspmu.map_raw_event(event->attr.config);
1248         } else {
1249                 /* The event type is not (yet) supported. */
1250                 return -EOPNOTSUPP;
1251         }
1252
1253         if (IS_ERR(pev)) {
1254                 if (PERF_TYPE_RAW == event->attr.type)
1255                         mutex_unlock(&raw_event_mutex);
1256                 return PTR_ERR(pev);
1257         }
1258
1259         /*
1260          * We allow max flexibility on how each individual counter shared
1261          * by the single CPU operates (the mode exclusion and the range).
1262          */
1263         hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
1264
1265         /* Calculate range bits and validate it. */
1266         if (num_possible_cpus() > 1)
1267                 check_and_calc_range(event, pev);
1268
1269         hwc->event_base = mipspmu_perf_event_encode(pev);
1270         if (PERF_TYPE_RAW == event->attr.type)
1271                 mutex_unlock(&raw_event_mutex);
1272
1273         if (!attr->exclude_user)
1274                 hwc->config_base |= M_PERFCTL_USER;
1275         if (!attr->exclude_kernel) {
1276                 hwc->config_base |= M_PERFCTL_KERNEL;
1277                 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1278                 hwc->config_base |= M_PERFCTL_EXL;
1279         }
1280         if (!attr->exclude_hv)
1281                 hwc->config_base |= M_PERFCTL_SUPERVISOR;
1282
1283         hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1284         /*
1285          * The event can belong to another cpu. We do not assign a local
1286          * counter for it for now.
1287          */
1288         hwc->idx = -1;
1289         hwc->config = 0;
1290
1291         if (!hwc->sample_period) {
1292                 hwc->sample_period  = mipspmu.max_period;
1293                 hwc->last_period    = hwc->sample_period;
1294                 local64_set(&hwc->period_left, hwc->sample_period);
1295         }
1296
1297         err = 0;
1298         if (event->group_leader != event)
1299                 err = validate_group(event);
1300
1301         event->destroy = hw_perf_event_destroy;
1302
1303         if (err)
1304                 event->destroy(event);
1305
1306         return err;
1307 }
1308
1309 static void pause_local_counters(void)
1310 {
1311         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1312         int ctr = mipspmu.num_counters;
1313         unsigned long flags;
1314
1315         local_irq_save(flags);
1316         do {
1317                 ctr--;
1318                 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1319                 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1320                                          ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1321         } while (ctr > 0);
1322         local_irq_restore(flags);
1323 }
1324
1325 static void resume_local_counters(void)
1326 {
1327         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1328         int ctr = mipspmu.num_counters;
1329
1330         do {
1331                 ctr--;
1332                 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1333         } while (ctr > 0);
1334 }
1335
1336 static int mipsxx_pmu_handle_shared_irq(void)
1337 {
1338         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1339         struct perf_sample_data data;
1340         unsigned int counters = mipspmu.num_counters;
1341         u64 counter;
1342         int handled = IRQ_NONE;
1343         struct pt_regs *regs;
1344
1345         if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
1346                 return handled;
1347         /*
1348          * First we pause the local counters, so that when we are locked
1349          * here, the counters are all paused. When it gets locked due to
1350          * perf_disable(), the timer interrupt handler will be delayed.
1351          *
1352          * See also mipsxx_pmu_start().
1353          */
1354         pause_local_counters();
1355 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1356         read_lock(&pmuint_rwlock);
1357 #endif
1358
1359         regs = get_irq_regs();
1360
1361         perf_sample_data_init(&data, 0, 0);
1362
1363         switch (counters) {
1364 #define HANDLE_COUNTER(n)                                               \
1365         case n + 1:                                                     \
1366                 if (test_bit(n, cpuc->used_mask)) {                     \
1367                         counter = mipspmu.read_counter(n);              \
1368                         if (counter & mipspmu.overflow) {               \
1369                                 handle_associated_event(cpuc, n, &data, regs); \
1370                                 handled = IRQ_HANDLED;                  \
1371                         }                                               \
1372                 }
1373         HANDLE_COUNTER(3)
1374         HANDLE_COUNTER(2)
1375         HANDLE_COUNTER(1)
1376         HANDLE_COUNTER(0)
1377         }
1378
1379         /*
1380          * Do all the work for the pending perf events. We can do this
1381          * in here because the performance counter interrupt is a regular
1382          * interrupt, not NMI.
1383          */
1384         if (handled == IRQ_HANDLED)
1385                 irq_work_run();
1386
1387 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1388         read_unlock(&pmuint_rwlock);
1389 #endif
1390         resume_local_counters();
1391         return handled;
1392 }
1393
1394 static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1395 {
1396         return mipsxx_pmu_handle_shared_irq();
1397 }
1398
1399 /* 24K */
1400 #define IS_BOTH_COUNTERS_24K_EVENT(b)                                   \
1401         ((b) == 0 || (b) == 1 || (b) == 11)
1402
1403 /* 34K */
1404 #define IS_BOTH_COUNTERS_34K_EVENT(b)                                   \
1405         ((b) == 0 || (b) == 1 || (b) == 11)
1406 #ifdef CONFIG_MIPS_MT_SMP
1407 #define IS_RANGE_P_34K_EVENT(r, b)                                      \
1408         ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
1409          (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 ||           \
1410          (r) == 176 || ((b) >= 50 && (b) <= 55) ||                      \
1411          ((b) >= 64 && (b) <= 67))
1412 #define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1413 #endif
1414
1415 /* 74K */
1416 #define IS_BOTH_COUNTERS_74K_EVENT(b)                                   \
1417         ((b) == 0 || (b) == 1)
1418
1419 /* 1004K */
1420 #define IS_BOTH_COUNTERS_1004K_EVENT(b)                                 \
1421         ((b) == 0 || (b) == 1 || (b) == 11)
1422 #ifdef CONFIG_MIPS_MT_SMP
1423 #define IS_RANGE_P_1004K_EVENT(r, b)                                    \
1424         ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
1425          (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 ||            \
1426          (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) ||        \
1427          (r) == 188 || (b) == 61 || (b) == 62 ||                        \
1428          ((b) >= 64 && (b) <= 67))
1429 #define IS_RANGE_V_1004K_EVENT(r)       ((r) == 47)
1430 #endif
1431
1432 /* BMIPS5000 */
1433 #define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b)                             \
1434         ((b) == 0 || (b) == 1)
1435
1436
1437 /*
1438  * User can use 0-255 raw events, where 0-127 for the events of even
1439  * counters, and 128-255 for odd counters. Note that bit 7 is used to
1440  * indicate the parity. So, for example, when user wants to take the
1441  * Event Num of 15 for odd counters (by referring to the user manual),
1442  * then 128 needs to be added to 15 as the input for the event config,
1443  * i.e., 143 (0x8F) to be used.
1444  */
1445 static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1446 {
1447         unsigned int raw_id = config & 0xff;
1448         unsigned int base_id = raw_id & 0x7f;
1449
1450         raw_event.event_id = base_id;
1451
1452         switch (current_cpu_type()) {
1453         case CPU_24K:
1454                 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1455                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1456                 else
1457                         raw_event.cntr_mask =
1458                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1459 #ifdef CONFIG_MIPS_MT_SMP
1460                 /*
1461                  * This is actually doing nothing. Non-multithreading
1462                  * CPUs will not check and calculate the range.
1463                  */
1464                 raw_event.range = P;
1465 #endif
1466                 break;
1467         case CPU_34K:
1468                 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1469                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1470                 else
1471                         raw_event.cntr_mask =
1472                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1473 #ifdef CONFIG_MIPS_MT_SMP
1474                 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1475                         raw_event.range = P;
1476                 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1477                         raw_event.range = V;
1478                 else
1479                         raw_event.range = T;
1480 #endif
1481                 break;
1482         case CPU_74K:
1483                 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1484                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1485                 else
1486                         raw_event.cntr_mask =
1487                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1488 #ifdef CONFIG_MIPS_MT_SMP
1489                 raw_event.range = P;
1490 #endif
1491                 break;
1492         case CPU_1004K:
1493                 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1494                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1495                 else
1496                         raw_event.cntr_mask =
1497                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1498 #ifdef CONFIG_MIPS_MT_SMP
1499                 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1500                         raw_event.range = P;
1501                 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1502                         raw_event.range = V;
1503                 else
1504                         raw_event.range = T;
1505 #endif
1506                 break;
1507         case CPU_BMIPS5000:
1508                 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
1509                         raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1510                 else
1511                         raw_event.cntr_mask =
1512                                 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1513         }
1514
1515         return &raw_event;
1516 }
1517
1518 static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1519 {
1520         unsigned int raw_id = config & 0xff;
1521         unsigned int base_id = raw_id & 0x7f;
1522
1523
1524         raw_event.cntr_mask = CNTR_ALL;
1525         raw_event.event_id = base_id;
1526
1527         if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
1528                 if (base_id > 0x42)
1529                         return ERR_PTR(-EOPNOTSUPP);
1530         } else {
1531                 if (base_id > 0x3a)
1532                         return ERR_PTR(-EOPNOTSUPP);
1533         }
1534
1535         switch (base_id) {
1536         case 0x00:
1537         case 0x0f:
1538         case 0x1e:
1539         case 0x1f:
1540         case 0x2f:
1541         case 0x34:
1542         case 0x3b ... 0x3f:
1543                 return ERR_PTR(-EOPNOTSUPP);
1544         default:
1545                 break;
1546         }
1547
1548         return &raw_event;
1549 }
1550
1551 static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
1552 {
1553         unsigned int raw_id = config & 0xff;
1554
1555         /* Only 1-63 are defined */
1556         if ((raw_id < 0x01) || (raw_id > 0x3f))
1557                 return ERR_PTR(-EOPNOTSUPP);
1558
1559         raw_event.cntr_mask = CNTR_ALL;
1560         raw_event.event_id = raw_id;
1561
1562         return &raw_event;
1563 }
1564
1565 static int __init
1566 init_hw_perf_events(void)
1567 {
1568         int counters, irq;
1569         int counter_bits;
1570
1571         pr_info("Performance counters: ");
1572
1573         counters = n_counters();
1574         if (counters == 0) {
1575                 pr_cont("No available PMU.\n");
1576                 return -ENODEV;
1577         }
1578
1579 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1580         cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
1581         if (!cpu_has_mipsmt_pertccounters)
1582                 counters = counters_total_to_per_cpu(counters);
1583 #endif
1584
1585 #ifdef MSC01E_INT_BASE
1586         if (cpu_has_veic) {
1587                 /*
1588                  * Using platform specific interrupt controller defines.
1589                  */
1590                 irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
1591         } else {
1592 #endif
1593                 if ((cp0_perfcount_irq >= 0) &&
1594                                 (cp0_compare_irq != cp0_perfcount_irq))
1595                         irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1596                 else
1597                         irq = -1;
1598 #ifdef MSC01E_INT_BASE
1599         }
1600 #endif
1601
1602         mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1603
1604         switch (current_cpu_type()) {
1605         case CPU_24K:
1606                 mipspmu.name = "mips/24K";
1607                 mipspmu.general_event_map = &mipsxxcore_event_map;
1608                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1609                 break;
1610         case CPU_34K:
1611                 mipspmu.name = "mips/34K";
1612                 mipspmu.general_event_map = &mipsxxcore_event_map;
1613                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1614                 break;
1615         case CPU_74K:
1616                 mipspmu.name = "mips/74K";
1617                 mipspmu.general_event_map = &mipsxx74Kcore_event_map;
1618                 mipspmu.cache_event_map = &mipsxx74Kcore_cache_map;
1619                 break;
1620         case CPU_1004K:
1621                 mipspmu.name = "mips/1004K";
1622                 mipspmu.general_event_map = &mipsxxcore_event_map;
1623                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1624                 break;
1625         case CPU_LOONGSON1:
1626                 mipspmu.name = "mips/loongson1";
1627                 mipspmu.general_event_map = &mipsxxcore_event_map;
1628                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1629                 break;
1630         case CPU_CAVIUM_OCTEON:
1631         case CPU_CAVIUM_OCTEON_PLUS:
1632         case CPU_CAVIUM_OCTEON2:
1633                 mipspmu.name = "octeon";
1634                 mipspmu.general_event_map = &octeon_event_map;
1635                 mipspmu.cache_event_map = &octeon_cache_map;
1636                 mipspmu.map_raw_event = octeon_pmu_map_raw_event;
1637                 break;
1638         case CPU_BMIPS5000:
1639                 mipspmu.name = "BMIPS5000";
1640                 mipspmu.general_event_map = &bmips5000_event_map;
1641                 mipspmu.cache_event_map = &bmips5000_cache_map;
1642                 break;
1643         case CPU_XLP:
1644                 mipspmu.name = "xlp";
1645                 mipspmu.general_event_map = &xlp_event_map;
1646                 mipspmu.cache_event_map = &xlp_cache_map;
1647                 mipspmu.map_raw_event = xlp_pmu_map_raw_event;
1648                 break;
1649         default:
1650                 pr_cont("Either hardware does not support performance "
1651                         "counters, or not yet implemented.\n");
1652                 return -ENODEV;
1653         }
1654
1655         mipspmu.num_counters = counters;
1656         mipspmu.irq = irq;
1657
1658         if (read_c0_perfctrl0() & M_PERFCTL_WIDE) {
1659                 mipspmu.max_period = (1ULL << 63) - 1;
1660                 mipspmu.valid_count = (1ULL << 63) - 1;
1661                 mipspmu.overflow = 1ULL << 63;
1662                 mipspmu.read_counter = mipsxx_pmu_read_counter_64;
1663                 mipspmu.write_counter = mipsxx_pmu_write_counter_64;
1664                 counter_bits = 64;
1665         } else {
1666                 mipspmu.max_period = (1ULL << 31) - 1;
1667                 mipspmu.valid_count = (1ULL << 31) - 1;
1668                 mipspmu.overflow = 1ULL << 31;
1669                 mipspmu.read_counter = mipsxx_pmu_read_counter;
1670                 mipspmu.write_counter = mipsxx_pmu_write_counter;
1671                 counter_bits = 32;
1672         }
1673
1674         on_each_cpu(reset_counters, (void *)(long)counters, 1);
1675
1676         pr_cont("%s PMU enabled, %d %d-bit counters available to each "
1677                 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
1678                 irq < 0 ? " (share with timer interrupt)" : "");
1679
1680         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1681
1682         return 0;
1683 }
1684 early_initcall(init_hw_perf_events);