1 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
2 defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
4 #define M_CONFIG1_PC (1 << 4)
6 #define M_PERFCTL_EXL (1UL << 0)
7 #define M_PERFCTL_KERNEL (1UL << 1)
8 #define M_PERFCTL_SUPERVISOR (1UL << 2)
9 #define M_PERFCTL_USER (1UL << 3)
10 #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
11 #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
12 #define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
13 #define M_PERFCTL_MT_EN(filter) ((filter) << 20)
14 #define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
15 #define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
16 #define M_TC_EN_TC M_PERFCTL_MT_EN(2)
17 #define M_PERFCTL_TCID(tcid) ((tcid) << 22)
18 #define M_PERFCTL_WIDE (1UL << 30)
19 #define M_PERFCTL_MORE (1UL << 31)
21 #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \
24 M_PERFCTL_SUPERVISOR | \
25 M_PERFCTL_INTERRUPT_ENABLE)
27 #ifdef CONFIG_MIPS_MT_SMP
28 #define M_PERFCTL_CONFIG_MASK 0x3fff801f
30 #define M_PERFCTL_CONFIG_MASK 0x1f
32 #define M_PERFCTL_EVENT_MASK 0xfe0
34 #define M_COUNTER_OVERFLOW (1UL << 31)
36 #ifdef CONFIG_MIPS_MT_SMP
37 static int cpu_has_mipsmt_pertccounters;
40 * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
41 * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
43 #if defined(CONFIG_HW_PERF_EVENTS)
44 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
45 0 : smp_processor_id())
47 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
48 0 : cpu_data[smp_processor_id()].vpe_id)
51 /* Copied from op_model_mipsxx.c */
52 static inline unsigned int vpe_shift(void)
54 if (num_possible_cpus() > 1)
59 #else /* !CONFIG_MIPS_MT_SMP */
62 static inline unsigned int vpe_shift(void)
66 #endif /* CONFIG_MIPS_MT_SMP */
68 static inline unsigned int
69 counters_total_to_per_cpu(unsigned int counters)
71 return counters >> vpe_shift();
74 static inline unsigned int
75 counters_per_cpu_to_total(unsigned int counters)
77 return counters << vpe_shift();
80 #define __define_perf_accessors(r, n, np) \
82 static inline unsigned int r_c0_ ## r ## n(void) \
84 unsigned int cpu = vpe_id(); \
88 return read_c0_ ## r ## n(); \
90 return read_c0_ ## r ## np(); \
97 static inline void w_c0_ ## r ## n(unsigned int value) \
99 unsigned int cpu = vpe_id(); \
103 write_c0_ ## r ## n(value); \
106 write_c0_ ## r ## np(value); \
114 __define_perf_accessors(perfcntr, 0, 2)
115 __define_perf_accessors(perfcntr, 1, 3)
116 __define_perf_accessors(perfcntr, 2, 0)
117 __define_perf_accessors(perfcntr, 3, 1)
119 __define_perf_accessors(perfctrl, 0, 2)
120 __define_perf_accessors(perfctrl, 1, 3)
121 __define_perf_accessors(perfctrl, 2, 0)
122 __define_perf_accessors(perfctrl, 3, 1)
124 static inline int __n_counters(void)
126 if (!(read_c0_config1() & M_CONFIG1_PC))
128 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
130 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
132 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
138 static inline int n_counters(void)
142 switch (current_cpu_type()) {
153 counters = __n_counters();
159 static void reset_counters(void *arg)
161 int counters = (int)(long)arg;
179 mipsxx_pmu_read_counter(unsigned int idx)
183 return r_c0_perfcntr0();
185 return r_c0_perfcntr1();
187 return r_c0_perfcntr2();
189 return r_c0_perfcntr3();
191 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
197 mipsxx_pmu_write_counter(unsigned int idx, u64 val)
215 static inline unsigned int
216 mipsxx_pmu_read_control(unsigned int idx)
220 return r_c0_perfctrl0();
222 return r_c0_perfctrl1();
224 return r_c0_perfctrl2();
226 return r_c0_perfctrl3();
228 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
234 mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
252 #ifdef CONFIG_MIPS_MT_SMP
253 static DEFINE_RWLOCK(pmuint_rwlock);
256 /* 24K/34K/1004K cores can share the same event map. */
257 static const struct mips_perf_event mipsxxcore_event_map
258 [PERF_COUNT_HW_MAX] = {
259 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
260 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
261 [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
262 [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
263 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
264 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
265 [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
268 /* 74K core has different branch event code. */
269 static const struct mips_perf_event mipsxx74Kcore_event_map
270 [PERF_COUNT_HW_MAX] = {
271 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
272 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
273 [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
274 [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
275 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
276 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
277 [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
280 /* 24K/34K/1004K cores can share the same cache event map. */
281 static const struct mips_perf_event mipsxxcore_cache_map
282 [PERF_COUNT_HW_CACHE_MAX]
283 [PERF_COUNT_HW_CACHE_OP_MAX]
284 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
287 * Like some other architectures (e.g. ARM), the performance
288 * counters don't differentiate between read and write
289 * accesses/misses, so this isn't strictly correct, but it's the
290 * best we can do. Writes and reads get combined.
293 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
294 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
297 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
298 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
301 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
302 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
307 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
308 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
311 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
312 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
315 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
317 * Note that MIPS has only "hit" events countable for
318 * the prefetch operation.
320 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
325 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
326 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
329 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
330 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
333 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
334 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
339 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
340 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
343 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
344 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
347 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
348 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
353 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
354 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
357 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
358 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
361 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
362 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
366 /* Using the same code for *HW_BRANCH* */
368 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
369 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
372 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
373 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
376 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
377 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
382 /* 74K core has completely different cache event map. */
383 static const struct mips_perf_event mipsxx74Kcore_cache_map
384 [PERF_COUNT_HW_CACHE_MAX]
385 [PERF_COUNT_HW_CACHE_OP_MAX]
386 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
389 * Like some other architectures (e.g. ARM), the performance
390 * counters don't differentiate between read and write
391 * accesses/misses, so this isn't strictly correct, but it's the
392 * best we can do. Writes and reads get combined.
395 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
396 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
399 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
400 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
403 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
404 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
409 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
410 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
413 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
414 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
417 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
419 * Note that MIPS has only "hit" events countable for
420 * the prefetch operation.
422 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
427 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
428 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
431 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
432 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
435 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
436 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
440 /* 74K core does not have specific DTLB events. */
442 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
443 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
446 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
447 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
450 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
451 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
456 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
457 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
460 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
461 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
464 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
465 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
469 /* Using the same code for *HW_BRANCH* */
471 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
472 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
475 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
476 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
479 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
480 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
485 #ifdef CONFIG_MIPS_MT_SMP
487 check_and_calc_range(struct perf_event *event,
488 const struct mips_perf_event *pev)
490 struct hw_perf_event *hwc = &event->hw;
492 if (event->cpu >= 0) {
493 if (pev->range > V) {
495 * The user selected an event that is processor
496 * wide, while expecting it to be VPE wide.
498 hwc->config_base |= M_TC_EN_ALL;
501 * FIXME: cpu_data[event->cpu].vpe_id reports 0
504 hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
505 hwc->config_base |= M_TC_EN_VPE;
508 hwc->config_base |= M_TC_EN_ALL;
512 check_and_calc_range(struct perf_event *event,
513 const struct mips_perf_event *pev)
518 static int __hw_perf_event_init(struct perf_event *event)
520 struct perf_event_attr *attr = &event->attr;
521 struct hw_perf_event *hwc = &event->hw;
522 const struct mips_perf_event *pev;
525 /* Returning MIPS event descriptor for generic perf event. */
526 if (PERF_TYPE_HARDWARE == event->attr.type) {
527 if (event->attr.config >= PERF_COUNT_HW_MAX)
529 pev = mipspmu_map_general_event(event->attr.config);
530 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
531 pev = mipspmu_map_cache_event(event->attr.config);
532 } else if (PERF_TYPE_RAW == event->attr.type) {
533 /* We are working on the global raw event. */
534 mutex_lock(&raw_event_mutex);
535 pev = mipspmu->map_raw_event(event->attr.config);
537 /* The event type is not (yet) supported. */
542 if (PERF_TYPE_RAW == event->attr.type)
543 mutex_unlock(&raw_event_mutex);
548 * We allow max flexibility on how each individual counter shared
549 * by the single CPU operates (the mode exclusion and the range).
551 hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
553 /* Calculate range bits and validate it. */
554 if (num_possible_cpus() > 1)
555 check_and_calc_range(event, pev);
557 hwc->event_base = mipspmu_perf_event_encode(pev);
558 if (PERF_TYPE_RAW == event->attr.type)
559 mutex_unlock(&raw_event_mutex);
561 if (!attr->exclude_user)
562 hwc->config_base |= M_PERFCTL_USER;
563 if (!attr->exclude_kernel) {
564 hwc->config_base |= M_PERFCTL_KERNEL;
565 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
566 hwc->config_base |= M_PERFCTL_EXL;
568 if (!attr->exclude_hv)
569 hwc->config_base |= M_PERFCTL_SUPERVISOR;
571 hwc->config_base &= M_PERFCTL_CONFIG_MASK;
573 * The event can belong to another cpu. We do not assign a local
574 * counter for it for now.
579 if (!hwc->sample_period) {
580 hwc->sample_period = MAX_PERIOD;
581 hwc->last_period = hwc->sample_period;
582 local64_set(&hwc->period_left, hwc->sample_period);
586 if (event->group_leader != event) {
587 err = validate_group(event);
592 event->destroy = hw_perf_event_destroy;
597 static void pause_local_counters(void)
599 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
600 int counters = mipspmu->num_counters;
603 local_irq_save(flags);
606 cpuc->saved_ctrl[3] = r_c0_perfctrl3();
607 w_c0_perfctrl3(cpuc->saved_ctrl[3] &
608 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
610 cpuc->saved_ctrl[2] = r_c0_perfctrl2();
611 w_c0_perfctrl2(cpuc->saved_ctrl[2] &
612 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
614 cpuc->saved_ctrl[1] = r_c0_perfctrl1();
615 w_c0_perfctrl1(cpuc->saved_ctrl[1] &
616 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
618 cpuc->saved_ctrl[0] = r_c0_perfctrl0();
619 w_c0_perfctrl0(cpuc->saved_ctrl[0] &
620 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
622 local_irq_restore(flags);
625 static void resume_local_counters(void)
627 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
628 int counters = mipspmu->num_counters;
631 local_irq_save(flags);
634 w_c0_perfctrl3(cpuc->saved_ctrl[3]);
636 w_c0_perfctrl2(cpuc->saved_ctrl[2]);
638 w_c0_perfctrl1(cpuc->saved_ctrl[1]);
640 w_c0_perfctrl0(cpuc->saved_ctrl[0]);
642 local_irq_restore(flags);
645 static int mipsxx_pmu_handle_shared_irq(void)
647 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
648 struct perf_sample_data data;
649 unsigned int counters = mipspmu->num_counters;
650 unsigned int counter;
651 int handled = IRQ_NONE;
652 struct pt_regs *regs;
654 if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
658 * First we pause the local counters, so that when we are locked
659 * here, the counters are all paused. When it gets locked due to
660 * perf_disable(), the timer interrupt handler will be delayed.
662 * See also mipsxx_pmu_start().
664 pause_local_counters();
665 #ifdef CONFIG_MIPS_MT_SMP
666 read_lock(&pmuint_rwlock);
669 regs = get_irq_regs();
671 perf_sample_data_init(&data, 0);
674 #define HANDLE_COUNTER(n) \
676 if (test_bit(n, cpuc->used_mask)) { \
677 counter = r_c0_perfcntr ## n(); \
678 if (counter & M_COUNTER_OVERFLOW) { \
679 w_c0_perfcntr ## n(counter & \
681 if (test_and_change_bit(n, cpuc->msbs)) \
682 handle_associated_event(cpuc, \
684 handled = IRQ_HANDLED; \
694 * Do all the work for the pending perf events. We can do this
695 * in here because the performance counter interrupt is a regular
696 * interrupt, not NMI.
698 if (handled == IRQ_HANDLED)
701 #ifdef CONFIG_MIPS_MT_SMP
702 read_unlock(&pmuint_rwlock);
704 resume_local_counters();
709 mipsxx_pmu_handle_irq(int irq, void *dev)
711 return mipsxx_pmu_handle_shared_irq();
714 static void mipsxx_pmu_start(void)
716 #ifdef CONFIG_MIPS_MT_SMP
717 write_unlock(&pmuint_rwlock);
719 resume_local_counters();
723 * MIPS performance counters can be per-TC. The control registers can
724 * not be directly accessed across CPUs. Hence if we want to do global
725 * control, we need cross CPU calls. on_each_cpu() can help us, but we
726 * can not make sure this function is called with interrupts enabled. So
727 * here we pause local counters and then grab a rwlock and leave the
728 * counters on other CPUs alone. If any counter interrupt raises while
729 * we own the write lock, simply pause local counters on that CPU and
730 * spin in the handler. Also we know we won't be switched to another
731 * CPU after pausing local counters and before grabbing the lock.
733 static void mipsxx_pmu_stop(void)
735 pause_local_counters();
736 #ifdef CONFIG_MIPS_MT_SMP
737 write_lock(&pmuint_rwlock);
742 mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
743 struct hw_perf_event *hwc)
748 * We only need to care the counter mask. The range has been
749 * checked definitely.
751 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
753 for (i = mipspmu->num_counters - 1; i >= 0; i--) {
755 * Note that some MIPS perf events can be counted by both
756 * even and odd counters, wheresas many other are only by
757 * even _or_ odd counters. This introduces an issue that
758 * when the former kind of event takes the counter the
759 * latter kind of event wants to use, then the "counter
760 * allocation" for the latter event will fail. In fact if
761 * they can be dynamically swapped, they both feel happy.
762 * But here we leave this issue alone for now.
764 if (test_bit(i, &cntr_mask) &&
765 !test_and_set_bit(i, cpuc->used_mask))
773 mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
775 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
778 WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
780 local_irq_save(flags);
781 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
782 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
783 /* Make sure interrupt enabled. */
784 M_PERFCTL_INTERRUPT_ENABLE;
786 * We do not actually let the counter run. Leave it until start().
788 local_irq_restore(flags);
792 mipsxx_pmu_disable_event(int idx)
794 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
797 WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
799 local_irq_save(flags);
800 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
801 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
802 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
803 local_irq_restore(flags);
807 #define IS_UNSUPPORTED_24K_EVENT(r, b) \
808 ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \
809 (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 || \
810 (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 || \
811 (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) || \
812 ((b) >= 68 && (b) <= 127))
813 #define IS_BOTH_COUNTERS_24K_EVENT(b) \
814 ((b) == 0 || (b) == 1 || (b) == 11)
817 #define IS_UNSUPPORTED_34K_EVENT(r, b) \
818 ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 || \
819 (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) || \
820 ((b) >= 68 && (b) <= 127))
821 #define IS_BOTH_COUNTERS_34K_EVENT(b) \
822 ((b) == 0 || (b) == 1 || (b) == 11)
823 #ifdef CONFIG_MIPS_MT_SMP
824 #define IS_RANGE_P_34K_EVENT(r, b) \
825 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
826 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
827 (r) == 176 || ((b) >= 50 && (b) <= 55) || \
828 ((b) >= 64 && (b) <= 67))
829 #define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
833 #define IS_UNSUPPORTED_74K_EVENT(r, b) \
834 ((r) == 5 || ((r) >= 135 && (r) <= 137) || \
835 ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 || \
836 (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) || \
837 (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 || \
838 (b) == 61 || (r) == 62 || (r) == 191 || \
839 ((b) >= 64 && (b) <= 127))
840 #define IS_BOTH_COUNTERS_74K_EVENT(b) \
841 ((b) == 0 || (b) == 1)
844 #define IS_UNSUPPORTED_1004K_EVENT(r, b) \
845 ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 || \
846 (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
847 #define IS_BOTH_COUNTERS_1004K_EVENT(b) \
848 ((b) == 0 || (b) == 1 || (b) == 11)
849 #ifdef CONFIG_MIPS_MT_SMP
850 #define IS_RANGE_P_1004K_EVENT(r, b) \
851 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
852 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \
853 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \
854 (r) == 188 || (b) == 61 || (b) == 62 || \
855 ((b) >= 64 && (b) <= 67))
856 #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
860 * User can use 0-255 raw events, where 0-127 for the events of even
861 * counters, and 128-255 for odd counters. Note that bit 7 is used to
862 * indicate the parity. So, for example, when user wants to take the
863 * Event Num of 15 for odd counters (by referring to the user manual),
864 * then 128 needs to be added to 15 as the input for the event config,
865 * i.e., 143 (0x8F) to be used.
867 static const struct mips_perf_event *
868 mipsxx_pmu_map_raw_event(u64 config)
870 unsigned int raw_id = config & 0xff;
871 unsigned int base_id = raw_id & 0x7f;
873 switch (current_cpu_type()) {
875 if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
876 return ERR_PTR(-EOPNOTSUPP);
877 raw_event.event_id = base_id;
878 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
879 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
881 raw_event.cntr_mask =
882 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
883 #ifdef CONFIG_MIPS_MT_SMP
885 * This is actually doing nothing. Non-multithreading
886 * CPUs will not check and calculate the range.
892 if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
893 return ERR_PTR(-EOPNOTSUPP);
894 raw_event.event_id = base_id;
895 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
896 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
898 raw_event.cntr_mask =
899 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
900 #ifdef CONFIG_MIPS_MT_SMP
901 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
903 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
910 if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
911 return ERR_PTR(-EOPNOTSUPP);
912 raw_event.event_id = base_id;
913 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
914 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
916 raw_event.cntr_mask =
917 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
918 #ifdef CONFIG_MIPS_MT_SMP
923 if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
924 return ERR_PTR(-EOPNOTSUPP);
925 raw_event.event_id = base_id;
926 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
927 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
929 raw_event.cntr_mask =
930 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
931 #ifdef CONFIG_MIPS_MT_SMP
932 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
934 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
945 static struct mips_pmu mipsxxcore_pmu = {
946 .handle_irq = mipsxx_pmu_handle_irq,
947 .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
948 .start = mipsxx_pmu_start,
949 .stop = mipsxx_pmu_stop,
950 .alloc_counter = mipsxx_pmu_alloc_counter,
951 .read_counter = mipsxx_pmu_read_counter,
952 .write_counter = mipsxx_pmu_write_counter,
953 .enable_event = mipsxx_pmu_enable_event,
954 .disable_event = mipsxx_pmu_disable_event,
955 .map_raw_event = mipsxx_pmu_map_raw_event,
956 .general_event_map = &mipsxxcore_event_map,
957 .cache_event_map = &mipsxxcore_cache_map,
960 static struct mips_pmu mipsxx74Kcore_pmu = {
961 .handle_irq = mipsxx_pmu_handle_irq,
962 .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
963 .start = mipsxx_pmu_start,
964 .stop = mipsxx_pmu_stop,
965 .alloc_counter = mipsxx_pmu_alloc_counter,
966 .read_counter = mipsxx_pmu_read_counter,
967 .write_counter = mipsxx_pmu_write_counter,
968 .enable_event = mipsxx_pmu_enable_event,
969 .disable_event = mipsxx_pmu_disable_event,
970 .map_raw_event = mipsxx_pmu_map_raw_event,
971 .general_event_map = &mipsxx74Kcore_event_map,
972 .cache_event_map = &mipsxx74Kcore_cache_map,
976 init_hw_perf_events(void)
980 pr_info("Performance counters: ");
982 counters = n_counters();
984 pr_cont("No available PMU.\n");
988 #ifdef CONFIG_MIPS_MT_SMP
989 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
990 if (!cpu_has_mipsmt_pertccounters)
991 counters = counters_total_to_per_cpu(counters);
994 #ifdef MSC01E_INT_BASE
997 * Using platform specific interrupt controller defines.
999 irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
1002 if (cp0_perfcount_irq >= 0)
1003 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1006 #ifdef MSC01E_INT_BASE
1010 on_each_cpu(reset_counters, (void *)(long)counters, 1);
1012 switch (current_cpu_type()) {
1014 mipsxxcore_pmu.name = "mips/24K";
1015 mipsxxcore_pmu.num_counters = counters;
1016 mipsxxcore_pmu.irq = irq;
1017 mipspmu = &mipsxxcore_pmu;
1020 mipsxxcore_pmu.name = "mips/34K";
1021 mipsxxcore_pmu.num_counters = counters;
1022 mipsxxcore_pmu.irq = irq;
1023 mipspmu = &mipsxxcore_pmu;
1026 mipsxx74Kcore_pmu.name = "mips/74K";
1027 mipsxx74Kcore_pmu.num_counters = counters;
1028 mipsxx74Kcore_pmu.irq = irq;
1029 mipspmu = &mipsxx74Kcore_pmu;
1032 mipsxxcore_pmu.name = "mips/1004K";
1033 mipsxxcore_pmu.num_counters = counters;
1034 mipsxxcore_pmu.irq = irq;
1035 mipspmu = &mipsxxcore_pmu;
1038 pr_cont("Either hardware does not support performance "
1039 "counters, or not yet implemented.\n");
1044 pr_cont("%s PMU enabled, %d counters available to each "
1045 "CPU, irq %d%s\n", mipspmu->name, counters, irq,
1046 irq < 0 ? " (share with timer interrupt)" : "");
1048 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1052 early_initcall(init_hw_perf_events);
1054 #endif /* defined(CONFIG_CPU_MIPS32)... */