2 * Linux performance counter support for MIPS.
4 * Copyright (C) 2010 MIPS Technologies, Inc.
5 * Copyright (C) 2011 Cavium Networks, Inc.
6 * Author: Deng-Cheng Zhu
8 * This code is based on the implementation for ARM, which is in turn
9 * based on the sparc64 perf event code and the x86 code. Performance
10 * counter access is based on the MIPS Oprofile code. And the callchain
11 * support references the code of MIPS stacktrace.c.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/cpumask.h>
19 #include <linux/interrupt.h>
20 #include <linux/smp.h>
21 #include <linux/kernel.h>
22 #include <linux/perf_event.h>
23 #include <linux/uaccess.h>
26 #include <asm/irq_regs.h>
27 #include <asm/stacktrace.h>
28 #include <asm/time.h> /* For perf_irq */
30 #define MIPS_MAX_HWEVENTS 4
31 #define MIPS_TCS_PER_COUNTER 2
32 #define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1)
34 struct cpu_hw_events {
35 /* Array of events on this cpu. */
36 struct perf_event *events[MIPS_MAX_HWEVENTS];
39 * Set the bit (indexed by the counter number) when the counter
40 * is used for an event.
42 unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
45 * Software copy of the control register for each performance counter.
46 * MIPS CPUs vary in performance counters. They use this differently,
47 * and even may not use it.
49 unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
51 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 /* The description of MIPS performance events. */
56 struct mips_perf_event {
57 unsigned int event_id;
59 * MIPS performance counters are indexed starting from 0.
60 * CNTR_EVEN indicates the indexes of the counters to be used are
63 unsigned int cntr_mask;
64 #define CNTR_EVEN 0x55555555
65 #define CNTR_ODD 0xaaaaaaaa
66 #define CNTR_ALL 0xffffffff
67 #ifdef CONFIG_MIPS_MT_SMP
80 static struct mips_perf_event raw_event;
81 static DEFINE_MUTEX(raw_event_mutex);
83 #define C(x) PERF_COUNT_HW_CACHE_##x
91 u64 (*read_counter)(unsigned int idx);
92 void (*write_counter)(unsigned int idx, u64 val);
93 const struct mips_perf_event *(*map_raw_event)(u64 config);
94 const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
95 const struct mips_perf_event (*cache_event_map)
96 [PERF_COUNT_HW_CACHE_MAX]
97 [PERF_COUNT_HW_CACHE_OP_MAX]
98 [PERF_COUNT_HW_CACHE_RESULT_MAX];
99 unsigned int num_counters;
102 static struct mips_pmu mipspmu;
104 #define M_CONFIG1_PC (1 << 4)
106 #define M_PERFCTL_EXL (1 << 0)
107 #define M_PERFCTL_KERNEL (1 << 1)
108 #define M_PERFCTL_SUPERVISOR (1 << 2)
109 #define M_PERFCTL_USER (1 << 3)
110 #define M_PERFCTL_INTERRUPT_ENABLE (1 << 4)
111 #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
112 #define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
114 #ifdef CONFIG_CPU_BMIPS5000
115 #define M_PERFCTL_MT_EN(filter) 0
116 #else /* !CONFIG_CPU_BMIPS5000 */
117 #define M_PERFCTL_MT_EN(filter) ((filter) << 20)
118 #endif /* CONFIG_CPU_BMIPS5000 */
120 #define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
121 #define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
122 #define M_TC_EN_TC M_PERFCTL_MT_EN(2)
123 #define M_PERFCTL_TCID(tcid) ((tcid) << 22)
124 #define M_PERFCTL_WIDE (1 << 30)
125 #define M_PERFCTL_MORE (1 << 31)
126 #define M_PERFCTL_TC (1 << 30)
128 #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \
131 M_PERFCTL_SUPERVISOR | \
132 M_PERFCTL_INTERRUPT_ENABLE)
134 #ifdef CONFIG_MIPS_MT_SMP
135 #define M_PERFCTL_CONFIG_MASK 0x3fff801f
137 #define M_PERFCTL_CONFIG_MASK 0x1f
139 #define M_PERFCTL_EVENT_MASK 0xfe0
142 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
143 static int cpu_has_mipsmt_pertccounters;
145 static DEFINE_RWLOCK(pmuint_rwlock);
147 #if defined(CONFIG_CPU_BMIPS5000)
148 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
149 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
152 * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
153 * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
155 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
156 0 : smp_processor_id())
159 /* Copied from op_model_mipsxx.c */
160 static unsigned int vpe_shift(void)
162 if (num_possible_cpus() > 1)
168 static unsigned int counters_total_to_per_cpu(unsigned int counters)
170 return counters >> vpe_shift();
173 #else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
176 #endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
178 static void resume_local_counters(void);
179 static void pause_local_counters(void);
180 static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
181 static int mipsxx_pmu_handle_shared_irq(void);
183 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
190 static u64 mipsxx_pmu_read_counter(unsigned int idx)
192 idx = mipsxx_pmu_swizzle_perf_idx(idx);
197 * The counters are unsigned, we must cast to truncate
200 return (u32)read_c0_perfcntr0();
202 return (u32)read_c0_perfcntr1();
204 return (u32)read_c0_perfcntr2();
206 return (u32)read_c0_perfcntr3();
208 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
213 static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
215 idx = mipsxx_pmu_swizzle_perf_idx(idx);
219 return read_c0_perfcntr0_64();
221 return read_c0_perfcntr1_64();
223 return read_c0_perfcntr2_64();
225 return read_c0_perfcntr3_64();
227 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
232 static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
234 idx = mipsxx_pmu_swizzle_perf_idx(idx);
238 write_c0_perfcntr0(val);
241 write_c0_perfcntr1(val);
244 write_c0_perfcntr2(val);
247 write_c0_perfcntr3(val);
252 static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
254 idx = mipsxx_pmu_swizzle_perf_idx(idx);
258 write_c0_perfcntr0_64(val);
261 write_c0_perfcntr1_64(val);
264 write_c0_perfcntr2_64(val);
267 write_c0_perfcntr3_64(val);
272 static unsigned int mipsxx_pmu_read_control(unsigned int idx)
274 idx = mipsxx_pmu_swizzle_perf_idx(idx);
278 return read_c0_perfctrl0();
280 return read_c0_perfctrl1();
282 return read_c0_perfctrl2();
284 return read_c0_perfctrl3();
286 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
291 static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
293 idx = mipsxx_pmu_swizzle_perf_idx(idx);
297 write_c0_perfctrl0(val);
300 write_c0_perfctrl1(val);
303 write_c0_perfctrl2(val);
306 write_c0_perfctrl3(val);
311 static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
312 struct hw_perf_event *hwc)
317 * We only need to care the counter mask. The range has been
318 * checked definitely.
320 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
322 for (i = mipspmu.num_counters - 1; i >= 0; i--) {
324 * Note that some MIPS perf events can be counted by both
325 * even and odd counters, wheresas many other are only by
326 * even _or_ odd counters. This introduces an issue that
327 * when the former kind of event takes the counter the
328 * latter kind of event wants to use, then the "counter
329 * allocation" for the latter event will fail. In fact if
330 * they can be dynamically swapped, they both feel happy.
331 * But here we leave this issue alone for now.
333 if (test_bit(i, &cntr_mask) &&
334 !test_and_set_bit(i, cpuc->used_mask))
341 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
343 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
345 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
347 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
348 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
349 /* Make sure interrupt enabled. */
350 M_PERFCTL_INTERRUPT_ENABLE;
351 if (IS_ENABLED(CONFIG_CPU_BMIPS5000))
352 /* enable the counter for the calling thread */
353 cpuc->saved_ctrl[idx] |=
354 (1 << (12 + vpe_id())) | M_PERFCTL_TC;
357 * We do not actually let the counter run. Leave it until start().
361 static void mipsxx_pmu_disable_event(int idx)
363 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
366 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
368 local_irq_save(flags);
369 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
370 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
371 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
372 local_irq_restore(flags);
375 static int mipspmu_event_set_period(struct perf_event *event,
376 struct hw_perf_event *hwc,
379 u64 left = local64_read(&hwc->period_left);
380 u64 period = hwc->sample_period;
383 if (unlikely((left + period) & (1ULL << 63))) {
384 /* left underflowed by more than period. */
386 local64_set(&hwc->period_left, left);
387 hwc->last_period = period;
389 } else if (unlikely((left + period) <= period)) {
390 /* left underflowed by less than period. */
392 local64_set(&hwc->period_left, left);
393 hwc->last_period = period;
397 if (left > mipspmu.max_period) {
398 left = mipspmu.max_period;
399 local64_set(&hwc->period_left, left);
402 local64_set(&hwc->prev_count, mipspmu.overflow - left);
404 mipspmu.write_counter(idx, mipspmu.overflow - left);
406 perf_event_update_userpage(event);
411 static void mipspmu_event_update(struct perf_event *event,
412 struct hw_perf_event *hwc,
415 u64 prev_raw_count, new_raw_count;
419 prev_raw_count = local64_read(&hwc->prev_count);
420 new_raw_count = mipspmu.read_counter(idx);
422 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
423 new_raw_count) != prev_raw_count)
426 delta = new_raw_count - prev_raw_count;
428 local64_add(delta, &event->count);
429 local64_sub(delta, &hwc->period_left);
432 static void mipspmu_start(struct perf_event *event, int flags)
434 struct hw_perf_event *hwc = &event->hw;
436 if (flags & PERF_EF_RELOAD)
437 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
441 /* Set the period for the event. */
442 mipspmu_event_set_period(event, hwc, hwc->idx);
444 /* Enable the event. */
445 mipsxx_pmu_enable_event(hwc, hwc->idx);
448 static void mipspmu_stop(struct perf_event *event, int flags)
450 struct hw_perf_event *hwc = &event->hw;
452 if (!(hwc->state & PERF_HES_STOPPED)) {
453 /* We are working on a local event. */
454 mipsxx_pmu_disable_event(hwc->idx);
456 mipspmu_event_update(event, hwc, hwc->idx);
457 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
461 static int mipspmu_add(struct perf_event *event, int flags)
463 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
464 struct hw_perf_event *hwc = &event->hw;
468 perf_pmu_disable(event->pmu);
470 /* To look for a free counter for this event. */
471 idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
478 * If there is an event in the counter we are going to use then
479 * make sure it is disabled.
482 mipsxx_pmu_disable_event(idx);
483 cpuc->events[idx] = event;
485 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
486 if (flags & PERF_EF_START)
487 mipspmu_start(event, PERF_EF_RELOAD);
489 /* Propagate our changes to the userspace mapping. */
490 perf_event_update_userpage(event);
493 perf_pmu_enable(event->pmu);
497 static void mipspmu_del(struct perf_event *event, int flags)
499 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
500 struct hw_perf_event *hwc = &event->hw;
503 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
505 mipspmu_stop(event, PERF_EF_UPDATE);
506 cpuc->events[idx] = NULL;
507 clear_bit(idx, cpuc->used_mask);
509 perf_event_update_userpage(event);
512 static void mipspmu_read(struct perf_event *event)
514 struct hw_perf_event *hwc = &event->hw;
516 /* Don't read disabled counters! */
520 mipspmu_event_update(event, hwc, hwc->idx);
523 static void mipspmu_enable(struct pmu *pmu)
525 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
526 write_unlock(&pmuint_rwlock);
528 resume_local_counters();
532 * MIPS performance counters can be per-TC. The control registers can
533 * not be directly accessed accross CPUs. Hence if we want to do global
534 * control, we need cross CPU calls. on_each_cpu() can help us, but we
535 * can not make sure this function is called with interrupts enabled. So
536 * here we pause local counters and then grab a rwlock and leave the
537 * counters on other CPUs alone. If any counter interrupt raises while
538 * we own the write lock, simply pause local counters on that CPU and
539 * spin in the handler. Also we know we won't be switched to another
540 * CPU after pausing local counters and before grabbing the lock.
542 static void mipspmu_disable(struct pmu *pmu)
544 pause_local_counters();
545 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
546 write_lock(&pmuint_rwlock);
550 static atomic_t active_events = ATOMIC_INIT(0);
551 static DEFINE_MUTEX(pmu_reserve_mutex);
552 static int (*save_perf_irq)(void);
554 static int mipspmu_get_irq(void)
558 if (mipspmu.irq >= 0) {
559 /* Request my own irq handler. */
560 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
561 IRQF_PERCPU | IRQF_NOBALANCING |
562 IRQF_NO_THREAD | IRQF_NO_SUSPEND |
564 "mips_perf_pmu", &mipspmu);
566 pr_warn("Unable to request IRQ%d for MIPS performance counters!\n",
569 } else if (cp0_perfcount_irq < 0) {
571 * We are sharing the irq number with the timer interrupt.
573 save_perf_irq = perf_irq;
574 perf_irq = mipsxx_pmu_handle_shared_irq;
577 pr_warn("The platform hasn't properly defined its interrupt controller\n");
584 static void mipspmu_free_irq(void)
586 if (mipspmu.irq >= 0)
587 free_irq(mipspmu.irq, &mipspmu);
588 else if (cp0_perfcount_irq < 0)
589 perf_irq = save_perf_irq;
593 * mipsxx/rm9000/loongson2 have different performance counters, they have
594 * specific low-level init routines.
596 static void reset_counters(void *arg);
597 static int __hw_perf_event_init(struct perf_event *event);
599 static void hw_perf_event_destroy(struct perf_event *event)
601 if (atomic_dec_and_mutex_lock(&active_events,
602 &pmu_reserve_mutex)) {
604 * We must not call the destroy function with interrupts
607 on_each_cpu(reset_counters,
608 (void *)(long)mipspmu.num_counters, 1);
610 mutex_unlock(&pmu_reserve_mutex);
614 static int mipspmu_event_init(struct perf_event *event)
618 /* does not support taken branch sampling */
619 if (has_branch_stack(event))
622 switch (event->attr.type) {
624 case PERF_TYPE_HARDWARE:
625 case PERF_TYPE_HW_CACHE:
632 if (event->cpu >= nr_cpumask_bits ||
633 (event->cpu >= 0 && !cpu_online(event->cpu)))
636 if (!atomic_inc_not_zero(&active_events)) {
637 mutex_lock(&pmu_reserve_mutex);
638 if (atomic_read(&active_events) == 0)
639 err = mipspmu_get_irq();
642 atomic_inc(&active_events);
643 mutex_unlock(&pmu_reserve_mutex);
649 return __hw_perf_event_init(event);
652 static struct pmu pmu = {
653 .pmu_enable = mipspmu_enable,
654 .pmu_disable = mipspmu_disable,
655 .event_init = mipspmu_event_init,
658 .start = mipspmu_start,
659 .stop = mipspmu_stop,
660 .read = mipspmu_read,
663 static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
666 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
669 #ifdef CONFIG_MIPS_MT_SMP
670 return ((unsigned int)pev->range << 24) |
671 (pev->cntr_mask & 0xffff00) |
672 (pev->event_id & 0xff);
674 return (pev->cntr_mask & 0xffff00) |
675 (pev->event_id & 0xff);
679 static const struct mips_perf_event *mipspmu_map_general_event(int idx)
682 if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
683 return ERR_PTR(-EOPNOTSUPP);
684 return &(*mipspmu.general_event_map)[idx];
687 static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
689 unsigned int cache_type, cache_op, cache_result;
690 const struct mips_perf_event *pev;
692 cache_type = (config >> 0) & 0xff;
693 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
694 return ERR_PTR(-EINVAL);
696 cache_op = (config >> 8) & 0xff;
697 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
698 return ERR_PTR(-EINVAL);
700 cache_result = (config >> 16) & 0xff;
701 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
702 return ERR_PTR(-EINVAL);
704 pev = &((*mipspmu.cache_event_map)
709 if (pev->cntr_mask == 0)
710 return ERR_PTR(-EOPNOTSUPP);
716 static int validate_group(struct perf_event *event)
718 struct perf_event *sibling, *leader = event->group_leader;
719 struct cpu_hw_events fake_cpuc;
721 memset(&fake_cpuc, 0, sizeof(fake_cpuc));
723 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
726 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
727 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
731 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
737 /* This is needed by specific irq handlers in perf_event_*.c */
738 static void handle_associated_event(struct cpu_hw_events *cpuc,
739 int idx, struct perf_sample_data *data,
740 struct pt_regs *regs)
742 struct perf_event *event = cpuc->events[idx];
743 struct hw_perf_event *hwc = &event->hw;
745 mipspmu_event_update(event, hwc, idx);
746 data->period = event->hw.last_period;
747 if (!mipspmu_event_set_period(event, hwc, idx))
750 if (perf_event_overflow(event, data, regs))
751 mipsxx_pmu_disable_event(idx);
755 static int __n_counters(void)
757 if (!(read_c0_config1() & M_CONFIG1_PC))
759 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
761 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
763 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
769 static int n_counters(void)
773 switch (current_cpu_type()) {
785 counters = __n_counters();
791 static void reset_counters(void *arg)
793 int counters = (int)(long)arg;
796 mipsxx_pmu_write_control(3, 0);
797 mipspmu.write_counter(3, 0);
799 mipsxx_pmu_write_control(2, 0);
800 mipspmu.write_counter(2, 0);
802 mipsxx_pmu_write_control(1, 0);
803 mipspmu.write_counter(1, 0);
805 mipsxx_pmu_write_control(0, 0);
806 mipspmu.write_counter(0, 0);
810 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
811 static const struct mips_perf_event mipsxxcore_event_map
812 [PERF_COUNT_HW_MAX] = {
813 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
814 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
815 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
816 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
819 /* 74K/proAptiv core has different branch event code. */
820 static const struct mips_perf_event mipsxxcore_event_map2
821 [PERF_COUNT_HW_MAX] = {
822 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
823 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
824 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
825 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
828 static const struct mips_perf_event loongson3_event_map[PERF_COUNT_HW_MAX] = {
829 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
830 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
831 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
832 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
835 static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
836 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
837 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
838 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
839 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL },
840 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
841 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
842 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
845 static const struct mips_perf_event bmips5000_event_map
846 [PERF_COUNT_HW_MAX] = {
847 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
848 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
849 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
852 static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
853 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
854 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
855 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
856 [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
857 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
858 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
861 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
862 static const struct mips_perf_event mipsxxcore_cache_map
863 [PERF_COUNT_HW_CACHE_MAX]
864 [PERF_COUNT_HW_CACHE_OP_MAX]
865 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
868 * Like some other architectures (e.g. ARM), the performance
869 * counters don't differentiate between read and write
870 * accesses/misses, so this isn't strictly correct, but it's the
871 * best we can do. Writes and reads get combined.
874 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
875 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
878 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
879 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
884 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
885 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
888 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
889 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
892 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
894 * Note that MIPS has only "hit" events countable for
895 * the prefetch operation.
901 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
902 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
905 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
906 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
911 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
912 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
915 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
916 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
921 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
922 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
925 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
926 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
930 /* Using the same code for *HW_BRANCH* */
932 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
933 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
936 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
937 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
942 /* 74K/proAptiv core has completely different cache event map. */
943 static const struct mips_perf_event mipsxxcore_cache_map2
944 [PERF_COUNT_HW_CACHE_MAX]
945 [PERF_COUNT_HW_CACHE_OP_MAX]
946 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
949 * Like some other architectures (e.g. ARM), the performance
950 * counters don't differentiate between read and write
951 * accesses/misses, so this isn't strictly correct, but it's the
952 * best we can do. Writes and reads get combined.
955 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
956 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
959 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
960 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
965 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
966 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
969 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
970 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
973 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
975 * Note that MIPS has only "hit" events countable for
976 * the prefetch operation.
982 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
983 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
986 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
987 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
991 * 74K core does not have specific DTLB events. proAptiv core has
992 * "speculative" DTLB events which are numbered 0x63 (even/odd) and
993 * not included here. One can use raw events if really needed.
997 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
998 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1001 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1002 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1006 /* Using the same code for *HW_BRANCH* */
1008 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1009 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1012 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1013 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1018 static const struct mips_perf_event loongson3_cache_map
1019 [PERF_COUNT_HW_CACHE_MAX]
1020 [PERF_COUNT_HW_CACHE_OP_MAX]
1021 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1024 * Like some other architectures (e.g. ARM), the performance
1025 * counters don't differentiate between read and write
1026 * accesses/misses, so this isn't strictly correct, but it's the
1027 * best we can do. Writes and reads get combined.
1030 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1033 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1038 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1041 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1046 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1049 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1054 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1057 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1061 /* Using the same code for *HW_BRANCH* */
1063 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1064 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1067 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1068 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1074 static const struct mips_perf_event bmips5000_cache_map
1075 [PERF_COUNT_HW_CACHE_MAX]
1076 [PERF_COUNT_HW_CACHE_OP_MAX]
1077 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1080 * Like some other architectures (e.g. ARM), the performance
1081 * counters don't differentiate between read and write
1082 * accesses/misses, so this isn't strictly correct, but it's the
1083 * best we can do. Writes and reads get combined.
1086 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1087 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1090 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1091 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1096 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1097 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1100 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1101 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1103 [C(OP_PREFETCH)] = {
1104 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1106 * Note that MIPS has only "hit" events countable for
1107 * the prefetch operation.
1113 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1114 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1117 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1118 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1122 /* Using the same code for *HW_BRANCH* */
1124 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1127 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1133 static const struct mips_perf_event octeon_cache_map
1134 [PERF_COUNT_HW_CACHE_MAX]
1135 [PERF_COUNT_HW_CACHE_OP_MAX]
1136 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1139 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1140 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1143 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1148 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1150 [C(OP_PREFETCH)] = {
1151 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1156 * Only general DTLB misses are counted use the same event for
1160 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1163 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1168 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1173 static const struct mips_perf_event xlp_cache_map
1174 [PERF_COUNT_HW_CACHE_MAX]
1175 [PERF_COUNT_HW_CACHE_OP_MAX]
1176 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1179 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1180 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1183 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1184 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1189 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1190 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1195 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1196 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1199 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1200 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1205 * Only general DTLB misses are counted use the same event for
1209 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1212 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1217 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1220 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1225 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },
1230 #ifdef CONFIG_MIPS_MT_SMP
1231 static void check_and_calc_range(struct perf_event *event,
1232 const struct mips_perf_event *pev)
1234 struct hw_perf_event *hwc = &event->hw;
1236 if (event->cpu >= 0) {
1237 if (pev->range > V) {
1239 * The user selected an event that is processor
1240 * wide, while expecting it to be VPE wide.
1242 hwc->config_base |= M_TC_EN_ALL;
1245 * FIXME: cpu_data[event->cpu].vpe_id reports 0
1248 hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
1249 hwc->config_base |= M_TC_EN_VPE;
1252 hwc->config_base |= M_TC_EN_ALL;
1255 static void check_and_calc_range(struct perf_event *event,
1256 const struct mips_perf_event *pev)
1261 static int __hw_perf_event_init(struct perf_event *event)
1263 struct perf_event_attr *attr = &event->attr;
1264 struct hw_perf_event *hwc = &event->hw;
1265 const struct mips_perf_event *pev;
1268 /* Returning MIPS event descriptor for generic perf event. */
1269 if (PERF_TYPE_HARDWARE == event->attr.type) {
1270 if (event->attr.config >= PERF_COUNT_HW_MAX)
1272 pev = mipspmu_map_general_event(event->attr.config);
1273 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1274 pev = mipspmu_map_cache_event(event->attr.config);
1275 } else if (PERF_TYPE_RAW == event->attr.type) {
1276 /* We are working on the global raw event. */
1277 mutex_lock(&raw_event_mutex);
1278 pev = mipspmu.map_raw_event(event->attr.config);
1280 /* The event type is not (yet) supported. */
1285 if (PERF_TYPE_RAW == event->attr.type)
1286 mutex_unlock(&raw_event_mutex);
1287 return PTR_ERR(pev);
1291 * We allow max flexibility on how each individual counter shared
1292 * by the single CPU operates (the mode exclusion and the range).
1294 hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
1296 /* Calculate range bits and validate it. */
1297 if (num_possible_cpus() > 1)
1298 check_and_calc_range(event, pev);
1300 hwc->event_base = mipspmu_perf_event_encode(pev);
1301 if (PERF_TYPE_RAW == event->attr.type)
1302 mutex_unlock(&raw_event_mutex);
1304 if (!attr->exclude_user)
1305 hwc->config_base |= M_PERFCTL_USER;
1306 if (!attr->exclude_kernel) {
1307 hwc->config_base |= M_PERFCTL_KERNEL;
1308 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1309 hwc->config_base |= M_PERFCTL_EXL;
1311 if (!attr->exclude_hv)
1312 hwc->config_base |= M_PERFCTL_SUPERVISOR;
1314 hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1316 * The event can belong to another cpu. We do not assign a local
1317 * counter for it for now.
1322 if (!hwc->sample_period) {
1323 hwc->sample_period = mipspmu.max_period;
1324 hwc->last_period = hwc->sample_period;
1325 local64_set(&hwc->period_left, hwc->sample_period);
1329 if (event->group_leader != event)
1330 err = validate_group(event);
1332 event->destroy = hw_perf_event_destroy;
1335 event->destroy(event);
1340 static void pause_local_counters(void)
1342 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1343 int ctr = mipspmu.num_counters;
1344 unsigned long flags;
1346 local_irq_save(flags);
1349 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1350 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1351 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1353 local_irq_restore(flags);
1356 static void resume_local_counters(void)
1358 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1359 int ctr = mipspmu.num_counters;
1363 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1367 static int mipsxx_pmu_handle_shared_irq(void)
1369 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1370 struct perf_sample_data data;
1371 unsigned int counters = mipspmu.num_counters;
1373 int handled = IRQ_NONE;
1374 struct pt_regs *regs;
1376 if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
1379 * First we pause the local counters, so that when we are locked
1380 * here, the counters are all paused. When it gets locked due to
1381 * perf_disable(), the timer interrupt handler will be delayed.
1383 * See also mipsxx_pmu_start().
1385 pause_local_counters();
1386 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1387 read_lock(&pmuint_rwlock);
1390 regs = get_irq_regs();
1392 perf_sample_data_init(&data, 0, 0);
1395 #define HANDLE_COUNTER(n) \
1397 if (test_bit(n, cpuc->used_mask)) { \
1398 counter = mipspmu.read_counter(n); \
1399 if (counter & mipspmu.overflow) { \
1400 handle_associated_event(cpuc, n, &data, regs); \
1401 handled = IRQ_HANDLED; \
1411 * Do all the work for the pending perf events. We can do this
1412 * in here because the performance counter interrupt is a regular
1413 * interrupt, not NMI.
1415 if (handled == IRQ_HANDLED)
1418 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1419 read_unlock(&pmuint_rwlock);
1421 resume_local_counters();
1425 static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1427 return mipsxx_pmu_handle_shared_irq();
1431 #define IS_BOTH_COUNTERS_24K_EVENT(b) \
1432 ((b) == 0 || (b) == 1 || (b) == 11)
1435 #define IS_BOTH_COUNTERS_34K_EVENT(b) \
1436 ((b) == 0 || (b) == 1 || (b) == 11)
1437 #ifdef CONFIG_MIPS_MT_SMP
1438 #define IS_RANGE_P_34K_EVENT(r, b) \
1439 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1440 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
1441 (r) == 176 || ((b) >= 50 && (b) <= 55) || \
1442 ((b) >= 64 && (b) <= 67))
1443 #define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1447 #define IS_BOTH_COUNTERS_74K_EVENT(b) \
1448 ((b) == 0 || (b) == 1)
1451 #define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b) \
1452 ((b) == 0 || (b) == 1)
1454 #define IS_BOTH_COUNTERS_P5600_EVENT(b) \
1455 ((b) == 0 || (b) == 1)
1458 #define IS_BOTH_COUNTERS_1004K_EVENT(b) \
1459 ((b) == 0 || (b) == 1 || (b) == 11)
1460 #ifdef CONFIG_MIPS_MT_SMP
1461 #define IS_RANGE_P_1004K_EVENT(r, b) \
1462 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1463 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \
1464 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \
1465 (r) == 188 || (b) == 61 || (b) == 62 || \
1466 ((b) >= 64 && (b) <= 67))
1467 #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
1471 #define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b) \
1472 ((b) == 0 || (b) == 1 || (b) == 11)
1473 #ifdef CONFIG_MIPS_MT_SMP
1474 /* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
1475 #define IS_RANGE_P_INTERAPTIV_EVENT(r, b) \
1476 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1477 (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 || \
1478 (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 && \
1479 (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 || \
1480 ((b) >= 64 && (b) <= 67))
1481 #define IS_RANGE_V_INTERAPTIV_EVENT(r) ((r) == 47 || (r) == 175)
1485 #define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \
1486 ((b) == 0 || (b) == 1)
1490 * For most cores the user can use 0-255 raw events, where 0-127 for the events
1491 * of even counters, and 128-255 for odd counters. Note that bit 7 is used to
1492 * indicate the even/odd bank selector. So, for example, when user wants to take
1493 * the Event Num of 15 for odd counters (by referring to the user manual), then
1494 * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F)
1497 * Some newer cores have even more events, in which case the user can use raw
1498 * events 0-511, where 0-255 are for the events of even counters, and 256-511
1499 * are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
1501 static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1503 /* currently most cores have 7-bit event numbers */
1504 unsigned int raw_id = config & 0xff;
1505 unsigned int base_id = raw_id & 0x7f;
1507 switch (current_cpu_type()) {
1509 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1510 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1512 raw_event.cntr_mask =
1513 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1514 #ifdef CONFIG_MIPS_MT_SMP
1516 * This is actually doing nothing. Non-multithreading
1517 * CPUs will not check and calculate the range.
1519 raw_event.range = P;
1523 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1524 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1526 raw_event.cntr_mask =
1527 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1528 #ifdef CONFIG_MIPS_MT_SMP
1529 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1530 raw_event.range = P;
1531 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1532 raw_event.range = V;
1534 raw_event.range = T;
1539 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1540 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1542 raw_event.cntr_mask =
1543 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1544 #ifdef CONFIG_MIPS_MT_SMP
1545 raw_event.range = P;
1549 if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id))
1550 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1552 raw_event.cntr_mask =
1553 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1554 #ifdef CONFIG_MIPS_MT_SMP
1555 raw_event.range = P;
1559 /* 8-bit event numbers */
1560 raw_id = config & 0x1ff;
1561 base_id = raw_id & 0xff;
1562 if (IS_BOTH_COUNTERS_P5600_EVENT(base_id))
1563 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1565 raw_event.cntr_mask =
1566 raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
1567 #ifdef CONFIG_MIPS_MT_SMP
1568 raw_event.range = P;
1572 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1573 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1575 raw_event.cntr_mask =
1576 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1577 #ifdef CONFIG_MIPS_MT_SMP
1578 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1579 raw_event.range = P;
1580 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1581 raw_event.range = V;
1583 raw_event.range = T;
1586 case CPU_INTERAPTIV:
1587 if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
1588 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1590 raw_event.cntr_mask =
1591 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1592 #ifdef CONFIG_MIPS_MT_SMP
1593 if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
1594 raw_event.range = P;
1595 else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
1596 raw_event.range = V;
1598 raw_event.range = T;
1602 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
1603 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1605 raw_event.cntr_mask =
1606 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1609 raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1613 raw_event.event_id = base_id;
1618 static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1620 unsigned int raw_id = config & 0xff;
1621 unsigned int base_id = raw_id & 0x7f;
1624 raw_event.cntr_mask = CNTR_ALL;
1625 raw_event.event_id = base_id;
1627 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
1629 return ERR_PTR(-EOPNOTSUPP);
1632 return ERR_PTR(-EOPNOTSUPP);
1643 return ERR_PTR(-EOPNOTSUPP);
1651 static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
1653 unsigned int raw_id = config & 0xff;
1655 /* Only 1-63 are defined */
1656 if ((raw_id < 0x01) || (raw_id > 0x3f))
1657 return ERR_PTR(-EOPNOTSUPP);
1659 raw_event.cntr_mask = CNTR_ALL;
1660 raw_event.event_id = raw_id;
1666 init_hw_perf_events(void)
1671 pr_info("Performance counters: ");
1673 counters = n_counters();
1674 if (counters == 0) {
1675 pr_cont("No available PMU.\n");
1679 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1680 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
1681 if (!cpu_has_mipsmt_pertccounters)
1682 counters = counters_total_to_per_cpu(counters);
1685 if (get_c0_perfcount_int)
1686 irq = get_c0_perfcount_int();
1687 else if (cp0_perfcount_irq >= 0)
1688 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1692 mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1694 switch (current_cpu_type()) {
1696 mipspmu.name = "mips/24K";
1697 mipspmu.general_event_map = &mipsxxcore_event_map;
1698 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1701 mipspmu.name = "mips/34K";
1702 mipspmu.general_event_map = &mipsxxcore_event_map;
1703 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1706 mipspmu.name = "mips/74K";
1707 mipspmu.general_event_map = &mipsxxcore_event_map2;
1708 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1711 mipspmu.name = "mips/proAptiv";
1712 mipspmu.general_event_map = &mipsxxcore_event_map2;
1713 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1716 mipspmu.name = "mips/P5600";
1717 mipspmu.general_event_map = &mipsxxcore_event_map2;
1718 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1721 mipspmu.name = "mips/1004K";
1722 mipspmu.general_event_map = &mipsxxcore_event_map;
1723 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1726 mipspmu.name = "mips/1074K";
1727 mipspmu.general_event_map = &mipsxxcore_event_map;
1728 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1730 case CPU_INTERAPTIV:
1731 mipspmu.name = "mips/interAptiv";
1732 mipspmu.general_event_map = &mipsxxcore_event_map;
1733 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1736 mipspmu.name = "mips/loongson1";
1737 mipspmu.general_event_map = &mipsxxcore_event_map;
1738 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1741 mipspmu.name = "mips/loongson3";
1742 mipspmu.general_event_map = &loongson3_event_map;
1743 mipspmu.cache_event_map = &loongson3_cache_map;
1745 case CPU_CAVIUM_OCTEON:
1746 case CPU_CAVIUM_OCTEON_PLUS:
1747 case CPU_CAVIUM_OCTEON2:
1748 mipspmu.name = "octeon";
1749 mipspmu.general_event_map = &octeon_event_map;
1750 mipspmu.cache_event_map = &octeon_cache_map;
1751 mipspmu.map_raw_event = octeon_pmu_map_raw_event;
1754 mipspmu.name = "BMIPS5000";
1755 mipspmu.general_event_map = &bmips5000_event_map;
1756 mipspmu.cache_event_map = &bmips5000_cache_map;
1759 mipspmu.name = "xlp";
1760 mipspmu.general_event_map = &xlp_event_map;
1761 mipspmu.cache_event_map = &xlp_cache_map;
1762 mipspmu.map_raw_event = xlp_pmu_map_raw_event;
1765 pr_cont("Either hardware does not support performance "
1766 "counters, or not yet implemented.\n");
1770 mipspmu.num_counters = counters;
1773 if (read_c0_perfctrl0() & M_PERFCTL_WIDE) {
1774 mipspmu.max_period = (1ULL << 63) - 1;
1775 mipspmu.valid_count = (1ULL << 63) - 1;
1776 mipspmu.overflow = 1ULL << 63;
1777 mipspmu.read_counter = mipsxx_pmu_read_counter_64;
1778 mipspmu.write_counter = mipsxx_pmu_write_counter_64;
1781 mipspmu.max_period = (1ULL << 31) - 1;
1782 mipspmu.valid_count = (1ULL << 31) - 1;
1783 mipspmu.overflow = 1ULL << 31;
1784 mipspmu.read_counter = mipsxx_pmu_read_counter;
1785 mipspmu.write_counter = mipsxx_pmu_write_counter;
1789 on_each_cpu(reset_counters, (void *)(long)counters, 1);
1791 pr_cont("%s PMU enabled, %d %d-bit counters available to each "
1792 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
1793 irq < 0 ? " (share with timer interrupt)" : "");
1795 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1799 early_initcall(init_hw_perf_events);