arch/mips/kernel/r4k_fpu.S

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
   7  *
   8  * Multi-arch abstraction and asm macros for easier reading:
   9  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  10  *
  11  * Carsten Langgaard, carstenl@mips.com
  12  * Copyright (C) 2000 MIPS Technologies, Inc.
  13  * Copyright (C) 1999, 2001 Silicon Graphics, Inc.
  14  */
  15 #include <asm/asm.h>
  16 #include <asm/asmmacro.h>
  17 #include <asm/errno.h>
  18 #include <asm/fpregdef.h>
  19 #include <asm/mipsregs.h>
  20 #include <asm/asm-offsets.h>
  21 #include <asm/regdef.h>
  22
  23 /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
  24 #undef fp
  25
  26         .macro  EX insn, reg, src
  27         .set    push
  28         SET_HARDFLOAT
  29         .set    nomacro
  30 .ex\@:  \insn   \reg, \src
  31         .set    pop
  32         .section __ex_table,"a"
  33         PTR     .ex\@, fault
  34         .previous
  35         .endm
  36
  37         .set    noreorder
  38
  39 LEAF(_save_fp_context)
  40         .set    push
  41         SET_HARDFLOAT
  42         cfc1    t1, fcr31
  43         .set    pop
  44
  45 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
  46                 defined(CONFIG_CPU_MIPS32_R6)
  47         .set    push
  48         SET_HARDFLOAT
  49 #ifdef CONFIG_CPU_MIPS32_R2
  50         .set    mips32r2
  51         .set    fp=64
  52         mfc0    t0, CP0_STATUS
  53         sll     t0, t0, 5
  54         bgez    t0, 1f                  # skip storing odd if FR=0
  55          nop
  56 #endif
  57         /* Store the 16 odd double precision registers */
  58         EX      sdc1 $f1, SC_FPREGS+8(a0)
  59         EX      sdc1 $f3, SC_FPREGS+24(a0)
  60         EX      sdc1 $f5, SC_FPREGS+40(a0)
  61         EX      sdc1 $f7, SC_FPREGS+56(a0)
  62         EX      sdc1 $f9, SC_FPREGS+72(a0)
  63         EX      sdc1 $f11, SC_FPREGS+88(a0)
  64         EX      sdc1 $f13, SC_FPREGS+104(a0)
  65         EX      sdc1 $f15, SC_FPREGS+120(a0)
  66         EX      sdc1 $f17, SC_FPREGS+136(a0)
  67         EX      sdc1 $f19, SC_FPREGS+152(a0)
  68         EX      sdc1 $f21, SC_FPREGS+168(a0)
  69         EX      sdc1 $f23, SC_FPREGS+184(a0)
  70         EX      sdc1 $f25, SC_FPREGS+200(a0)
  71         EX      sdc1 $f27, SC_FPREGS+216(a0)
  72         EX      sdc1 $f29, SC_FPREGS+232(a0)
  73         EX      sdc1 $f31, SC_FPREGS+248(a0)
  74 1:      .set    pop
  75 #endif
  76
  77         .set push
  78         SET_HARDFLOAT
  79         /* Store the 16 even double precision registers */
  80         EX      sdc1 $f0, SC_FPREGS+0(a0)
  81         EX      sdc1 $f2, SC_FPREGS+16(a0)
  82         EX      sdc1 $f4, SC_FPREGS+32(a0)
  83         EX      sdc1 $f6, SC_FPREGS+48(a0)
  84         EX      sdc1 $f8, SC_FPREGS+64(a0)
  85         EX      sdc1 $f10, SC_FPREGS+80(a0)
  86         EX      sdc1 $f12, SC_FPREGS+96(a0)
  87         EX      sdc1 $f14, SC_FPREGS+112(a0)
  88         EX      sdc1 $f16, SC_FPREGS+128(a0)
  89         EX      sdc1 $f18, SC_FPREGS+144(a0)
  90         EX      sdc1 $f20, SC_FPREGS+160(a0)
  91         EX      sdc1 $f22, SC_FPREGS+176(a0)
  92         EX      sdc1 $f24, SC_FPREGS+192(a0)
  93         EX      sdc1 $f26, SC_FPREGS+208(a0)
  94         EX      sdc1 $f28, SC_FPREGS+224(a0)
  95         EX      sdc1 $f30, SC_FPREGS+240(a0)
  96         EX      sw t1, SC_FPC_CSR(a0)
  97         jr      ra
  98          li     v0, 0                                   # success
  99         .set pop
 100         END(_save_fp_context)
 101
 102 #ifdef CONFIG_MIPS32_COMPAT
 103         /* Save 32-bit process floating point context */
 104 LEAF(_save_fp_context32)
 105         .set push
 106         .set MIPS_ISA_ARCH_LEVEL_RAW
 107         SET_HARDFLOAT
 108         cfc1    t1, fcr31
 109
 110 #ifndef CONFIG_CPU_MIPS64_R6
 111         mfc0    t0, CP0_STATUS
 112         sll     t0, t0, 5
 113         bgez    t0, 1f                  # skip storing odd if FR=0
 114          nop
 115 #endif
 116
 117         /* Store the 16 odd double precision registers */
 118         EX      sdc1 $f1, SC32_FPREGS+8(a0)
 119         EX      sdc1 $f3, SC32_FPREGS+24(a0)
 120         EX      sdc1 $f5, SC32_FPREGS+40(a0)
 121         EX      sdc1 $f7, SC32_FPREGS+56(a0)
 122         EX      sdc1 $f9, SC32_FPREGS+72(a0)
 123         EX      sdc1 $f11, SC32_FPREGS+88(a0)
 124         EX      sdc1 $f13, SC32_FPREGS+104(a0)
 125         EX      sdc1 $f15, SC32_FPREGS+120(a0)
 126         EX      sdc1 $f17, SC32_FPREGS+136(a0)
 127         EX      sdc1 $f19, SC32_FPREGS+152(a0)
 128         EX      sdc1 $f21, SC32_FPREGS+168(a0)
 129         EX      sdc1 $f23, SC32_FPREGS+184(a0)
 130         EX      sdc1 $f25, SC32_FPREGS+200(a0)
 131         EX      sdc1 $f27, SC32_FPREGS+216(a0)
 132         EX      sdc1 $f29, SC32_FPREGS+232(a0)
 133         EX      sdc1 $f31, SC32_FPREGS+248(a0)
 134
 135         /* Store the 16 even double precision registers */
 136 1:      EX      sdc1 $f0, SC32_FPREGS+0(a0)
 137         EX      sdc1 $f2, SC32_FPREGS+16(a0)
 138         EX      sdc1 $f4, SC32_FPREGS+32(a0)
 139         EX      sdc1 $f6, SC32_FPREGS+48(a0)
 140         EX      sdc1 $f8, SC32_FPREGS+64(a0)
 141         EX      sdc1 $f10, SC32_FPREGS+80(a0)
 142         EX      sdc1 $f12, SC32_FPREGS+96(a0)
 143         EX      sdc1 $f14, SC32_FPREGS+112(a0)
 144         EX      sdc1 $f16, SC32_FPREGS+128(a0)
 145         EX      sdc1 $f18, SC32_FPREGS+144(a0)
 146         EX      sdc1 $f20, SC32_FPREGS+160(a0)
 147         EX      sdc1 $f22, SC32_FPREGS+176(a0)
 148         EX      sdc1 $f24, SC32_FPREGS+192(a0)
 149         EX      sdc1 $f26, SC32_FPREGS+208(a0)
 150         EX      sdc1 $f28, SC32_FPREGS+224(a0)
 151         EX      sdc1 $f30, SC32_FPREGS+240(a0)
 152         EX      sw t1, SC32_FPC_CSR(a0)
 153         cfc1    t0, $0                          # implementation/version
 154         EX      sw t0, SC32_FPC_EIR(a0)
 155         .set pop
 156
 157         jr      ra
 158          li     v0, 0                                   # success
 159         END(_save_fp_context32)
 160 #endif
 161
 162 /*
 163  * Restore FPU state:
 164  *  - fp gp registers
 165  *  - cp1 status/control register
 166  */
 167 LEAF(_restore_fp_context)
 168         EX      lw t1, SC_FPC_CSR(a0)
 169
 170 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)  || \
 171                 defined(CONFIG_CPU_MIPS32_R6)
 172         .set    push
 173         SET_HARDFLOAT
 174 #ifdef CONFIG_CPU_MIPS32_R2
 175         .set    mips32r2
 176         .set    fp=64
 177         mfc0    t0, CP0_STATUS
 178         sll     t0, t0, 5
 179         bgez    t0, 1f                  # skip loading odd if FR=0
 180          nop
 181 #endif
 182         EX      ldc1 $f1, SC_FPREGS+8(a0)
 183         EX      ldc1 $f3, SC_FPREGS+24(a0)
 184         EX      ldc1 $f5, SC_FPREGS+40(a0)
 185         EX      ldc1 $f7, SC_FPREGS+56(a0)
 186         EX      ldc1 $f9, SC_FPREGS+72(a0)
 187         EX      ldc1 $f11, SC_FPREGS+88(a0)
 188         EX      ldc1 $f13, SC_FPREGS+104(a0)
 189         EX      ldc1 $f15, SC_FPREGS+120(a0)
 190         EX      ldc1 $f17, SC_FPREGS+136(a0)
 191         EX      ldc1 $f19, SC_FPREGS+152(a0)
 192         EX      ldc1 $f21, SC_FPREGS+168(a0)
 193         EX      ldc1 $f23, SC_FPREGS+184(a0)
 194         EX      ldc1 $f25, SC_FPREGS+200(a0)
 195         EX      ldc1 $f27, SC_FPREGS+216(a0)
 196         EX      ldc1 $f29, SC_FPREGS+232(a0)
 197         EX      ldc1 $f31, SC_FPREGS+248(a0)
 198 1:      .set pop
 199 #endif
 200         .set push
 201         SET_HARDFLOAT
 202         EX      ldc1 $f0, SC_FPREGS+0(a0)
 203         EX      ldc1 $f2, SC_FPREGS+16(a0)
 204         EX      ldc1 $f4, SC_FPREGS+32(a0)
 205         EX      ldc1 $f6, SC_FPREGS+48(a0)
 206         EX      ldc1 $f8, SC_FPREGS+64(a0)
 207         EX      ldc1 $f10, SC_FPREGS+80(a0)
 208         EX      ldc1 $f12, SC_FPREGS+96(a0)
 209         EX      ldc1 $f14, SC_FPREGS+112(a0)
 210         EX      ldc1 $f16, SC_FPREGS+128(a0)
 211         EX      ldc1 $f18, SC_FPREGS+144(a0)
 212         EX      ldc1 $f20, SC_FPREGS+160(a0)
 213         EX      ldc1 $f22, SC_FPREGS+176(a0)
 214         EX      ldc1 $f24, SC_FPREGS+192(a0)
 215         EX      ldc1 $f26, SC_FPREGS+208(a0)
 216         EX      ldc1 $f28, SC_FPREGS+224(a0)
 217         EX      ldc1 $f30, SC_FPREGS+240(a0)
 218         ctc1    t1, fcr31
 219         .set pop
 220         jr      ra
 221          li     v0, 0                                   # success
 222         END(_restore_fp_context)
 223
 224 #ifdef CONFIG_MIPS32_COMPAT
 225 LEAF(_restore_fp_context32)
 226         /* Restore an o32 sigcontext.  */
 227         .set push
 228         SET_HARDFLOAT
 229         EX      lw t1, SC32_FPC_CSR(a0)
 230
 231 #ifndef CONFIG_CPU_MIPS64_R6
 232         mfc0    t0, CP0_STATUS
 233         sll     t0, t0, 5
 234         bgez    t0, 1f                  # skip loading odd if FR=0
 235          nop
 236 #endif
 237
 238         EX      ldc1 $f1, SC32_FPREGS+8(a0)
 239         EX      ldc1 $f3, SC32_FPREGS+24(a0)
 240         EX      ldc1 $f5, SC32_FPREGS+40(a0)
 241         EX      ldc1 $f7, SC32_FPREGS+56(a0)
 242         EX      ldc1 $f9, SC32_FPREGS+72(a0)
 243         EX      ldc1 $f11, SC32_FPREGS+88(a0)
 244         EX      ldc1 $f13, SC32_FPREGS+104(a0)
 245         EX      ldc1 $f15, SC32_FPREGS+120(a0)
 246         EX      ldc1 $f17, SC32_FPREGS+136(a0)
 247         EX      ldc1 $f19, SC32_FPREGS+152(a0)
 248         EX      ldc1 $f21, SC32_FPREGS+168(a0)
 249         EX      ldc1 $f23, SC32_FPREGS+184(a0)
 250         EX      ldc1 $f25, SC32_FPREGS+200(a0)
 251         EX      ldc1 $f27, SC32_FPREGS+216(a0)
 252         EX      ldc1 $f29, SC32_FPREGS+232(a0)
 253         EX      ldc1 $f31, SC32_FPREGS+248(a0)
 254
 255 1:      EX      ldc1 $f0, SC32_FPREGS+0(a0)
 256         EX      ldc1 $f2, SC32_FPREGS+16(a0)
 257         EX      ldc1 $f4, SC32_FPREGS+32(a0)
 258         EX      ldc1 $f6, SC32_FPREGS+48(a0)
 259         EX      ldc1 $f8, SC32_FPREGS+64(a0)
 260         EX      ldc1 $f10, SC32_FPREGS+80(a0)
 261         EX      ldc1 $f12, SC32_FPREGS+96(a0)
 262         EX      ldc1 $f14, SC32_FPREGS+112(a0)
 263         EX      ldc1 $f16, SC32_FPREGS+128(a0)
 264         EX      ldc1 $f18, SC32_FPREGS+144(a0)
 265         EX      ldc1 $f20, SC32_FPREGS+160(a0)
 266         EX      ldc1 $f22, SC32_FPREGS+176(a0)
 267         EX      ldc1 $f24, SC32_FPREGS+192(a0)
 268         EX      ldc1 $f26, SC32_FPREGS+208(a0)
 269         EX      ldc1 $f28, SC32_FPREGS+224(a0)
 270         EX      ldc1 $f30, SC32_FPREGS+240(a0)
 271         ctc1    t1, fcr31
 272         jr      ra
 273          li     v0, 0                                   # success
 274         .set pop
 275         END(_restore_fp_context32)
 276 #endif
 277
 278 #ifdef CONFIG_CPU_HAS_MSA
 279
 280         .macro  op_one_wr       op, idx, base
 281         .align  4
 282 \idx:   \op     \idx, 0, \base
 283         jr      ra
 284          nop
 285         .endm
 286
 287         .macro  op_msa_wr       name, op
 288 LEAF(\name)
 289         .set            push
 290         .set            noreorder
 291         sll             t0, a0, 4
 292         PTR_LA          t1, 0f
 293         PTR_ADDU        t0, t0, t1
 294         jr              t0
 295           nop
 296         op_one_wr       \op, 0, a1
 297         op_one_wr       \op, 1, a1
 298         op_one_wr       \op, 2, a1
 299         op_one_wr       \op, 3, a1
 300         op_one_wr       \op, 4, a1
 301         op_one_wr       \op, 5, a1
 302         op_one_wr       \op, 6, a1
 303         op_one_wr       \op, 7, a1
 304         op_one_wr       \op, 8, a1
 305         op_one_wr       \op, 9, a1
 306         op_one_wr       \op, 10, a1
 307         op_one_wr       \op, 11, a1
 308         op_one_wr       \op, 12, a1
 309         op_one_wr       \op, 13, a1
 310         op_one_wr       \op, 14, a1
 311         op_one_wr       \op, 15, a1
 312         op_one_wr       \op, 16, a1
 313         op_one_wr       \op, 17, a1
 314         op_one_wr       \op, 18, a1
 315         op_one_wr       \op, 19, a1
 316         op_one_wr       \op, 20, a1
 317         op_one_wr       \op, 21, a1
 318         op_one_wr       \op, 22, a1
 319         op_one_wr       \op, 23, a1
 320         op_one_wr       \op, 24, a1
 321         op_one_wr       \op, 25, a1
 322         op_one_wr       \op, 26, a1
 323         op_one_wr       \op, 27, a1
 324         op_one_wr       \op, 28, a1
 325         op_one_wr       \op, 29, a1
 326         op_one_wr       \op, 30, a1
 327         op_one_wr       \op, 31, a1
 328         .set            pop
 329         END(\name)
 330         .endm
 331
 332         op_msa_wr       read_msa_wr_b, st_b
 333         op_msa_wr       read_msa_wr_h, st_h
 334         op_msa_wr       read_msa_wr_w, st_w
 335         op_msa_wr       read_msa_wr_d, st_d
 336
 337         op_msa_wr       write_msa_wr_b, ld_b
 338         op_msa_wr       write_msa_wr_h, ld_h
 339         op_msa_wr       write_msa_wr_w, ld_w
 340         op_msa_wr       write_msa_wr_d, ld_d
 341
 342 #endif /* CONFIG_CPU_HAS_MSA */
 343
 344         .set    reorder
 345
 346         .type   fault@function
 347         .ent    fault
 348 fault:  li      v0, -EFAULT                             # failure
 349         jr      ra
 350         .end    fault