arch/mips/kernel/smp-cps.c

   1 /*
   2  * Copyright (C) 2013 Imagination Technologies
   3  * Author: Paul Burton <paul.burton@imgtec.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/irqchip/mips-gic.h>
  14 #include <linux/sched.h>
  15 #include <linux/slab.h>
  16 #include <linux/smp.h>
  17 #include <linux/types.h>
  18
  19 #include <asm/bcache.h>
  20 #include <asm/mips-cm.h>
  21 #include <asm/mips-cpc.h>
  22 #include <asm/mips_mt.h>
  23 #include <asm/mipsregs.h>
  24 #include <asm/pm-cps.h>
  25 #include <asm/r4kcache.h>
  26 #include <asm/smp-cps.h>
  27 #include <asm/time.h>
  28 #include <asm/uasm.h>
  29
  30 static DECLARE_BITMAP(core_power, NR_CPUS);
  31
  32 struct core_boot_config *mips_cps_core_bootcfg;
  33
  34 static unsigned core_vpe_count(unsigned core)
  35 {
  36         unsigned cfg;
  37
  38         if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
  39                 return 1;
  40
  41         write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
  42         cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
  43         return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
  44 }
  45
  46 static void __init cps_smp_setup(void)
  47 {
  48         unsigned int ncores, nvpes, core_vpes;
  49         int c, v;
  50
  51         /* Detect & record VPE topology */
  52         ncores = mips_cm_numcores();
  53         pr_info("VPE topology ");
  54         for (c = nvpes = 0; c < ncores; c++) {
  55                 core_vpes = core_vpe_count(c);
  56                 pr_cont("%c%u", c ? ',' : '{', core_vpes);
  57
  58                 /* Use the number of VPEs in core 0 for smp_num_siblings */
  59                 if (!c)
  60                         smp_num_siblings = core_vpes;
  61
  62                 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
  63                         cpu_data[nvpes + v].core = c;
  64 #ifdef CONFIG_MIPS_MT_SMP
  65                         cpu_data[nvpes + v].vpe_id = v;
  66 #endif
  67                 }
  68
  69                 nvpes += core_vpes;
  70         }
  71         pr_cont("} total %u\n", nvpes);
  72
  73         /* Indicate present CPUs (CPU being synonymous with VPE) */
  74         for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
  75                 set_cpu_possible(v, true);
  76                 set_cpu_present(v, true);
  77                 __cpu_number_map[v] = v;
  78                 __cpu_logical_map[v] = v;
  79         }
  80
  81         /* Set a coherent default CCA (CWB) */
  82         change_c0_config(CONF_CM_CMASK, 0x5);
  83
  84         /* Core 0 is powered up (we're running on it) */
  85         bitmap_set(core_power, 0, 1);
  86
  87         /* Initialise core 0 */
  88         mips_cps_core_init();
  89
  90         /* Make core 0 coherent with everything */
  91         write_gcr_cl_coherence(0xff);
  92
  93 #ifdef CONFIG_MIPS_MT_FPAFF
  94         /* If we have an FPU, enroll ourselves in the FPU-full mask */
  95         if (cpu_has_fpu)
  96                 cpumask_set_cpu(0, &mt_fpu_cpumask);
  97 #endif /* CONFIG_MIPS_MT_FPAFF */
  98 }
  99
 100 static void __init cps_prepare_cpus(unsigned int max_cpus)
 101 {
 102         unsigned ncores, core_vpes, c, cca;
 103         bool cca_unsuitable;
 104         u32 *entry_code;
 105
 106         mips_mt_set_cpuoptions();
 107
 108         /* Detect whether the CCA is unsuited to multi-core SMP */
 109         cca = read_c0_config() & CONF_CM_CMASK;
 110         switch (cca) {
 111         case 0x4: /* CWBE */
 112         case 0x5: /* CWB */
 113                 /* The CCA is coherent, multi-core is fine */
 114                 cca_unsuitable = false;
 115                 break;
 116
 117         default:
 118                 /* CCA is not coherent, multi-core is not usable */
 119                 cca_unsuitable = true;
 120         }
 121
 122         /* Warn the user if the CCA prevents multi-core */
 123         ncores = mips_cm_numcores();
 124         if (cca_unsuitable && ncores > 1) {
 125                 pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
 126                         cca);
 127
 128                 for_each_present_cpu(c) {
 129                         if (cpu_data[c].core)
 130                                 set_cpu_present(c, false);
 131                 }
 132         }
 133
 134         /*
 135          * Patch the start of mips_cps_core_entry to provide:
 136          *
 137          * s0 = kseg0 CCA
 138          */
 139         entry_code = (u32 *)&mips_cps_core_entry;
 140         uasm_i_addiu(&entry_code, 16, 0, cca);
 141         blast_dcache_range((unsigned long)&mips_cps_core_entry,
 142                            (unsigned long)entry_code);
 143         bc_wback_inv((unsigned long)&mips_cps_core_entry,
 144                      (void *)entry_code - (void *)&mips_cps_core_entry);
 145         __sync();
 146
 147         /* Allocate core boot configuration structs */
 148         mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
 149                                         GFP_KERNEL);
 150         if (!mips_cps_core_bootcfg) {
 151                 pr_err("Failed to allocate boot config for %u cores\n", ncores);
 152                 goto err_out;
 153         }
 154
 155         /* Allocate VPE boot configuration structs */
 156         for (c = 0; c < ncores; c++) {
 157                 core_vpes = core_vpe_count(c);
 158                 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
 159                                 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
 160                                 GFP_KERNEL);
 161                 if (!mips_cps_core_bootcfg[c].vpe_config) {
 162                         pr_err("Failed to allocate %u VPE boot configs\n",
 163                                core_vpes);
 164                         goto err_out;
 165                 }
 166         }
 167
 168         /* Mark this CPU as booted */
 169         atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
 170                    1 << cpu_vpe_id(&current_cpu_data));
 171
 172         return;
 173 err_out:
 174         /* Clean up allocations */
 175         if (mips_cps_core_bootcfg) {
 176                 for (c = 0; c < ncores; c++)
 177                         kfree(mips_cps_core_bootcfg[c].vpe_config);
 178                 kfree(mips_cps_core_bootcfg);
 179                 mips_cps_core_bootcfg = NULL;
 180         }
 181
 182         /* Effectively disable SMP by declaring CPUs not present */
 183         for_each_possible_cpu(c) {
 184                 if (c == 0)
 185                         continue;
 186                 set_cpu_present(c, false);
 187         }
 188 }
 189
 190 static void boot_core(unsigned core)
 191 {
 192         u32 access, stat, seq_state;
 193         unsigned timeout;
 194
 195         /* Select the appropriate core */
 196         write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
 197
 198         /* Set its reset vector */
 199         write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
 200
 201         /* Ensure its coherency is disabled */
 202         write_gcr_co_coherence(0);
 203
 204         /* Ensure the core can access the GCRs */
 205         access = read_gcr_access();
 206         access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
 207         write_gcr_access(access);
 208
 209         if (mips_cpc_present()) {
 210                 /* Reset the core */
 211                 mips_cpc_lock_other(core);
 212                 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
 213
 214                 timeout = 100;
 215                 while (true) {
 216                         stat = read_cpc_co_stat_conf();
 217                         seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK;
 218
 219                         /* U6 == coherent execution, ie. the core is up */
 220                         if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
 221                                 break;
 222
 223                         /* Delay a little while before we start warning */
 224                         if (timeout) {
 225                                 timeout--;
 226                                 mdelay(10);
 227                                 continue;
 228                         }
 229
 230                         pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
 231                                 core, stat);
 232                         mdelay(1000);
 233                 }
 234
 235                 mips_cpc_unlock_other();
 236         } else {
 237                 /* Take the core out of reset */
 238                 write_gcr_co_reset_release(0);
 239         }
 240
 241         /* The core is now powered up */
 242         bitmap_set(core_power, core, 1);
 243 }
 244
 245 static void remote_vpe_boot(void *dummy)
 246 {
 247         mips_cps_boot_vpes();
 248 }
 249
 250 static void cps_boot_secondary(int cpu, struct task_struct *idle)
 251 {
 252         unsigned core = cpu_data[cpu].core;
 253         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 254         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 255         struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
 256         unsigned int remote;
 257         int err;
 258
 259         vpe_cfg->pc = (unsigned long)&smp_bootstrap;
 260         vpe_cfg->sp = __KSTK_TOS(idle);
 261         vpe_cfg->gp = (unsigned long)task_thread_info(idle);
 262
 263         atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
 264
 265         preempt_disable();
 266
 267         if (!test_bit(core, core_power)) {
 268                 /* Boot a VPE on a powered down core */
 269                 boot_core(core);
 270                 goto out;
 271         }
 272
 273         if (core != current_cpu_data.core) {
 274                 /* Boot a VPE on another powered up core */
 275                 for (remote = 0; remote < NR_CPUS; remote++) {
 276                         if (cpu_data[remote].core != core)
 277                                 continue;
 278                         if (cpu_online(remote))
 279                                 break;
 280                 }
 281                 BUG_ON(remote >= NR_CPUS);
 282
 283                 err = smp_call_function_single(remote, remote_vpe_boot,
 284                                                NULL, 1);
 285                 if (err)
 286                         panic("Failed to call remote CPU\n");
 287                 goto out;
 288         }
 289
 290         BUG_ON(!cpu_has_mipsmt);
 291
 292         /* Boot a VPE on this core */
 293         mips_cps_boot_vpes();
 294 out:
 295         preempt_enable();
 296 }
 297
 298 static void cps_init_secondary(void)
 299 {
 300         /* Disable MT - we only want to run 1 TC per VPE */
 301         if (cpu_has_mipsmt)
 302                 dmt();
 303
 304         change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
 305                                  STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
 306 }
 307
 308 static void cps_smp_finish(void)
 309 {
 310         write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
 311
 312 #ifdef CONFIG_MIPS_MT_FPAFF
 313         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 314         if (cpu_has_fpu)
 315                 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
 316 #endif /* CONFIG_MIPS_MT_FPAFF */
 317
 318         local_irq_enable();
 319 }
 320
 321 #ifdef CONFIG_HOTPLUG_CPU
 322
 323 static int cps_cpu_disable(void)
 324 {
 325         unsigned cpu = smp_processor_id();
 326         struct core_boot_config *core_cfg;
 327
 328         if (!cpu)
 329                 return -EBUSY;
 330
 331         if (!cps_pm_support_state(CPS_PM_POWER_GATED))
 332                 return -EINVAL;
 333
 334         core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
 335         atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
 336         smp_mb__after_atomic();
 337         set_cpu_online(cpu, false);
 338         cpumask_clear_cpu(cpu, &cpu_callin_map);
 339
 340         return 0;
 341 }
 342
 343 static DECLARE_COMPLETION(cpu_death_chosen);
 344 static unsigned cpu_death_sibling;
 345 static enum {
 346         CPU_DEATH_HALT,
 347         CPU_DEATH_POWER,
 348 } cpu_death;
 349
 350 void play_dead(void)
 351 {
 352         unsigned cpu, core;
 353
 354         local_irq_disable();
 355         idle_task_exit();
 356         cpu = smp_processor_id();
 357         cpu_death = CPU_DEATH_POWER;
 358
 359         if (cpu_has_mipsmt) {
 360                 core = cpu_data[cpu].core;
 361
 362                 /* Look for another online VPE within the core */
 363                 for_each_online_cpu(cpu_death_sibling) {
 364                         if (cpu_data[cpu_death_sibling].core != core)
 365                                 continue;
 366
 367                         /*
 368                          * There is an online VPE within the core. Just halt
 369                          * this TC and leave the core alone.
 370                          */
 371                         cpu_death = CPU_DEATH_HALT;
 372                         break;
 373                 }
 374         }
 375
 376         /* This CPU has chosen its way out */
 377         complete(&cpu_death_chosen);
 378
 379         if (cpu_death == CPU_DEATH_HALT) {
 380                 /* Halt this TC */
 381                 write_c0_tchalt(TCHALT_H);
 382                 instruction_hazard();
 383         } else {
 384                 /* Power down the core */
 385                 cps_pm_enter_state(CPS_PM_POWER_GATED);
 386         }
 387
 388         /* This should never be reached */
 389         panic("Failed to offline CPU %u", cpu);
 390 }
 391
 392 static void wait_for_sibling_halt(void *ptr_cpu)
 393 {
 394         unsigned cpu = (unsigned long)ptr_cpu;
 395         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 396         unsigned halted;
 397         unsigned long flags;
 398
 399         do {
 400                 local_irq_save(flags);
 401                 settc(vpe_id);
 402                 halted = read_tc_c0_tchalt();
 403                 local_irq_restore(flags);
 404         } while (!(halted & TCHALT_H));
 405 }
 406
 407 static void cps_cpu_die(unsigned int cpu)
 408 {
 409         unsigned core = cpu_data[cpu].core;
 410         unsigned stat;
 411         int err;
 412
 413         /* Wait for the cpu to choose its way out */
 414         if (!wait_for_completion_timeout(&cpu_death_chosen,
 415                                          msecs_to_jiffies(5000))) {
 416                 pr_err("CPU%u: didn't offline\n", cpu);
 417                 return;
 418         }
 419
 420         /*
 421          * Now wait for the CPU to actually offline. Without doing this that
 422          * offlining may race with one or more of:
 423          *
 424          *   - Onlining the CPU again.
 425          *   - Powering down the core if another VPE within it is offlined.
 426          *   - A sibling VPE entering a non-coherent state.
 427          *
 428          * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
 429          * with which we could race, so do nothing.
 430          */
 431         if (cpu_death == CPU_DEATH_POWER) {
 432                 /*
 433                  * Wait for the core to enter a powered down or clock gated
 434                  * state, the latter happening when a JTAG probe is connected
 435                  * in which case the CPC will refuse to power down the core.
 436                  */
 437                 do {
 438                         mips_cpc_lock_other(core);
 439                         stat = read_cpc_co_stat_conf();
 440                         stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
 441                         mips_cpc_unlock_other();
 442                 } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
 443                          stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
 444                          stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
 445
 446                 /* Indicate the core is powered off */
 447                 bitmap_clear(core_power, core, 1);
 448         } else if (cpu_has_mipsmt) {
 449                 /*
 450                  * Have a CPU with access to the offlined CPUs registers wait
 451                  * for its TC to halt.
 452                  */
 453                 err = smp_call_function_single(cpu_death_sibling,
 454                                                wait_for_sibling_halt,
 455                                                (void *)(unsigned long)cpu, 1);
 456                 if (err)
 457                         panic("Failed to call remote sibling CPU\n");
 458         }
 459 }
 460
 461 #endif /* CONFIG_HOTPLUG_CPU */
 462
 463 static struct plat_smp_ops cps_smp_ops = {
 464         .smp_setup              = cps_smp_setup,
 465         .prepare_cpus           = cps_prepare_cpus,
 466         .boot_secondary         = cps_boot_secondary,
 467         .init_secondary         = cps_init_secondary,
 468         .smp_finish             = cps_smp_finish,
 469         .send_ipi_single        = gic_send_ipi_single,
 470         .send_ipi_mask          = gic_send_ipi_mask,
 471 #ifdef CONFIG_HOTPLUG_CPU
 472         .cpu_disable            = cps_cpu_disable,
 473         .cpu_die                = cps_cpu_die,
 474 #endif
 475 };
 476
 477 bool mips_cps_smp_in_use(void)
 478 {
 479         extern struct plat_smp_ops *mp_ops;
 480         return mp_ops == &cps_smp_ops;
 481 }
 482
 483 int register_cps_smp_ops(void)
 484 {
 485         if (!mips_cm_present()) {
 486                 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
 487                 return -ENODEV;
 488         }
 489
 490         /* check we have a GIC - we need one for IPIs */
 491         if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
 492                 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
 493                 return -ENODEV;
 494         }
 495
 496         register_smp_ops(&cps_smp_ops);
 497         return 0;
 498 }