4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 * Copyright (C) 2007, 2008 MIPS Technologies, Inc.
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/ptrace.h>
14 #include <linux/stddef.h>
17 #include <asm/mipsregs.h>
18 #include <asm/system.h>
19 #include <asm/r4kcache.h>
20 #include <asm/hazards.h>
23 * These definitions are correct for the 24K/34K/74K SPRAM sample
24 * implementation. The 4KS interpreted the tags differently...
26 #define SPRAM_TAG0_ENABLE 0x00000080
27 #define SPRAM_TAG0_PA_MASK 0xfffff000
28 #define SPRAM_TAG1_SIZE_MASK 0xfffff000
30 #define SPRAM_TAG_STRIDE 8
32 #define ERRCTL_SPRAM (1 << 28)
35 #define read_c0_errctl(x) read_c0_ecc(x)
36 #define write_c0_errctl(x) write_c0_ecc(x)
39 * Different semantics to the set_c0_* function built by __BUILD_SET_C0
41 static __cpuinit unsigned int bis_c0_errctl(unsigned int set)
44 res = read_c0_errctl();
45 write_c0_errctl(res | set);
49 static __cpuinit void ispram_store_tag(unsigned int offset, unsigned int data)
53 /* enable SPRAM tag access */
54 errctl = bis_c0_errctl(ERRCTL_SPRAM);
60 cache_op(Index_Store_Tag_I, CKSEG0|offset);
63 write_c0_errctl(errctl);
68 static __cpuinit unsigned int ispram_load_tag(unsigned int offset)
73 /* enable SPRAM tag access */
74 errctl = bis_c0_errctl(ERRCTL_SPRAM);
76 cache_op(Index_Load_Tag_I, CKSEG0 | offset);
78 data = read_c0_taglo();
80 write_c0_errctl(errctl);
86 static __cpuinit void dspram_store_tag(unsigned int offset, unsigned int data)
90 /* enable SPRAM tag access */
91 errctl = bis_c0_errctl(ERRCTL_SPRAM);
93 write_c0_dtaglo(data);
95 cache_op(Index_Store_Tag_D, CKSEG0 | offset);
97 write_c0_errctl(errctl);
102 static __cpuinit unsigned int dspram_load_tag(unsigned int offset)
107 errctl = bis_c0_errctl(ERRCTL_SPRAM);
109 cache_op(Index_Load_Tag_D, CKSEG0 | offset);
111 data = read_c0_dtaglo();
113 write_c0_errctl(errctl);
119 static __cpuinit void probe_spram(char *type,
121 unsigned int (*read)(unsigned int),
122 void (*write)(unsigned int, unsigned int))
124 unsigned int firstsize = 0, lastsize = 0;
125 unsigned int firstpa = 0, lastpa = 0, pa = 0;
126 unsigned int offset = 0;
127 unsigned int size, tag0, tag1;
128 unsigned int enabled;
132 * The limit is arbitrary but avoids the loop running away if
133 * the SPRAM tags are implemented differently
136 for (i = 0; i < 8; i++) {
138 tag1 = read(offset+SPRAM_TAG_STRIDE);
139 pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
140 type, i, tag0, tag1);
142 size = tag1 & SPRAM_TAG1_SIZE_MASK;
148 /* tags may repeat... */
149 if ((pa == firstpa && size == firstsize) ||
150 (pa == lastpa && size == lastsize))
154 /* Align base with size */
155 base = (base + size - 1) & ~(size-1);
157 /* reprogram the base address base address and enable */
158 tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
165 pa = tag0 & SPRAM_TAG0_PA_MASK;
166 enabled = tag0 & SPRAM_TAG0_ENABLE;
176 if (strcmp(type, "DSPRAM") == 0) {
177 unsigned int *vp = (unsigned int *)(CKSEG1 | pa);
179 #define TDAT 0x5a5aa5a5
187 printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
191 printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
195 pr_info("%s%d: PA=%08x,Size=%08x%s\n",
196 type, i, pa, size, enabled ? ",enabled" : "");
197 offset += 2 * SPRAM_TAG_STRIDE;
200 void __cpuinit spram_config(void)
202 struct cpuinfo_mips *c = ¤t_cpu_data;
203 unsigned int config0;
205 switch (c->cputype) {
210 config0 = read_c0_config();
211 /* FIXME: addresses are Malta specific */
212 if (config0 & (1<<24)) {
213 probe_spram("ISPRAM", 0x1c000000,
214 &ispram_load_tag, &ispram_store_tag);
216 if (config0 & (1<<23))
217 probe_spram("DSPRAM", 0x1c100000,
218 &dspram_load_tag, &dspram_store_tag);