2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
13 * Copyright (C) 2014, Imagination Technologies Ltd.
15 #include <linux/bug.h>
16 #include <linux/compiler.h>
17 #include <linux/context_tracking.h>
18 #include <linux/cpu_pm.h>
19 #include <linux/kexec.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
24 #include <linux/sched.h>
25 #include <linux/smp.h>
26 #include <linux/spinlock.h>
27 #include <linux/kallsyms.h>
28 #include <linux/bootmem.h>
29 #include <linux/interrupt.h>
30 #include <linux/ptrace.h>
31 #include <linux/kgdb.h>
32 #include <linux/kdebug.h>
33 #include <linux/kprobes.h>
34 #include <linux/notifier.h>
35 #include <linux/kdb.h>
36 #include <linux/irq.h>
37 #include <linux/perf_event.h>
39 #include <asm/bootinfo.h>
40 #include <asm/branch.h>
41 #include <asm/break.h>
44 #include <asm/cpu-type.h>
47 #include <asm/fpu_emulator.h>
49 #include <asm/mipsregs.h>
50 #include <asm/mipsmtregs.h>
51 #include <asm/module.h>
53 #include <asm/pgtable.h>
54 #include <asm/ptrace.h>
55 #include <asm/sections.h>
56 #include <asm/tlbdebug.h>
57 #include <asm/traps.h>
58 #include <asm/uaccess.h>
59 #include <asm/watch.h>
60 #include <asm/mmu_context.h>
61 #include <asm/types.h>
62 #include <asm/stacktrace.h>
65 extern void check_wait(void);
66 extern asmlinkage void rollback_handle_int(void);
67 extern asmlinkage void handle_int(void);
68 extern u32 handle_tlbl[];
69 extern u32 handle_tlbs[];
70 extern u32 handle_tlbm[];
71 extern asmlinkage void handle_adel(void);
72 extern asmlinkage void handle_ades(void);
73 extern asmlinkage void handle_ibe(void);
74 extern asmlinkage void handle_dbe(void);
75 extern asmlinkage void handle_sys(void);
76 extern asmlinkage void handle_bp(void);
77 extern asmlinkage void handle_ri(void);
78 extern asmlinkage void handle_ri_rdhwr_vivt(void);
79 extern asmlinkage void handle_ri_rdhwr(void);
80 extern asmlinkage void handle_cpu(void);
81 extern asmlinkage void handle_ov(void);
82 extern asmlinkage void handle_tr(void);
83 extern asmlinkage void handle_msa_fpe(void);
84 extern asmlinkage void handle_fpe(void);
85 extern asmlinkage void handle_ftlb(void);
86 extern asmlinkage void handle_msa(void);
87 extern asmlinkage void handle_mdmx(void);
88 extern asmlinkage void handle_watch(void);
89 extern asmlinkage void handle_mt(void);
90 extern asmlinkage void handle_dsp(void);
91 extern asmlinkage void handle_mcheck(void);
92 extern asmlinkage void handle_reserved(void);
93 extern void tlb_do_page_fault_0(void);
95 void (*board_be_init)(void);
96 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
97 void (*board_nmi_handler_setup)(void);
98 void (*board_ejtag_handler_setup)(void);
99 void (*board_bind_eic_interrupt)(int irq, int regset);
100 void (*board_ebase_setup)(void);
101 void(*board_cache_error_setup)(void);
103 static void show_raw_backtrace(unsigned long reg29)
105 unsigned long *sp = (unsigned long *)(reg29 & ~3);
108 printk("Call Trace:");
109 #ifdef CONFIG_KALLSYMS
112 while (!kstack_end(sp)) {
113 unsigned long __user *p =
114 (unsigned long __user *)(unsigned long)sp++;
115 if (__get_user(addr, p)) {
116 printk(" (Bad stack address)");
119 if (__kernel_text_address(addr))
125 #ifdef CONFIG_KALLSYMS
127 static int __init set_raw_show_trace(char *str)
132 __setup("raw_show_trace", set_raw_show_trace);
135 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
137 unsigned long sp = regs->regs[29];
138 unsigned long ra = regs->regs[31];
139 unsigned long pc = regs->cp0_epc;
144 if (raw_show_trace || !__kernel_text_address(pc)) {
145 show_raw_backtrace(sp);
148 printk("Call Trace:\n");
151 pc = unwind_stack(task, &sp, pc, &ra);
157 * This routine abuses get_user()/put_user() to reference pointers
158 * with at least a bit of error checking ...
160 static void show_stacktrace(struct task_struct *task,
161 const struct pt_regs *regs)
163 const int field = 2 * sizeof(unsigned long);
166 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
170 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
171 if (i && ((i % (64 / field)) == 0))
178 if (__get_user(stackdata, sp++)) {
179 printk(" (Bad stack address)");
183 printk(" %0*lx", field, stackdata);
187 show_backtrace(task, regs);
190 void show_stack(struct task_struct *task, unsigned long *sp)
194 regs.regs[29] = (unsigned long)sp;
198 if (task && task != current) {
199 regs.regs[29] = task->thread.reg29;
201 regs.cp0_epc = task->thread.reg31;
202 #ifdef CONFIG_KGDB_KDB
203 } else if (atomic_read(&kgdb_active) != -1 &&
205 memcpy(®s, kdb_current_regs, sizeof(regs));
206 #endif /* CONFIG_KGDB_KDB */
208 prepare_frametrace(®s);
211 show_stacktrace(task, ®s);
214 static void show_code(unsigned int __user *pc)
217 unsigned short __user *pc16 = NULL;
221 if ((unsigned long)pc & 1)
222 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
223 for(i = -3 ; i < 6 ; i++) {
225 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
226 printk(" (Bad address in epc)\n");
229 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
233 static void __show_regs(const struct pt_regs *regs)
235 const int field = 2 * sizeof(unsigned long);
236 unsigned int cause = regs->cp0_cause;
239 show_regs_print_info(KERN_DEFAULT);
242 * Saved main processor registers
244 for (i = 0; i < 32; ) {
248 printk(" %0*lx", field, 0UL);
249 else if (i == 26 || i == 27)
250 printk(" %*s", field, "");
252 printk(" %0*lx", field, regs->regs[i]);
259 #ifdef CONFIG_CPU_HAS_SMARTMIPS
260 printk("Acx : %0*lx\n", field, regs->acx);
262 printk("Hi : %0*lx\n", field, regs->hi);
263 printk("Lo : %0*lx\n", field, regs->lo);
266 * Saved cp0 registers
268 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
269 (void *) regs->cp0_epc);
270 printk(" %s\n", print_tainted());
271 printk("ra : %0*lx %pS\n", field, regs->regs[31],
272 (void *) regs->regs[31]);
274 printk("Status: %08x ", (uint32_t) regs->cp0_status);
277 if (regs->cp0_status & ST0_KUO)
279 if (regs->cp0_status & ST0_IEO)
281 if (regs->cp0_status & ST0_KUP)
283 if (regs->cp0_status & ST0_IEP)
285 if (regs->cp0_status & ST0_KUC)
287 if (regs->cp0_status & ST0_IEC)
289 } else if (cpu_has_4kex) {
290 if (regs->cp0_status & ST0_KX)
292 if (regs->cp0_status & ST0_SX)
294 if (regs->cp0_status & ST0_UX)
296 switch (regs->cp0_status & ST0_KSU) {
301 printk("SUPERVISOR ");
310 if (regs->cp0_status & ST0_ERL)
312 if (regs->cp0_status & ST0_EXL)
314 if (regs->cp0_status & ST0_IE)
319 printk("Cause : %08x\n", cause);
321 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
322 if (1 <= cause && cause <= 5)
323 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
325 printk("PrId : %08x (%s)\n", read_c0_prid(),
330 * FIXME: really the generic show_regs should take a const pointer argument.
332 void show_regs(struct pt_regs *regs)
334 __show_regs((struct pt_regs *)regs);
337 void show_registers(struct pt_regs *regs)
339 const int field = 2 * sizeof(unsigned long);
340 mm_segment_t old_fs = get_fs();
344 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
345 current->comm, current->pid, current_thread_info(), current,
346 field, current_thread_info()->tp_value);
347 if (cpu_has_userlocal) {
350 tls = read_c0_userlocal();
351 if (tls != current_thread_info()->tp_value)
352 printk("*HwTLS: %0*lx\n", field, tls);
355 if (!user_mode(regs))
356 /* Necessary for getting the correct stack content */
358 show_stacktrace(current, regs);
359 show_code((unsigned int __user *) regs->cp0_epc);
364 static int regs_to_trapnr(struct pt_regs *regs)
366 return (regs->cp0_cause >> 2) & 0x1f;
369 static DEFINE_RAW_SPINLOCK(die_lock);
371 void __noreturn die(const char *str, struct pt_regs *regs)
373 static int die_counter;
378 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs),
379 SIGSEGV) == NOTIFY_STOP)
383 raw_spin_lock_irq(&die_lock);
386 printk("%s[#%d]:\n", str, ++die_counter);
387 show_registers(regs);
388 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
389 raw_spin_unlock_irq(&die_lock);
394 panic("Fatal exception in interrupt");
397 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
399 panic("Fatal exception");
402 if (regs && kexec_should_crash(current))
408 extern struct exception_table_entry __start___dbe_table[];
409 extern struct exception_table_entry __stop___dbe_table[];
412 " .section __dbe_table, \"a\"\n"
415 /* Given an address, look for it in the exception tables. */
416 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
418 const struct exception_table_entry *e;
420 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
422 e = search_module_dbetables(addr);
426 asmlinkage void do_be(struct pt_regs *regs)
428 const int field = 2 * sizeof(unsigned long);
429 const struct exception_table_entry *fixup = NULL;
430 int data = regs->cp0_cause & 4;
431 int action = MIPS_BE_FATAL;
432 enum ctx_state prev_state;
434 prev_state = exception_enter();
435 /* XXX For now. Fixme, this searches the wrong table ... */
436 if (data && !user_mode(regs))
437 fixup = search_dbe_tables(exception_epc(regs));
440 action = MIPS_BE_FIXUP;
442 if (board_be_handler)
443 action = board_be_handler(regs, fixup != NULL);
446 case MIPS_BE_DISCARD:
450 regs->cp0_epc = fixup->nextinsn;
459 * Assume it would be too dangerous to continue ...
461 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
462 data ? "Data" : "Instruction",
463 field, regs->cp0_epc, field, regs->regs[31]);
464 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs),
465 SIGBUS) == NOTIFY_STOP)
468 die_if_kernel("Oops", regs);
469 force_sig(SIGBUS, current);
472 exception_exit(prev_state);
476 * ll/sc, rdhwr, sync emulation
479 #define OPCODE 0xfc000000
480 #define BASE 0x03e00000
481 #define RT 0x001f0000
482 #define OFFSET 0x0000ffff
483 #define LL 0xc0000000
484 #define SC 0xe0000000
485 #define SPEC0 0x00000000
486 #define SPEC3 0x7c000000
487 #define RD 0x0000f800
488 #define FUNC 0x0000003f
489 #define SYNC 0x0000000f
490 #define RDHWR 0x0000003b
492 /* microMIPS definitions */
493 #define MM_POOL32A_FUNC 0xfc00ffff
494 #define MM_RDHWR 0x00006b3c
495 #define MM_RS 0x001f0000
496 #define MM_RT 0x03e00000
499 * The ll_bit is cleared by r*_switch.S
503 struct task_struct *ll_task;
505 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
507 unsigned long value, __user *vaddr;
511 * analyse the ll instruction that just caused a ri exception
512 * and put the referenced address to addr.
515 /* sign extend offset */
516 offset = opcode & OFFSET;
520 vaddr = (unsigned long __user *)
521 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
523 if ((unsigned long)vaddr & 3)
525 if (get_user(value, vaddr))
530 if (ll_task == NULL || ll_task == current) {
539 regs->regs[(opcode & RT) >> 16] = value;
544 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
546 unsigned long __user *vaddr;
551 * analyse the sc instruction that just caused a ri exception
552 * and put the referenced address to addr.
555 /* sign extend offset */
556 offset = opcode & OFFSET;
560 vaddr = (unsigned long __user *)
561 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
562 reg = (opcode & RT) >> 16;
564 if ((unsigned long)vaddr & 3)
569 if (ll_bit == 0 || ll_task != current) {
577 if (put_user(regs->regs[reg], vaddr))
586 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
587 * opcodes are supposed to result in coprocessor unusable exceptions if
588 * executed on ll/sc-less processors. That's the theory. In practice a
589 * few processors such as NEC's VR4100 throw reserved instruction exceptions
590 * instead, so we're doing the emulation thing in both exception handlers.
592 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
594 if ((opcode & OPCODE) == LL) {
595 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
597 return simulate_ll(regs, opcode);
599 if ((opcode & OPCODE) == SC) {
600 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
602 return simulate_sc(regs, opcode);
605 return -1; /* Must be something else ... */
609 * Simulate trapping 'rdhwr' instructions to provide user accessible
610 * registers not implemented in hardware.
612 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
614 struct thread_info *ti = task_thread_info(current);
616 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
619 case 0: /* CPU number */
620 regs->regs[rt] = smp_processor_id();
622 case 1: /* SYNCI length */
623 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
624 current_cpu_data.icache.linesz);
626 case 2: /* Read count register */
627 regs->regs[rt] = read_c0_count();
629 case 3: /* Count register resolution */
630 switch (current_cpu_type()) {
640 regs->regs[rt] = ti->tp_value;
647 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
649 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
650 int rd = (opcode & RD) >> 11;
651 int rt = (opcode & RT) >> 16;
653 simulate_rdhwr(regs, rd, rt);
661 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
663 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
664 int rd = (opcode & MM_RS) >> 16;
665 int rt = (opcode & MM_RT) >> 21;
666 simulate_rdhwr(regs, rd, rt);
674 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
676 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
677 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
682 return -1; /* Must be something else ... */
685 asmlinkage void do_ov(struct pt_regs *regs)
687 enum ctx_state prev_state;
690 prev_state = exception_enter();
691 die_if_kernel("Integer overflow", regs);
693 info.si_code = FPE_INTOVF;
694 info.si_signo = SIGFPE;
696 info.si_addr = (void __user *) regs->cp0_epc;
697 force_sig_info(SIGFPE, &info, current);
698 exception_exit(prev_state);
701 int process_fpemu_return(int sig, void __user *fault_addr)
703 if (sig == SIGSEGV || sig == SIGBUS) {
704 struct siginfo si = {0};
705 si.si_addr = fault_addr;
707 if (sig == SIGSEGV) {
708 down_read(¤t->mm->mmap_sem);
709 if (find_vma(current->mm, (unsigned long)fault_addr))
710 si.si_code = SEGV_ACCERR;
712 si.si_code = SEGV_MAPERR;
713 up_read(¤t->mm->mmap_sem);
715 si.si_code = BUS_ADRERR;
717 force_sig_info(sig, &si, current);
720 force_sig(sig, current);
727 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
728 unsigned long old_epc, unsigned long old_ra)
730 union mips_instruction inst = { .word = opcode };
731 void __user *fault_addr = NULL;
734 /* If it's obviously not an FP instruction, skip it */
735 switch (inst.i_format.opcode) {
749 * do_ri skipped over the instruction via compute_return_epc, undo
750 * that for the FPU emulator.
752 regs->cp0_epc = old_epc;
753 regs->regs[31] = old_ra;
755 /* Save the FP context to struct thread_struct */
758 /* Run the emulator */
759 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
762 /* If something went wrong, signal */
763 process_fpemu_return(sig, fault_addr);
765 /* Restore the hardware register state */
772 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
774 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
776 enum ctx_state prev_state;
777 siginfo_t info = {0};
779 prev_state = exception_enter();
780 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs),
781 SIGFPE) == NOTIFY_STOP)
783 die_if_kernel("FP exception in kernel code", regs);
785 if (fcr31 & FPU_CSR_UNI_X) {
787 void __user *fault_addr = NULL;
790 * Unimplemented operation exception. If we've got the full
791 * software emulator on-board, let's use it...
793 * Force FPU to dump state into task/thread context. We're
794 * moving a lot of data here for what is probably a single
795 * instruction, but the alternative is to pre-decode the FP
796 * register operands before invoking the emulator, which seems
797 * a bit extreme for what should be an infrequent event.
799 /* Ensure 'resume' not overwrite saved fp context again. */
802 /* Run the emulator */
803 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
807 * We can't allow the emulated instruction to leave any of
808 * the cause bit set in $fcr31.
810 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
812 /* Restore the hardware register state */
813 own_fpu(1); /* Using the FPU again. */
815 /* If something went wrong, signal */
816 process_fpemu_return(sig, fault_addr);
819 } else if (fcr31 & FPU_CSR_INV_X)
820 info.si_code = FPE_FLTINV;
821 else if (fcr31 & FPU_CSR_DIV_X)
822 info.si_code = FPE_FLTDIV;
823 else if (fcr31 & FPU_CSR_OVF_X)
824 info.si_code = FPE_FLTOVF;
825 else if (fcr31 & FPU_CSR_UDF_X)
826 info.si_code = FPE_FLTUND;
827 else if (fcr31 & FPU_CSR_INE_X)
828 info.si_code = FPE_FLTRES;
830 info.si_code = __SI_FAULT;
831 info.si_signo = SIGFPE;
833 info.si_addr = (void __user *) regs->cp0_epc;
834 force_sig_info(SIGFPE, &info, current);
837 exception_exit(prev_state);
840 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
846 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
847 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
849 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
851 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs),
852 SIGTRAP) == NOTIFY_STOP)
856 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
857 * insns, even for trap and break codes that indicate arithmetic
858 * failures. Weird ...
859 * But should we continue the brokenness??? --macro
864 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
865 die_if_kernel(b, regs);
866 if (code == BRK_DIVZERO)
867 info.si_code = FPE_INTDIV;
869 info.si_code = FPE_INTOVF;
870 info.si_signo = SIGFPE;
872 info.si_addr = (void __user *) regs->cp0_epc;
873 force_sig_info(SIGFPE, &info, current);
876 die_if_kernel("Kernel bug detected", regs);
877 force_sig(SIGTRAP, current);
881 * Address errors may be deliberately induced by the FPU
882 * emulator to retake control of the CPU after executing the
883 * instruction in the delay slot of an emulated branch.
885 * Terminate if exception was recognized as a delay slot return
886 * otherwise handle as normal.
888 if (do_dsemulret(regs))
891 die_if_kernel("Math emu break/trap", regs);
892 force_sig(SIGTRAP, current);
895 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
896 die_if_kernel(b, regs);
897 force_sig(SIGTRAP, current);
901 asmlinkage void do_bp(struct pt_regs *regs)
903 unsigned int opcode, bcode;
904 enum ctx_state prev_state;
910 if (!user_mode(regs))
913 prev_state = exception_enter();
914 if (get_isa16_mode(regs->cp0_epc)) {
916 epc = exception_epc(regs);
918 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) ||
919 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))))
921 opcode = (instr[0] << 16) | instr[1];
924 if (__get_user(instr[0],
925 (u16 __user *)msk_isa16_mode(epc)))
927 bcode = (instr[0] >> 6) & 0x3f;
928 do_trap_or_bp(regs, bcode, "Break");
932 if (__get_user(opcode,
933 (unsigned int __user *) exception_epc(regs)))
938 * There is the ancient bug in the MIPS assemblers that the break
939 * code starts left to bit 16 instead to bit 6 in the opcode.
940 * Gas is bug-compatible, but not always, grrr...
941 * We handle both cases with a simple heuristics. --macro
943 bcode = ((opcode >> 6) & ((1 << 20) - 1));
944 if (bcode >= (1 << 10))
948 * notify the kprobe handlers, if instruction is likely to
953 if (notify_die(DIE_BREAK, "debug", regs, bcode,
954 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
958 case BRK_KPROBE_SSTEPBP:
959 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
960 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
968 do_trap_or_bp(regs, bcode, "Break");
972 exception_exit(prev_state);
976 force_sig(SIGSEGV, current);
980 asmlinkage void do_tr(struct pt_regs *regs)
982 u32 opcode, tcode = 0;
983 enum ctx_state prev_state;
986 unsigned long epc = msk_isa16_mode(exception_epc(regs));
989 if (!user_mode(regs))
992 prev_state = exception_enter();
993 if (get_isa16_mode(regs->cp0_epc)) {
994 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
995 __get_user(instr[1], (u16 __user *)(epc + 2)))
997 opcode = (instr[0] << 16) | instr[1];
998 /* Immediate versions don't provide a code. */
999 if (!(opcode & OPCODE))
1000 tcode = (opcode >> 12) & ((1 << 4) - 1);
1002 if (__get_user(opcode, (u32 __user *)epc))
1004 /* Immediate versions don't provide a code. */
1005 if (!(opcode & OPCODE))
1006 tcode = (opcode >> 6) & ((1 << 10) - 1);
1009 do_trap_or_bp(regs, tcode, "Trap");
1013 exception_exit(prev_state);
1017 force_sig(SIGSEGV, current);
1021 asmlinkage void do_ri(struct pt_regs *regs)
1023 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1024 unsigned long old_epc = regs->cp0_epc;
1025 unsigned long old31 = regs->regs[31];
1026 enum ctx_state prev_state;
1027 unsigned int opcode = 0;
1030 prev_state = exception_enter();
1031 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
1032 SIGILL) == NOTIFY_STOP)
1035 die_if_kernel("Reserved instruction in kernel code", regs);
1037 if (unlikely(compute_return_epc(regs) < 0))
1040 if (get_isa16_mode(regs->cp0_epc)) {
1041 unsigned short mmop[2] = { 0 };
1043 if (unlikely(get_user(mmop[0], epc) < 0))
1045 if (unlikely(get_user(mmop[1], epc) < 0))
1047 opcode = (mmop[0] << 16) | mmop[1];
1050 status = simulate_rdhwr_mm(regs, opcode);
1052 if (unlikely(get_user(opcode, epc) < 0))
1055 if (!cpu_has_llsc && status < 0)
1056 status = simulate_llsc(regs, opcode);
1059 status = simulate_rdhwr_normal(regs, opcode);
1062 status = simulate_sync(regs, opcode);
1065 status = simulate_fp(regs, opcode, old_epc, old31);
1071 if (unlikely(status > 0)) {
1072 regs->cp0_epc = old_epc; /* Undo skip-over. */
1073 regs->regs[31] = old31;
1074 force_sig(status, current);
1078 exception_exit(prev_state);
1082 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
1083 * emulated more than some threshold number of instructions, force migration to
1084 * a "CPU" that has FP support.
1086 static void mt_ase_fp_affinity(void)
1088 #ifdef CONFIG_MIPS_MT_FPAFF
1089 if (mt_fpemul_threshold > 0 &&
1090 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
1092 * If there's no FPU present, or if the application has already
1093 * restricted the allowed set to exclude any CPUs with FPUs,
1094 * we'll skip the procedure.
1096 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
1099 current->thread.user_cpus_allowed
1100 = current->cpus_allowed;
1101 cpus_and(tmask, current->cpus_allowed,
1103 set_cpus_allowed_ptr(current, &tmask);
1104 set_thread_flag(TIF_FPUBOUND);
1107 #endif /* CONFIG_MIPS_MT_FPAFF */
1111 * No lock; only written during early bootup by CPU 0.
1113 static RAW_NOTIFIER_HEAD(cu2_chain);
1115 int __ref register_cu2_notifier(struct notifier_block *nb)
1117 return raw_notifier_chain_register(&cu2_chain, nb);
1120 int cu2_notifier_call_chain(unsigned long val, void *v)
1122 return raw_notifier_call_chain(&cu2_chain, val, v);
1125 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
1128 struct pt_regs *regs = data;
1130 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
1131 "instruction", regs);
1132 force_sig(SIGILL, current);
1137 static int enable_restore_fp_context(int msa)
1139 int err, was_fpu_owner, prior_msa;
1142 /* First time FP context user. */
1148 set_thread_flag(TIF_USEDMSA);
1149 set_thread_flag(TIF_MSA_CTX_LIVE);
1158 * This task has formerly used the FP context.
1160 * If this thread has no live MSA vector context then we can simply
1161 * restore the scalar FP context. If it has live MSA vector context
1162 * (that is, it has or may have used MSA since last performing a
1163 * function call) then we'll need to restore the vector context. This
1164 * applies even if we're currently only executing a scalar FP
1165 * instruction. This is because if we were to later execute an MSA
1166 * instruction then we'd either have to:
1168 * - Restore the vector context & clobber any registers modified by
1169 * scalar FP instructions between now & then.
1173 * - Not restore the vector context & lose the most significant bits
1174 * of all vector registers.
1176 * Neither of those options is acceptable. We cannot restore the least
1177 * significant bits of the registers now & only restore the most
1178 * significant bits later because the most significant bits of any
1179 * vector registers whose aliased FP register is modified now will have
1180 * been zeroed. We'd have no way to know that when restoring the vector
1181 * context & thus may load an outdated value for the most significant
1182 * bits of a vector register.
1184 if (!msa && !thread_msa_context_live())
1188 * This task is using or has previously used MSA. Thus we require
1189 * that Status.FR == 1.
1192 was_fpu_owner = is_fpu_owner();
1193 err = own_fpu_inatomic(0);
1198 write_msa_csr(current->thread.fpu.msacsr);
1199 set_thread_flag(TIF_USEDMSA);
1202 * If this is the first time that the task is using MSA and it has
1203 * previously used scalar FP in this time slice then we already nave
1204 * FP context which we shouldn't clobber. We do however need to clear
1205 * the upper 64b of each vector register so that this task has no
1206 * opportunity to see data left behind by another.
1208 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1209 if (!prior_msa && was_fpu_owner) {
1217 * Restore the least significant 64b of each vector register
1218 * from the existing scalar FP context.
1220 _restore_fp(current);
1223 * The task has not formerly used MSA, so clear the upper 64b
1224 * of each vector register such that it cannot see data left
1225 * behind by another task.
1229 /* We need to restore the vector context. */
1230 restore_msa(current);
1232 /* Restore the scalar FP control & status register */
1234 write_32bit_cp1_register(CP1_STATUS,
1235 current->thread.fpu.fcr31);
1244 asmlinkage void do_cpu(struct pt_regs *regs)
1246 enum ctx_state prev_state;
1247 unsigned int __user *epc;
1248 unsigned long old_epc, old31;
1249 unsigned int opcode;
1252 unsigned long __maybe_unused flags;
1254 prev_state = exception_enter();
1255 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1258 die_if_kernel("do_cpu invoked from kernel context!", regs);
1262 epc = (unsigned int __user *)exception_epc(regs);
1263 old_epc = regs->cp0_epc;
1264 old31 = regs->regs[31];
1268 if (unlikely(compute_return_epc(regs) < 0))
1271 if (get_isa16_mode(regs->cp0_epc)) {
1272 unsigned short mmop[2] = { 0 };
1274 if (unlikely(get_user(mmop[0], epc) < 0))
1276 if (unlikely(get_user(mmop[1], epc) < 0))
1278 opcode = (mmop[0] << 16) | mmop[1];
1281 status = simulate_rdhwr_mm(regs, opcode);
1283 if (unlikely(get_user(opcode, epc) < 0))
1286 if (!cpu_has_llsc && status < 0)
1287 status = simulate_llsc(regs, opcode);
1290 status = simulate_rdhwr_normal(regs, opcode);
1296 if (unlikely(status > 0)) {
1297 regs->cp0_epc = old_epc; /* Undo skip-over. */
1298 regs->regs[31] = old31;
1299 force_sig(status, current);
1306 * Old (MIPS I and MIPS II) processors will set this code
1307 * for COP1X opcode instructions that replaced the original
1308 * COP3 space. We don't limit COP1 space instructions in
1309 * the emulator according to the CPU ISA, so we want to
1310 * treat COP1X instructions consistently regardless of which
1311 * code the CPU chose. Therefore we redirect this trap to
1312 * the FP emulator too.
1314 * Then some newer FPU-less processors use this code
1315 * erroneously too, so they are covered by this choice
1318 if (raw_cpu_has_fpu)
1323 err = enable_restore_fp_context(0);
1325 if (!raw_cpu_has_fpu || err) {
1327 void __user *fault_addr = NULL;
1328 sig = fpu_emulator_cop1Handler(regs,
1329 ¤t->thread.fpu,
1331 if (!process_fpemu_return(sig, fault_addr) && !err)
1332 mt_ase_fp_affinity();
1338 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1342 force_sig(SIGILL, current);
1345 exception_exit(prev_state);
1348 asmlinkage void do_msa_fpe(struct pt_regs *regs)
1350 enum ctx_state prev_state;
1352 prev_state = exception_enter();
1353 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
1354 force_sig(SIGFPE, current);
1355 exception_exit(prev_state);
1358 asmlinkage void do_msa(struct pt_regs *regs)
1360 enum ctx_state prev_state;
1363 prev_state = exception_enter();
1365 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
1366 force_sig(SIGILL, current);
1370 die_if_kernel("do_msa invoked from kernel context!", regs);
1372 err = enable_restore_fp_context(1);
1374 force_sig(SIGILL, current);
1376 exception_exit(prev_state);
1379 asmlinkage void do_mdmx(struct pt_regs *regs)
1381 enum ctx_state prev_state;
1383 prev_state = exception_enter();
1384 force_sig(SIGILL, current);
1385 exception_exit(prev_state);
1389 * Called with interrupts disabled.
1391 asmlinkage void do_watch(struct pt_regs *regs)
1393 enum ctx_state prev_state;
1396 prev_state = exception_enter();
1398 * Clear WP (bit 22) bit of cause register so we don't loop
1401 cause = read_c0_cause();
1402 cause &= ~(1 << 22);
1403 write_c0_cause(cause);
1406 * If the current thread has the watch registers loaded, save
1407 * their values and send SIGTRAP. Otherwise another thread
1408 * left the registers set, clear them and continue.
1410 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1411 mips_read_watch_registers();
1413 force_sig(SIGTRAP, current);
1415 mips_clear_watch_registers();
1418 exception_exit(prev_state);
1421 asmlinkage void do_mcheck(struct pt_regs *regs)
1423 const int field = 2 * sizeof(unsigned long);
1424 int multi_match = regs->cp0_status & ST0_TS;
1425 enum ctx_state prev_state;
1427 prev_state = exception_enter();
1431 pr_err("Index : %0x\n", read_c0_index());
1432 pr_err("Pagemask: %0x\n", read_c0_pagemask());
1433 pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi());
1434 pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1435 pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1436 pr_err("Wired : %0x\n", read_c0_wired());
1437 pr_err("Pagegrain: %0x\n", read_c0_pagegrain());
1439 pr_err("PWField : %0*lx\n", field, read_c0_pwfield());
1440 pr_err("PWSize : %0*lx\n", field, read_c0_pwsize());
1441 pr_err("PWCtl : %0x\n", read_c0_pwctl());
1447 show_code((unsigned int __user *) regs->cp0_epc);
1450 * Some chips may have other causes of machine check (e.g. SB1
1453 panic("Caught Machine Check exception - %scaused by multiple "
1454 "matching entries in the TLB.",
1455 (multi_match) ? "" : "not ");
1458 asmlinkage void do_mt(struct pt_regs *regs)
1462 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1463 >> VPECONTROL_EXCPT_SHIFT;
1466 printk(KERN_DEBUG "Thread Underflow\n");
1469 printk(KERN_DEBUG "Thread Overflow\n");
1472 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1475 printk(KERN_DEBUG "Gating Storage Exception\n");
1478 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1481 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
1484 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1488 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1490 force_sig(SIGILL, current);
1494 asmlinkage void do_dsp(struct pt_regs *regs)
1497 panic("Unexpected DSP exception");
1499 force_sig(SIGILL, current);
1502 asmlinkage void do_reserved(struct pt_regs *regs)
1505 * Game over - no way to handle this if it ever occurs. Most probably
1506 * caused by a new unknown cpu type or after another deadly
1507 * hard/software error.
1510 panic("Caught reserved exception %ld - should not happen.",
1511 (regs->cp0_cause & 0x7f) >> 2);
1514 static int __initdata l1parity = 1;
1515 static int __init nol1parity(char *s)
1520 __setup("nol1par", nol1parity);
1521 static int __initdata l2parity = 1;
1522 static int __init nol2parity(char *s)
1527 __setup("nol2par", nol2parity);
1530 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1531 * it different ways.
1533 static inline void parity_protection_init(void)
1535 switch (current_cpu_type()) {
1541 case CPU_INTERAPTIV:
1545 #define ERRCTL_PE 0x80000000
1546 #define ERRCTL_L2P 0x00800000
1547 unsigned long errctl;
1548 unsigned int l1parity_present, l2parity_present;
1550 errctl = read_c0_ecc();
1551 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1553 /* probe L1 parity support */
1554 write_c0_ecc(errctl | ERRCTL_PE);
1555 back_to_back_c0_hazard();
1556 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1558 /* probe L2 parity support */
1559 write_c0_ecc(errctl|ERRCTL_L2P);
1560 back_to_back_c0_hazard();
1561 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1563 if (l1parity_present && l2parity_present) {
1565 errctl |= ERRCTL_PE;
1566 if (l1parity ^ l2parity)
1567 errctl |= ERRCTL_L2P;
1568 } else if (l1parity_present) {
1570 errctl |= ERRCTL_PE;
1571 } else if (l2parity_present) {
1573 errctl |= ERRCTL_L2P;
1575 /* No parity available */
1578 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1580 write_c0_ecc(errctl);
1581 back_to_back_c0_hazard();
1582 errctl = read_c0_ecc();
1583 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1585 if (l1parity_present)
1586 printk(KERN_INFO "Cache parity protection %sabled\n",
1587 (errctl & ERRCTL_PE) ? "en" : "dis");
1589 if (l2parity_present) {
1590 if (l1parity_present && l1parity)
1591 errctl ^= ERRCTL_L2P;
1592 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1593 (errctl & ERRCTL_L2P) ? "en" : "dis");
1601 write_c0_ecc(0x80000000);
1602 back_to_back_c0_hazard();
1603 /* Set the PE bit (bit 31) in the c0_errctl register. */
1604 printk(KERN_INFO "Cache parity protection %sabled\n",
1605 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1609 /* Clear the DE bit (bit 16) in the c0_status register. */
1610 printk(KERN_INFO "Enable cache parity protection for "
1611 "MIPS 20KC/25KF CPUs.\n");
1612 clear_c0_status(ST0_DE);
1619 asmlinkage void cache_parity_error(void)
1621 const int field = 2 * sizeof(unsigned long);
1622 unsigned int reg_val;
1624 /* For the moment, report the problem and hang. */
1625 printk("Cache error exception:\n");
1626 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1627 reg_val = read_c0_cacheerr();
1628 printk("c0_cacheerr == %08x\n", reg_val);
1630 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1631 reg_val & (1<<30) ? "secondary" : "primary",
1632 reg_val & (1<<31) ? "data" : "insn");
1633 if (cpu_has_mips_r2 &&
1634 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1635 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1636 reg_val & (1<<29) ? "ED " : "",
1637 reg_val & (1<<28) ? "ET " : "",
1638 reg_val & (1<<27) ? "ES " : "",
1639 reg_val & (1<<26) ? "EE " : "",
1640 reg_val & (1<<25) ? "EB " : "",
1641 reg_val & (1<<24) ? "EI " : "",
1642 reg_val & (1<<23) ? "E1 " : "",
1643 reg_val & (1<<22) ? "E0 " : "");
1645 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1646 reg_val & (1<<29) ? "ED " : "",
1647 reg_val & (1<<28) ? "ET " : "",
1648 reg_val & (1<<26) ? "EE " : "",
1649 reg_val & (1<<25) ? "EB " : "",
1650 reg_val & (1<<24) ? "EI " : "",
1651 reg_val & (1<<23) ? "E1 " : "",
1652 reg_val & (1<<22) ? "E0 " : "");
1654 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1656 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1657 if (reg_val & (1<<22))
1658 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1660 if (reg_val & (1<<23))
1661 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1664 panic("Can't handle the cache error!");
1667 asmlinkage void do_ftlb(void)
1669 const int field = 2 * sizeof(unsigned long);
1670 unsigned int reg_val;
1672 /* For the moment, report the problem and hang. */
1673 if (cpu_has_mips_r2 &&
1674 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1675 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1677 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1678 reg_val = read_c0_cacheerr();
1679 pr_err("c0_cacheerr == %08x\n", reg_val);
1681 if ((reg_val & 0xc0000000) == 0xc0000000) {
1682 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1684 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1685 reg_val & (1<<30) ? "secondary" : "primary",
1686 reg_val & (1<<31) ? "data" : "insn");
1689 pr_err("FTLB error exception\n");
1691 /* Just print the cacheerr bits for now */
1692 cache_parity_error();
1696 * SDBBP EJTAG debug exception handler.
1697 * We skip the instruction and return to the next instruction.
1699 void ejtag_exception_handler(struct pt_regs *regs)
1701 const int field = 2 * sizeof(unsigned long);
1702 unsigned long depc, old_epc, old_ra;
1705 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1706 depc = read_c0_depc();
1707 debug = read_c0_debug();
1708 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1709 if (debug & 0x80000000) {
1711 * In branch delay slot.
1712 * We cheat a little bit here and use EPC to calculate the
1713 * debug return address (DEPC). EPC is restored after the
1716 old_epc = regs->cp0_epc;
1717 old_ra = regs->regs[31];
1718 regs->cp0_epc = depc;
1719 compute_return_epc(regs);
1720 depc = regs->cp0_epc;
1721 regs->cp0_epc = old_epc;
1722 regs->regs[31] = old_ra;
1725 write_c0_depc(depc);
1728 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1729 write_c0_debug(debug | 0x100);
1734 * NMI exception handler.
1735 * No lock; only written during early bootup by CPU 0.
1737 static RAW_NOTIFIER_HEAD(nmi_chain);
1739 int register_nmi_notifier(struct notifier_block *nb)
1741 return raw_notifier_chain_register(&nmi_chain, nb);
1744 void __noreturn nmi_exception_handler(struct pt_regs *regs)
1748 raw_notifier_call_chain(&nmi_chain, 0, regs);
1750 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1751 smp_processor_id(), regs->cp0_epc);
1752 regs->cp0_epc = read_c0_errorepc();
1756 #define VECTORSPACING 0x100 /* for EI/VI mode */
1758 unsigned long ebase;
1759 unsigned long exception_handlers[32];
1760 unsigned long vi_handlers[64];
1762 void __init *set_except_vector(int n, void *addr)
1764 unsigned long handler = (unsigned long) addr;
1765 unsigned long old_handler;
1767 #ifdef CONFIG_CPU_MICROMIPS
1769 * Only the TLB handlers are cache aligned with an even
1770 * address. All other handlers are on an odd address and
1771 * require no modification. Otherwise, MIPS32 mode will
1772 * be entered when handling any TLB exceptions. That
1773 * would be bad...since we must stay in microMIPS mode.
1775 if (!(handler & 0x1))
1778 old_handler = xchg(&exception_handlers[n], handler);
1780 if (n == 0 && cpu_has_divec) {
1781 #ifdef CONFIG_CPU_MICROMIPS
1782 unsigned long jump_mask = ~((1 << 27) - 1);
1784 unsigned long jump_mask = ~((1 << 28) - 1);
1786 u32 *buf = (u32 *)(ebase + 0x200);
1787 unsigned int k0 = 26;
1788 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1789 uasm_i_j(&buf, handler & ~jump_mask);
1792 UASM_i_LA(&buf, k0, handler);
1793 uasm_i_jr(&buf, k0);
1796 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1798 return (void *)old_handler;
1801 static void do_default_vi(void)
1803 show_regs(get_irq_regs());
1804 panic("Caught unexpected vectored interrupt.");
1807 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1809 unsigned long handler;
1810 unsigned long old_handler = vi_handlers[n];
1811 int srssets = current_cpu_data.srsets;
1815 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1818 handler = (unsigned long) do_default_vi;
1821 handler = (unsigned long) addr;
1822 vi_handlers[n] = handler;
1824 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1827 panic("Shadow register set %d not supported", srs);
1830 if (board_bind_eic_interrupt)
1831 board_bind_eic_interrupt(n, srs);
1832 } else if (cpu_has_vint) {
1833 /* SRSMap is only defined if shadow sets are implemented */
1835 change_c0_srsmap(0xf << n*4, srs << n*4);
1840 * If no shadow set is selected then use the default handler
1841 * that does normal register saving and standard interrupt exit
1843 extern char except_vec_vi, except_vec_vi_lui;
1844 extern char except_vec_vi_ori, except_vec_vi_end;
1845 extern char rollback_except_vec_vi;
1846 char *vec_start = using_rollback_handler() ?
1847 &rollback_except_vec_vi : &except_vec_vi;
1848 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1849 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1850 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1852 const int lui_offset = &except_vec_vi_lui - vec_start;
1853 const int ori_offset = &except_vec_vi_ori - vec_start;
1855 const int handler_len = &except_vec_vi_end - vec_start;
1857 if (handler_len > VECTORSPACING) {
1859 * Sigh... panicing won't help as the console
1860 * is probably not configured :(
1862 panic("VECTORSPACING too small");
1865 set_handler(((unsigned long)b - ebase), vec_start,
1866 #ifdef CONFIG_CPU_MICROMIPS
1871 h = (u16 *)(b + lui_offset);
1872 *h = (handler >> 16) & 0xffff;
1873 h = (u16 *)(b + ori_offset);
1874 *h = (handler & 0xffff);
1875 local_flush_icache_range((unsigned long)b,
1876 (unsigned long)(b+handler_len));
1880 * In other cases jump directly to the interrupt handler. It
1881 * is the handler's responsibility to save registers if required
1882 * (eg hi/lo) and return from the exception using "eret".
1888 #ifdef CONFIG_CPU_MICROMIPS
1889 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1891 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1893 h[0] = (insn >> 16) & 0xffff;
1894 h[1] = insn & 0xffff;
1897 local_flush_icache_range((unsigned long)b,
1898 (unsigned long)(b+8));
1901 return (void *)old_handler;
1904 void *set_vi_handler(int n, vi_handler_t addr)
1906 return set_vi_srs_handler(n, addr, 0);
1909 extern void tlb_init(void);
1914 int cp0_compare_irq;
1915 EXPORT_SYMBOL_GPL(cp0_compare_irq);
1916 int cp0_compare_irq_shift;
1919 * Performance counter IRQ or -1 if shared with timer
1921 int cp0_perfcount_irq;
1922 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1926 static int __init ulri_disable(char *s)
1928 pr_info("Disabling ulri\n");
1933 __setup("noulri", ulri_disable);
1935 /* configure STATUS register */
1936 static void configure_status(void)
1939 * Disable coprocessors and select 32-bit or 64-bit addressing
1940 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1941 * flag that some firmware may have left set and the TS bit (for
1942 * IP27). Set XX for ISA IV code to work.
1944 unsigned int status_set = ST0_CU0;
1946 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1948 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1949 status_set |= ST0_XX;
1951 status_set |= ST0_MX;
1953 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1957 /* configure HWRENA register */
1958 static void configure_hwrena(void)
1960 unsigned int hwrena = cpu_hwrena_impl_bits;
1962 if (cpu_has_mips_r2)
1963 hwrena |= 0x0000000f;
1965 if (!noulri && cpu_has_userlocal)
1966 hwrena |= (1 << 29);
1969 write_c0_hwrena(hwrena);
1972 static void configure_exception_vector(void)
1974 if (cpu_has_veic || cpu_has_vint) {
1975 unsigned long sr = set_c0_status(ST0_BEV);
1976 write_c0_ebase(ebase);
1977 write_c0_status(sr);
1978 /* Setting vector spacing enables EI/VI mode */
1979 change_c0_intctl(0x3e0, VECTORSPACING);
1981 if (cpu_has_divec) {
1982 if (cpu_has_mipsmt) {
1983 unsigned int vpflags = dvpe();
1984 set_c0_cause(CAUSEF_IV);
1987 set_c0_cause(CAUSEF_IV);
1991 void per_cpu_trap_init(bool is_boot_cpu)
1993 unsigned int cpu = smp_processor_id();
1998 configure_exception_vector();
2001 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2003 * o read IntCtl.IPTI to determine the timer interrupt
2004 * o read IntCtl.IPPCI to determine the performance counter interrupt
2006 if (cpu_has_mips_r2) {
2007 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2008 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2009 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
2010 if (cp0_perfcount_irq == cp0_compare_irq)
2011 cp0_perfcount_irq = -1;
2013 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
2014 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
2015 cp0_perfcount_irq = -1;
2018 if (!cpu_data[cpu].asid_cache)
2019 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
2021 atomic_inc(&init_mm.mm_count);
2022 current->active_mm = &init_mm;
2023 BUG_ON(current->mm);
2024 enter_lazy_tlb(&init_mm, current);
2026 /* Boot CPU's cache setup in setup_arch(). */
2030 TLBMISS_HANDLER_SETUP();
2033 /* Install CPU exception handler */
2034 void set_handler(unsigned long offset, void *addr, unsigned long size)
2036 #ifdef CONFIG_CPU_MICROMIPS
2037 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2039 memcpy((void *)(ebase + offset), addr, size);
2041 local_flush_icache_range(ebase + offset, ebase + offset + size);
2044 static char panic_null_cerr[] =
2045 "Trying to set NULL cache error exception handler";
2048 * Install uncached CPU exception handler.
2049 * This is suitable only for the cache error exception which is the only
2050 * exception handler that is being run uncached.
2052 void set_uncached_handler(unsigned long offset, void *addr,
2055 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
2058 panic(panic_null_cerr);
2060 memcpy((void *)(uncached_ebase + offset), addr, size);
2063 static int __initdata rdhwr_noopt;
2064 static int __init set_rdhwr_noopt(char *str)
2070 __setup("rdhwr_noopt", set_rdhwr_noopt);
2072 void __init trap_init(void)
2074 extern char except_vec3_generic;
2075 extern char except_vec4;
2076 extern char except_vec3_r4000;
2081 #if defined(CONFIG_KGDB)
2082 if (kgdb_early_setup)
2083 return; /* Already done */
2086 if (cpu_has_veic || cpu_has_vint) {
2087 unsigned long size = 0x200 + VECTORSPACING*64;
2088 ebase = (unsigned long)
2089 __alloc_bootmem(size, 1 << fls(size), 0);
2091 #ifdef CONFIG_KVM_GUEST
2092 #define KVM_GUEST_KSEG0 0x40000000
2093 ebase = KVM_GUEST_KSEG0;
2097 if (cpu_has_mips_r2)
2098 ebase += (read_c0_ebase() & 0x3ffff000);
2101 if (cpu_has_mmips) {
2102 unsigned int config3 = read_c0_config3();
2104 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2105 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2107 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2110 if (board_ebase_setup)
2111 board_ebase_setup();
2112 per_cpu_trap_init(true);
2115 * Copy the generic exception handlers to their final destination.
2116 * This will be overriden later as suitable for a particular
2119 set_handler(0x180, &except_vec3_generic, 0x80);
2122 * Setup default vectors
2124 for (i = 0; i <= 31; i++)
2125 set_except_vector(i, handle_reserved);
2128 * Copy the EJTAG debug exception vector handler code to it's final
2131 if (cpu_has_ejtag && board_ejtag_handler_setup)
2132 board_ejtag_handler_setup();
2135 * Only some CPUs have the watch exceptions.
2138 set_except_vector(23, handle_watch);
2141 * Initialise interrupt handlers
2143 if (cpu_has_veic || cpu_has_vint) {
2144 int nvec = cpu_has_veic ? 64 : 8;
2145 for (i = 0; i < nvec; i++)
2146 set_vi_handler(i, NULL);
2148 else if (cpu_has_divec)
2149 set_handler(0x200, &except_vec4, 0x8);
2152 * Some CPUs can enable/disable for cache parity detection, but does
2153 * it different ways.
2155 parity_protection_init();
2158 * The Data Bus Errors / Instruction Bus Errors are signaled
2159 * by external hardware. Therefore these two exceptions
2160 * may have board specific handlers.
2165 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
2167 set_except_vector(1, handle_tlbm);
2168 set_except_vector(2, handle_tlbl);
2169 set_except_vector(3, handle_tlbs);
2171 set_except_vector(4, handle_adel);
2172 set_except_vector(5, handle_ades);
2174 set_except_vector(6, handle_ibe);
2175 set_except_vector(7, handle_dbe);
2177 set_except_vector(8, handle_sys);
2178 set_except_vector(9, handle_bp);
2179 set_except_vector(10, rdhwr_noopt ? handle_ri :
2180 (cpu_has_vtag_icache ?
2181 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
2182 set_except_vector(11, handle_cpu);
2183 set_except_vector(12, handle_ov);
2184 set_except_vector(13, handle_tr);
2185 set_except_vector(14, handle_msa_fpe);
2187 if (current_cpu_type() == CPU_R6000 ||
2188 current_cpu_type() == CPU_R6000A) {
2190 * The R6000 is the only R-series CPU that features a machine
2191 * check exception (similar to the R4000 cache error) and
2192 * unaligned ldc1/sdc1 exception. The handlers have not been
2193 * written yet. Well, anyway there is no R6000 machine on the
2194 * current list of targets for Linux/MIPS.
2195 * (Duh, crap, there is someone with a triple R6k machine)
2197 //set_except_vector(14, handle_mc);
2198 //set_except_vector(15, handle_ndc);
2202 if (board_nmi_handler_setup)
2203 board_nmi_handler_setup();
2205 if (cpu_has_fpu && !cpu_has_nofpuex)
2206 set_except_vector(15, handle_fpe);
2208 set_except_vector(16, handle_ftlb);
2210 if (cpu_has_rixiex) {
2211 set_except_vector(19, tlb_do_page_fault_0);
2212 set_except_vector(20, tlb_do_page_fault_0);
2215 set_except_vector(21, handle_msa);
2216 set_except_vector(22, handle_mdmx);
2219 set_except_vector(24, handle_mcheck);
2222 set_except_vector(25, handle_mt);
2224 set_except_vector(26, handle_dsp);
2226 if (board_cache_error_setup)
2227 board_cache_error_setup();
2230 /* Special exception: R4[04]00 uses also the divec space. */
2231 set_handler(0x180, &except_vec3_r4000, 0x100);
2232 else if (cpu_has_4kex)
2233 set_handler(0x180, &except_vec3_generic, 0x80);
2235 set_handler(0x080, &except_vec3_generic, 0x80);
2237 local_flush_icache_range(ebase, ebase + 0x400);
2239 sort_extable(__start___dbe_table, __stop___dbe_table);
2241 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
2244 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2248 case CPU_PM_ENTER_FAILED:
2252 configure_exception_vector();
2254 /* Restore register with CPU number for TLB handlers */
2255 TLBMISS_HANDLER_RESTORE();
2263 static struct notifier_block trap_pm_notifier_block = {
2264 .notifier_call = trap_pm_notifier,
2267 static int __init trap_pm_init(void)
2269 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2271 arch_initcall(trap_pm_init);