2 * Handle unaligned accesses by emulation.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2014 Imagination Technologies Ltd.
12 * This file contains exception handler for address error exception with the
13 * special capability to execute faulting instructions in software. The
14 * handler does not try to handle the case when the program counter points
15 * to an address not aligned to a word boundary.
17 * Putting data to unaligned addresses is a bad practice even on Intel where
18 * only the performance is affected. Much worse is that such code is non-
19 * portable. Due to several programs that die on MIPS due to alignment
20 * problems I decided to implement this handler anyway though I originally
21 * didn't intend to do this at all for user code.
23 * For now I enable fixing of address errors by default to make life easier.
24 * I however intend to disable this somewhen in the future when the alignment
25 * problems with user programs have been fixed. For programmers this is the
28 * Fixing address errors is a per process option. The option is inherited
29 * across fork(2) and execve(2) calls. If you really want to use the
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
33 * #include <sys/sysmips.h>
36 * sysmips(MIPS_FIXADE, x);
39 * The argument x is 0 for disabling software emulation, enabled otherwise.
41 * Below a little program to play around with this feature.
44 * #include <sys/sysmips.h>
47 * unsigned char bar[8];
50 * main(int argc, char *argv[])
52 * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
53 * unsigned int *p = (unsigned int *) (x.bar + 3);
57 * sysmips(MIPS_FIXADE, atoi(argv[1]));
59 * printf("*p = %08lx\n", *p);
63 * for(i = 0; i <= 7; i++)
64 * printf("%02x ", x.bar[i]);
68 * Coprocessor loads are not supported; I think this case is unimportant
71 * TODO: Handle ndc (attempted store to doubleword in uncached memory)
72 * exception for the R6000.
73 * A store crossing a page boundary might be executed only partially.
74 * Undo the partial store in this case.
76 #include <linux/context_tracking.h>
78 #include <linux/signal.h>
79 #include <linux/smp.h>
80 #include <linux/sched.h>
81 #include <linux/debugfs.h>
82 #include <linux/perf_event.h>
85 #include <asm/branch.h>
86 #include <asm/byteorder.h>
89 #include <asm/fpu_emulator.h>
91 #include <asm/uaccess.h>
93 #include <asm/fpu_emulator.h>
95 #define STR(x) __STR(x)
99 UNALIGNED_ACTION_QUIET,
100 UNALIGNED_ACTION_SIGNAL,
101 UNALIGNED_ACTION_SHOW,
103 #ifdef CONFIG_DEBUG_FS
104 static u32 unaligned_instructions;
105 static u32 unaligned_action;
107 #define unaligned_action UNALIGNED_ACTION_QUIET
109 extern void show_registers(struct pt_regs *regs);
112 #define LoadHW(addr, value, res) \
113 __asm__ __volatile__ (".set\tnoat\n" \
114 "1:\t"user_lb("%0", "0(%2)")"\n" \
115 "2:\t"user_lbu("$1", "1(%2)")"\n\t" \
121 ".section\t.fixup,\"ax\"\n\t" \
122 "4:\tli\t%1, %3\n\t" \
125 ".section\t__ex_table,\"a\"\n\t" \
126 STR(PTR)"\t1b, 4b\n\t" \
127 STR(PTR)"\t2b, 4b\n\t" \
129 : "=&r" (value), "=r" (res) \
130 : "r" (addr), "i" (-EFAULT));
132 #define LoadW(addr, value, res) \
133 __asm__ __volatile__ ( \
134 "1:\t"user_lwl("%0", "(%2)")"\n" \
135 "2:\t"user_lwr("%0", "3(%2)")"\n\t" \
139 ".section\t.fixup,\"ax\"\n\t" \
140 "4:\tli\t%1, %3\n\t" \
143 ".section\t__ex_table,\"a\"\n\t" \
144 STR(PTR)"\t1b, 4b\n\t" \
145 STR(PTR)"\t2b, 4b\n\t" \
147 : "=&r" (value), "=r" (res) \
148 : "r" (addr), "i" (-EFAULT));
150 #define LoadHWU(addr, value, res) \
151 __asm__ __volatile__ ( \
153 "1:\t"user_lbu("%0", "0(%2)")"\n" \
154 "2:\t"user_lbu("$1", "1(%2)")"\n\t" \
161 ".section\t.fixup,\"ax\"\n\t" \
162 "4:\tli\t%1, %3\n\t" \
165 ".section\t__ex_table,\"a\"\n\t" \
166 STR(PTR)"\t1b, 4b\n\t" \
167 STR(PTR)"\t2b, 4b\n\t" \
169 : "=&r" (value), "=r" (res) \
170 : "r" (addr), "i" (-EFAULT));
172 #define LoadWU(addr, value, res) \
173 __asm__ __volatile__ ( \
174 "1:\t"user_lwl("%0", "(%2)")"\n" \
175 "2:\t"user_lwr("%0", "3(%2)")"\n\t" \
176 "dsll\t%0, %0, 32\n\t" \
177 "dsrl\t%0, %0, 32\n\t" \
181 "\t.section\t.fixup,\"ax\"\n\t" \
182 "4:\tli\t%1, %3\n\t" \
185 ".section\t__ex_table,\"a\"\n\t" \
186 STR(PTR)"\t1b, 4b\n\t" \
187 STR(PTR)"\t2b, 4b\n\t" \
189 : "=&r" (value), "=r" (res) \
190 : "r" (addr), "i" (-EFAULT));
192 #define LoadDW(addr, value, res) \
193 __asm__ __volatile__ ( \
194 "1:\tldl\t%0, (%2)\n" \
195 "2:\tldr\t%0, 7(%2)\n\t" \
199 "\t.section\t.fixup,\"ax\"\n\t" \
200 "4:\tli\t%1, %3\n\t" \
203 ".section\t__ex_table,\"a\"\n\t" \
204 STR(PTR)"\t1b, 4b\n\t" \
205 STR(PTR)"\t2b, 4b\n\t" \
207 : "=&r" (value), "=r" (res) \
208 : "r" (addr), "i" (-EFAULT));
210 #define StoreHW(addr, value, res) \
211 __asm__ __volatile__ ( \
213 "1:\t"user_sb("%1", "1(%2)")"\n" \
214 "srl\t$1, %1, 0x8\n" \
215 "2:\t"user_sb("$1", "0(%2)")"\n" \
220 ".section\t.fixup,\"ax\"\n\t" \
221 "4:\tli\t%0, %3\n\t" \
224 ".section\t__ex_table,\"a\"\n\t" \
225 STR(PTR)"\t1b, 4b\n\t" \
226 STR(PTR)"\t2b, 4b\n\t" \
229 : "r" (value), "r" (addr), "i" (-EFAULT));
231 #define StoreW(addr, value, res) \
232 __asm__ __volatile__ ( \
233 "1:\t"user_swl("%1", "(%2)")"\n" \
234 "2:\t"user_swr("%1", "3(%2)")"\n\t" \
238 ".section\t.fixup,\"ax\"\n\t" \
239 "4:\tli\t%0, %3\n\t" \
242 ".section\t__ex_table,\"a\"\n\t" \
243 STR(PTR)"\t1b, 4b\n\t" \
244 STR(PTR)"\t2b, 4b\n\t" \
247 : "r" (value), "r" (addr), "i" (-EFAULT));
249 #define StoreDW(addr, value, res) \
250 __asm__ __volatile__ ( \
251 "1:\tsdl\t%1,(%2)\n" \
252 "2:\tsdr\t%1, 7(%2)\n\t" \
256 ".section\t.fixup,\"ax\"\n\t" \
257 "4:\tli\t%0, %3\n\t" \
260 ".section\t__ex_table,\"a\"\n\t" \
261 STR(PTR)"\t1b, 4b\n\t" \
262 STR(PTR)"\t2b, 4b\n\t" \
265 : "r" (value), "r" (addr), "i" (-EFAULT));
268 #ifdef __LITTLE_ENDIAN
269 #define LoadHW(addr, value, res) \
270 __asm__ __volatile__ (".set\tnoat\n" \
271 "1:\t"user_lb("%0", "1(%2)")"\n" \
272 "2:\t"user_lbu("$1", "0(%2)")"\n\t" \
278 ".section\t.fixup,\"ax\"\n\t" \
279 "4:\tli\t%1, %3\n\t" \
282 ".section\t__ex_table,\"a\"\n\t" \
283 STR(PTR)"\t1b, 4b\n\t" \
284 STR(PTR)"\t2b, 4b\n\t" \
286 : "=&r" (value), "=r" (res) \
287 : "r" (addr), "i" (-EFAULT));
289 #define LoadW(addr, value, res) \
290 __asm__ __volatile__ ( \
291 "1:\t"user_lwl("%0", "3(%2)")"\n" \
292 "2:\t"user_lwr("%0", "(%2)")"\n\t" \
296 ".section\t.fixup,\"ax\"\n\t" \
297 "4:\tli\t%1, %3\n\t" \
300 ".section\t__ex_table,\"a\"\n\t" \
301 STR(PTR)"\t1b, 4b\n\t" \
302 STR(PTR)"\t2b, 4b\n\t" \
304 : "=&r" (value), "=r" (res) \
305 : "r" (addr), "i" (-EFAULT));
307 #define LoadHWU(addr, value, res) \
308 __asm__ __volatile__ ( \
310 "1:\t"user_lbu("%0", "1(%2)")"\n" \
311 "2:\t"user_lbu("$1", "0(%2)")"\n\t" \
318 ".section\t.fixup,\"ax\"\n\t" \
319 "4:\tli\t%1, %3\n\t" \
322 ".section\t__ex_table,\"a\"\n\t" \
323 STR(PTR)"\t1b, 4b\n\t" \
324 STR(PTR)"\t2b, 4b\n\t" \
326 : "=&r" (value), "=r" (res) \
327 : "r" (addr), "i" (-EFAULT));
329 #define LoadWU(addr, value, res) \
330 __asm__ __volatile__ ( \
331 "1:\t"user_lwl("%0", "3(%2)")"\n" \
332 "2:\t"user_lwr("%0", "(%2)")"\n\t" \
333 "dsll\t%0, %0, 32\n\t" \
334 "dsrl\t%0, %0, 32\n\t" \
338 "\t.section\t.fixup,\"ax\"\n\t" \
339 "4:\tli\t%1, %3\n\t" \
342 ".section\t__ex_table,\"a\"\n\t" \
343 STR(PTR)"\t1b, 4b\n\t" \
344 STR(PTR)"\t2b, 4b\n\t" \
346 : "=&r" (value), "=r" (res) \
347 : "r" (addr), "i" (-EFAULT));
349 #define LoadDW(addr, value, res) \
350 __asm__ __volatile__ ( \
351 "1:\tldl\t%0, 7(%2)\n" \
352 "2:\tldr\t%0, (%2)\n\t" \
356 "\t.section\t.fixup,\"ax\"\n\t" \
357 "4:\tli\t%1, %3\n\t" \
360 ".section\t__ex_table,\"a\"\n\t" \
361 STR(PTR)"\t1b, 4b\n\t" \
362 STR(PTR)"\t2b, 4b\n\t" \
364 : "=&r" (value), "=r" (res) \
365 : "r" (addr), "i" (-EFAULT));
367 #define StoreHW(addr, value, res) \
368 __asm__ __volatile__ ( \
370 "1:\t"user_sb("%1", "0(%2)")"\n" \
371 "srl\t$1,%1, 0x8\n" \
372 "2:\t"user_sb("$1", "1(%2)")"\n" \
377 ".section\t.fixup,\"ax\"\n\t" \
378 "4:\tli\t%0, %3\n\t" \
381 ".section\t__ex_table,\"a\"\n\t" \
382 STR(PTR)"\t1b, 4b\n\t" \
383 STR(PTR)"\t2b, 4b\n\t" \
386 : "r" (value), "r" (addr), "i" (-EFAULT));
388 #define StoreW(addr, value, res) \
389 __asm__ __volatile__ ( \
390 "1:\t"user_swl("%1", "3(%2)")"\n" \
391 "2:\t"user_swr("%1", "(%2)")"\n\t" \
395 ".section\t.fixup,\"ax\"\n\t" \
396 "4:\tli\t%0, %3\n\t" \
399 ".section\t__ex_table,\"a\"\n\t" \
400 STR(PTR)"\t1b, 4b\n\t" \
401 STR(PTR)"\t2b, 4b\n\t" \
404 : "r" (value), "r" (addr), "i" (-EFAULT));
406 #define StoreDW(addr, value, res) \
407 __asm__ __volatile__ ( \
408 "1:\tsdl\t%1, 7(%2)\n" \
409 "2:\tsdr\t%1, (%2)\n\t" \
413 ".section\t.fixup,\"ax\"\n\t" \
414 "4:\tli\t%0, %3\n\t" \
417 ".section\t__ex_table,\"a\"\n\t" \
418 STR(PTR)"\t1b, 4b\n\t" \
419 STR(PTR)"\t2b, 4b\n\t" \
422 : "r" (value), "r" (addr), "i" (-EFAULT));
425 static void emulate_load_store_insn(struct pt_regs *regs,
426 void __user *addr, unsigned int __user *pc)
428 union mips_instruction insn;
431 unsigned long origpc;
432 unsigned long orig31;
433 void __user *fault_addr = NULL;
437 origpc = (unsigned long)pc;
438 orig31 = regs->regs[31];
440 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
443 * This load never faults.
445 __get_user(insn.word, pc);
447 switch (insn.i_format.opcode) {
449 * These are instructions that a compiler doesn't generate. We
450 * can assume therefore that the code is MIPS-aware and
451 * really buggy. Emulating these instructions would break the
460 * For these instructions the only way to create an address
461 * error is an attempted access to kernel/supervisor address
478 * The remaining opcodes are the ones that are really of
484 * we can land here only from kernel accessing user memory,
485 * so we need to "switch" the address limit to user space, so
486 * address check can work properly.
490 switch (insn.spec3_format.func) {
492 if (!access_ok(VERIFY_READ, addr, 2)) {
496 LoadHW(addr, value, res);
501 compute_return_epc(regs);
502 regs->regs[insn.spec3_format.rt] = value;
505 if (!access_ok(VERIFY_READ, addr, 4)) {
509 LoadW(addr, value, res);
514 compute_return_epc(regs);
515 regs->regs[insn.spec3_format.rt] = value;
518 if (!access_ok(VERIFY_READ, addr, 2)) {
522 LoadHWU(addr, value, res);
527 compute_return_epc(regs);
528 regs->regs[insn.spec3_format.rt] = value;
531 if (!access_ok(VERIFY_WRITE, addr, 2)) {
535 compute_return_epc(regs);
536 value = regs->regs[insn.spec3_format.rt];
537 StoreHW(addr, value, res);
544 if (!access_ok(VERIFY_WRITE, addr, 4)) {
548 compute_return_epc(regs);
549 value = regs->regs[insn.spec3_format.rt];
550 StoreW(addr, value, res);
564 if (!access_ok(VERIFY_READ, addr, 2))
567 LoadHW(addr, value, res);
570 compute_return_epc(regs);
571 regs->regs[insn.i_format.rt] = value;
575 if (!access_ok(VERIFY_READ, addr, 4))
578 LoadW(addr, value, res);
581 compute_return_epc(regs);
582 regs->regs[insn.i_format.rt] = value;
586 if (!access_ok(VERIFY_READ, addr, 2))
589 LoadHWU(addr, value, res);
592 compute_return_epc(regs);
593 regs->regs[insn.i_format.rt] = value;
599 * A 32-bit kernel might be running on a 64-bit processor. But
600 * if we're on a 32-bit processor and an i-cache incoherency
601 * or race makes us see a 64-bit instruction here the sdl/sdr
602 * would blow up, so for now we don't handle unaligned 64-bit
603 * instructions on 32-bit kernels.
605 if (!access_ok(VERIFY_READ, addr, 4))
608 LoadWU(addr, value, res);
611 compute_return_epc(regs);
612 regs->regs[insn.i_format.rt] = value;
614 #endif /* CONFIG_64BIT */
616 /* Cannot handle 64-bit instructions in 32-bit kernel */
622 * A 32-bit kernel might be running on a 64-bit processor. But
623 * if we're on a 32-bit processor and an i-cache incoherency
624 * or race makes us see a 64-bit instruction here the sdl/sdr
625 * would blow up, so for now we don't handle unaligned 64-bit
626 * instructions on 32-bit kernels.
628 if (!access_ok(VERIFY_READ, addr, 8))
631 LoadDW(addr, value, res);
634 compute_return_epc(regs);
635 regs->regs[insn.i_format.rt] = value;
637 #endif /* CONFIG_64BIT */
639 /* Cannot handle 64-bit instructions in 32-bit kernel */
643 if (!access_ok(VERIFY_WRITE, addr, 2))
646 compute_return_epc(regs);
647 value = regs->regs[insn.i_format.rt];
648 StoreHW(addr, value, res);
654 if (!access_ok(VERIFY_WRITE, addr, 4))
657 compute_return_epc(regs);
658 value = regs->regs[insn.i_format.rt];
659 StoreW(addr, value, res);
667 * A 32-bit kernel might be running on a 64-bit processor. But
668 * if we're on a 32-bit processor and an i-cache incoherency
669 * or race makes us see a 64-bit instruction here the sdl/sdr
670 * would blow up, so for now we don't handle unaligned 64-bit
671 * instructions on 32-bit kernels.
673 if (!access_ok(VERIFY_WRITE, addr, 8))
676 compute_return_epc(regs);
677 value = regs->regs[insn.i_format.rt];
678 StoreDW(addr, value, res);
682 #endif /* CONFIG_64BIT */
684 /* Cannot handle 64-bit instructions in 32-bit kernel */
691 die_if_kernel("Unaligned FP access in kernel code", regs);
692 BUG_ON(!used_math());
693 BUG_ON(!is_fpu_owner());
695 lose_fpu(1); /* Save FPU state for the emulator. */
696 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
698 own_fpu(1); /* Restore FPU state. */
700 /* Signal if something went wrong. */
701 process_fpemu_return(res, fault_addr);
708 * COP2 is available to implementor for application specific use.
709 * It's up to applications to register a notifier chain and do
710 * whatever they have to do, including possible sending of signals.
713 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
717 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
721 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
725 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
730 * Pheeee... We encountered an yet unknown instruction or
731 * cache coherence problem. Die sucker, die ...
736 #ifdef CONFIG_DEBUG_FS
737 unaligned_instructions++;
743 /* roll back jump/branch */
744 regs->cp0_epc = origpc;
745 regs->regs[31] = orig31;
746 /* Did we have an exception handler installed? */
747 if (fixup_exception(regs))
750 die_if_kernel("Unhandled kernel unaligned access", regs);
751 force_sig(SIGSEGV, current);
756 die_if_kernel("Unhandled kernel unaligned access", regs);
757 force_sig(SIGBUS, current);
763 ("Unhandled kernel unaligned access or invalid instruction", regs);
764 force_sig(SIGILL, current);
767 /* Recode table from 16-bit register notation to 32-bit GPR. */
768 const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
770 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
771 const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
773 static void emulate_load_store_microMIPS(struct pt_regs *regs,
779 unsigned int reg = 0, rvar;
780 unsigned long orig31;
784 unsigned long origpc, contpc;
785 union mips_instruction insn;
786 struct mm_decoded_insn mminsn;
787 void __user *fault_addr = NULL;
789 origpc = regs->cp0_epc;
790 orig31 = regs->regs[31];
792 mminsn.micro_mips_mode = 1;
795 * This load never faults.
797 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
798 __get_user(halfword, pc16);
800 contpc = regs->cp0_epc + 2;
801 word = ((unsigned int)halfword << 16);
804 if (!mm_insn_16bit(halfword)) {
805 __get_user(halfword, pc16);
807 contpc = regs->cp0_epc + 4;
813 if (get_user(halfword, pc16))
815 mminsn.next_pc_inc = 2;
816 word = ((unsigned int)halfword << 16);
818 if (!mm_insn_16bit(halfword)) {
820 if (get_user(halfword, pc16))
822 mminsn.next_pc_inc = 4;
825 mminsn.next_insn = word;
827 insn = (union mips_instruction)(mminsn.insn);
828 if (mm_isBranchInstr(regs, mminsn, &contpc))
829 insn = (union mips_instruction)(mminsn.next_insn);
831 /* Parse instruction to find what to do */
833 switch (insn.mm_i_format.opcode) {
836 switch (insn.mm_x_format.func) {
838 reg = insn.mm_x_format.rd;
845 switch (insn.mm_m_format.func) {
847 reg = insn.mm_m_format.rd;
851 if (!access_ok(VERIFY_READ, addr, 8))
854 LoadW(addr, value, res);
857 regs->regs[reg] = value;
859 LoadW(addr, value, res);
862 regs->regs[reg + 1] = value;
866 reg = insn.mm_m_format.rd;
870 if (!access_ok(VERIFY_WRITE, addr, 8))
873 value = regs->regs[reg];
874 StoreW(addr, value, res);
878 value = regs->regs[reg + 1];
879 StoreW(addr, value, res);
886 reg = insn.mm_m_format.rd;
890 if (!access_ok(VERIFY_READ, addr, 16))
893 LoadDW(addr, value, res);
896 regs->regs[reg] = value;
898 LoadDW(addr, value, res);
901 regs->regs[reg + 1] = value;
903 #endif /* CONFIG_64BIT */
909 reg = insn.mm_m_format.rd;
913 if (!access_ok(VERIFY_WRITE, addr, 16))
916 value = regs->regs[reg];
917 StoreDW(addr, value, res);
921 value = regs->regs[reg + 1];
922 StoreDW(addr, value, res);
926 #endif /* CONFIG_64BIT */
931 reg = insn.mm_m_format.rd;
933 if ((rvar > 9) || !reg)
937 (VERIFY_READ, addr, 4 * (rvar + 1)))
940 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
945 for (i = 16; rvar; rvar--, i++) {
946 LoadW(addr, value, res);
950 regs->regs[i] = value;
952 if ((reg & 0xf) == 9) {
953 LoadW(addr, value, res);
957 regs->regs[30] = value;
960 LoadW(addr, value, res);
963 regs->regs[31] = value;
968 reg = insn.mm_m_format.rd;
970 if ((rvar > 9) || !reg)
974 (VERIFY_WRITE, addr, 4 * (rvar + 1)))
977 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
982 for (i = 16; rvar; rvar--, i++) {
983 value = regs->regs[i];
984 StoreW(addr, value, res);
989 if ((reg & 0xf) == 9) {
990 value = regs->regs[30];
991 StoreW(addr, value, res);
997 value = regs->regs[31];
998 StoreW(addr, value, res);
1006 reg = insn.mm_m_format.rd;
1008 if ((rvar > 9) || !reg)
1012 (VERIFY_READ, addr, 8 * (rvar + 1)))
1015 if (!access_ok(VERIFY_READ, addr, 8 * rvar))
1021 for (i = 16; rvar; rvar--, i++) {
1022 LoadDW(addr, value, res);
1026 regs->regs[i] = value;
1028 if ((reg & 0xf) == 9) {
1029 LoadDW(addr, value, res);
1033 regs->regs[30] = value;
1036 LoadDW(addr, value, res);
1039 regs->regs[31] = value;
1042 #endif /* CONFIG_64BIT */
1048 reg = insn.mm_m_format.rd;
1050 if ((rvar > 9) || !reg)
1054 (VERIFY_WRITE, addr, 8 * (rvar + 1)))
1057 if (!access_ok(VERIFY_WRITE, addr, 8 * rvar))
1063 for (i = 16; rvar; rvar--, i++) {
1064 value = regs->regs[i];
1065 StoreDW(addr, value, res);
1070 if ((reg & 0xf) == 9) {
1071 value = regs->regs[30];
1072 StoreDW(addr, value, res);
1078 value = regs->regs[31];
1079 StoreDW(addr, value, res);
1084 #endif /* CONFIG_64BIT */
1088 /* LWC2, SWC2, LDC2, SDC2 are not serviced */
1094 switch (insn.mm_m_format.func) {
1096 reg = insn.mm_m_format.rd;
1100 /* LL,SC,LLD,SCD are not serviced */
1104 switch (insn.mm_x_format.func) {
1119 /* roll back jump/branch */
1120 regs->cp0_epc = origpc;
1121 regs->regs[31] = orig31;
1123 die_if_kernel("Unaligned FP access in kernel code", regs);
1124 BUG_ON(!used_math());
1125 BUG_ON(!is_fpu_owner());
1127 lose_fpu(1); /* save the FPU state for the emulator */
1128 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1,
1130 own_fpu(1); /* restore FPU state */
1132 /* If something went wrong, signal */
1133 process_fpemu_return(res, fault_addr);
1140 reg = insn.mm_i_format.rt;
1144 reg = insn.mm_i_format.rt;
1148 reg = insn.mm_i_format.rt;
1152 reg = insn.mm_i_format.rt;
1156 reg = insn.mm_i_format.rt;
1160 reg = insn.mm_i_format.rt;
1164 reg = insn.mm_i_format.rt;
1168 switch (insn.mm16_m_format.func) {
1170 reg = insn.mm16_m_format.rlist;
1172 if (!access_ok(VERIFY_READ, addr, 4 * rvar))
1175 for (i = 16; rvar; rvar--, i++) {
1176 LoadW(addr, value, res);
1180 regs->regs[i] = value;
1182 LoadW(addr, value, res);
1185 regs->regs[31] = value;
1190 reg = insn.mm16_m_format.rlist;
1192 if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
1195 for (i = 16; rvar; rvar--, i++) {
1196 value = regs->regs[i];
1197 StoreW(addr, value, res);
1202 value = regs->regs[31];
1203 StoreW(addr, value, res);
1214 reg = reg16to32[insn.mm16_rb_format.rt];
1218 reg = reg16to32[insn.mm16_rb_format.rt];
1222 reg = reg16to32st[insn.mm16_rb_format.rt];
1226 reg = reg16to32st[insn.mm16_rb_format.rt];
1230 reg = insn.mm16_r5_format.rt;
1234 reg = insn.mm16_r5_format.rt;
1238 reg = reg16to32[insn.mm16_r3_format.rt];
1246 if (!access_ok(VERIFY_READ, addr, 2))
1249 LoadHW(addr, value, res);
1252 regs->regs[reg] = value;
1256 if (!access_ok(VERIFY_READ, addr, 2))
1259 LoadHWU(addr, value, res);
1262 regs->regs[reg] = value;
1266 if (!access_ok(VERIFY_READ, addr, 4))
1269 LoadW(addr, value, res);
1272 regs->regs[reg] = value;
1278 * A 32-bit kernel might be running on a 64-bit processor. But
1279 * if we're on a 32-bit processor and an i-cache incoherency
1280 * or race makes us see a 64-bit instruction here the sdl/sdr
1281 * would blow up, so for now we don't handle unaligned 64-bit
1282 * instructions on 32-bit kernels.
1284 if (!access_ok(VERIFY_READ, addr, 4))
1287 LoadWU(addr, value, res);
1290 regs->regs[reg] = value;
1292 #endif /* CONFIG_64BIT */
1294 /* Cannot handle 64-bit instructions in 32-bit kernel */
1300 * A 32-bit kernel might be running on a 64-bit processor. But
1301 * if we're on a 32-bit processor and an i-cache incoherency
1302 * or race makes us see a 64-bit instruction here the sdl/sdr
1303 * would blow up, so for now we don't handle unaligned 64-bit
1304 * instructions on 32-bit kernels.
1306 if (!access_ok(VERIFY_READ, addr, 8))
1309 LoadDW(addr, value, res);
1312 regs->regs[reg] = value;
1314 #endif /* CONFIG_64BIT */
1316 /* Cannot handle 64-bit instructions in 32-bit kernel */
1320 if (!access_ok(VERIFY_WRITE, addr, 2))
1323 value = regs->regs[reg];
1324 StoreHW(addr, value, res);
1330 if (!access_ok(VERIFY_WRITE, addr, 4))
1333 value = regs->regs[reg];
1334 StoreW(addr, value, res);
1342 * A 32-bit kernel might be running on a 64-bit processor. But
1343 * if we're on a 32-bit processor and an i-cache incoherency
1344 * or race makes us see a 64-bit instruction here the sdl/sdr
1345 * would blow up, so for now we don't handle unaligned 64-bit
1346 * instructions on 32-bit kernels.
1348 if (!access_ok(VERIFY_WRITE, addr, 8))
1351 value = regs->regs[reg];
1352 StoreDW(addr, value, res);
1356 #endif /* CONFIG_64BIT */
1358 /* Cannot handle 64-bit instructions in 32-bit kernel */
1362 regs->cp0_epc = contpc; /* advance or branch */
1364 #ifdef CONFIG_DEBUG_FS
1365 unaligned_instructions++;
1370 /* roll back jump/branch */
1371 regs->cp0_epc = origpc;
1372 regs->regs[31] = orig31;
1373 /* Did we have an exception handler installed? */
1374 if (fixup_exception(regs))
1377 die_if_kernel("Unhandled kernel unaligned access", regs);
1378 force_sig(SIGSEGV, current);
1383 die_if_kernel("Unhandled kernel unaligned access", regs);
1384 force_sig(SIGBUS, current);
1390 ("Unhandled kernel unaligned access or invalid instruction", regs);
1391 force_sig(SIGILL, current);
1394 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
1396 unsigned long value;
1399 unsigned long orig31;
1401 unsigned long origpc;
1402 union mips16e_instruction mips16inst, oldinst;
1404 origpc = regs->cp0_epc;
1405 orig31 = regs->regs[31];
1406 pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
1408 * This load never faults.
1410 __get_user(mips16inst.full, pc16);
1411 oldinst = mips16inst;
1413 /* skip EXTEND instruction */
1414 if (mips16inst.ri.opcode == MIPS16e_extend_op) {
1416 __get_user(mips16inst.full, pc16);
1417 } else if (delay_slot(regs)) {
1418 /* skip jump instructions */
1419 /* JAL/JALX are 32 bits but have OPCODE in first short int */
1420 if (mips16inst.ri.opcode == MIPS16e_jal_op)
1423 if (get_user(mips16inst.full, pc16))
1427 switch (mips16inst.ri.opcode) {
1428 case MIPS16e_i64_op: /* I64 or RI64 instruction */
1429 switch (mips16inst.i64.func) { /* I64/RI64 func field check */
1430 case MIPS16e_ldpc_func:
1431 case MIPS16e_ldsp_func:
1432 reg = reg16to32[mips16inst.ri64.ry];
1435 case MIPS16e_sdsp_func:
1436 reg = reg16to32[mips16inst.ri64.ry];
1439 case MIPS16e_sdrasp_func:
1440 reg = 29; /* GPRSP */
1446 case MIPS16e_swsp_op:
1447 case MIPS16e_lwpc_op:
1448 case MIPS16e_lwsp_op:
1449 reg = reg16to32[mips16inst.ri.rx];
1453 if (mips16inst.i8.func != MIPS16e_swrasp_func)
1455 reg = 29; /* GPRSP */
1459 reg = reg16to32[mips16inst.rri.ry];
1463 switch (mips16inst.ri.opcode) {
1466 case MIPS16e_lbu_op:
1471 if (!access_ok(VERIFY_READ, addr, 2))
1474 LoadHW(addr, value, res);
1477 MIPS16e_compute_return_epc(regs, &oldinst);
1478 regs->regs[reg] = value;
1481 case MIPS16e_lhu_op:
1482 if (!access_ok(VERIFY_READ, addr, 2))
1485 LoadHWU(addr, value, res);
1488 MIPS16e_compute_return_epc(regs, &oldinst);
1489 regs->regs[reg] = value;
1493 case MIPS16e_lwpc_op:
1494 case MIPS16e_lwsp_op:
1495 if (!access_ok(VERIFY_READ, addr, 4))
1498 LoadW(addr, value, res);
1501 MIPS16e_compute_return_epc(regs, &oldinst);
1502 regs->regs[reg] = value;
1505 case MIPS16e_lwu_op:
1508 * A 32-bit kernel might be running on a 64-bit processor. But
1509 * if we're on a 32-bit processor and an i-cache incoherency
1510 * or race makes us see a 64-bit instruction here the sdl/sdr
1511 * would blow up, so for now we don't handle unaligned 64-bit
1512 * instructions on 32-bit kernels.
1514 if (!access_ok(VERIFY_READ, addr, 4))
1517 LoadWU(addr, value, res);
1520 MIPS16e_compute_return_epc(regs, &oldinst);
1521 regs->regs[reg] = value;
1523 #endif /* CONFIG_64BIT */
1525 /* Cannot handle 64-bit instructions in 32-bit kernel */
1532 * A 32-bit kernel might be running on a 64-bit processor. But
1533 * if we're on a 32-bit processor and an i-cache incoherency
1534 * or race makes us see a 64-bit instruction here the sdl/sdr
1535 * would blow up, so for now we don't handle unaligned 64-bit
1536 * instructions on 32-bit kernels.
1538 if (!access_ok(VERIFY_READ, addr, 8))
1541 LoadDW(addr, value, res);
1544 MIPS16e_compute_return_epc(regs, &oldinst);
1545 regs->regs[reg] = value;
1547 #endif /* CONFIG_64BIT */
1549 /* Cannot handle 64-bit instructions in 32-bit kernel */
1553 if (!access_ok(VERIFY_WRITE, addr, 2))
1556 MIPS16e_compute_return_epc(regs, &oldinst);
1557 value = regs->regs[reg];
1558 StoreHW(addr, value, res);
1564 case MIPS16e_swsp_op:
1565 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
1566 if (!access_ok(VERIFY_WRITE, addr, 4))
1569 MIPS16e_compute_return_epc(regs, &oldinst);
1570 value = regs->regs[reg];
1571 StoreW(addr, value, res);
1580 * A 32-bit kernel might be running on a 64-bit processor. But
1581 * if we're on a 32-bit processor and an i-cache incoherency
1582 * or race makes us see a 64-bit instruction here the sdl/sdr
1583 * would blow up, so for now we don't handle unaligned 64-bit
1584 * instructions on 32-bit kernels.
1586 if (!access_ok(VERIFY_WRITE, addr, 8))
1589 MIPS16e_compute_return_epc(regs, &oldinst);
1590 value = regs->regs[reg];
1591 StoreDW(addr, value, res);
1595 #endif /* CONFIG_64BIT */
1597 /* Cannot handle 64-bit instructions in 32-bit kernel */
1602 * Pheeee... We encountered an yet unknown instruction or
1603 * cache coherence problem. Die sucker, die ...
1608 #ifdef CONFIG_DEBUG_FS
1609 unaligned_instructions++;
1615 /* roll back jump/branch */
1616 regs->cp0_epc = origpc;
1617 regs->regs[31] = orig31;
1618 /* Did we have an exception handler installed? */
1619 if (fixup_exception(regs))
1622 die_if_kernel("Unhandled kernel unaligned access", regs);
1623 force_sig(SIGSEGV, current);
1628 die_if_kernel("Unhandled kernel unaligned access", regs);
1629 force_sig(SIGBUS, current);
1635 ("Unhandled kernel unaligned access or invalid instruction", regs);
1636 force_sig(SIGILL, current);
1639 asmlinkage void do_ade(struct pt_regs *regs)
1641 enum ctx_state prev_state;
1642 unsigned int __user *pc;
1645 prev_state = exception_enter();
1646 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
1647 1, regs, regs->cp0_badvaddr);
1649 * Did we catch a fault trying to load an instruction?
1651 if (regs->cp0_badvaddr == regs->cp0_epc)
1654 if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
1656 if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
1660 * Do branch emulation only if we didn't forward the exception.
1661 * This is all so but ugly ...
1665 * Are we running in microMIPS mode?
1667 if (get_isa16_mode(regs->cp0_epc)) {
1669 * Did we catch a fault trying to load an instruction in
1672 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
1674 if (unaligned_action == UNALIGNED_ACTION_SHOW)
1675 show_registers(regs);
1677 if (cpu_has_mmips) {
1679 if (!user_mode(regs))
1681 emulate_load_store_microMIPS(regs,
1682 (void __user *)regs->cp0_badvaddr);
1688 if (cpu_has_mips16) {
1690 if (!user_mode(regs))
1692 emulate_load_store_MIPS16e(regs,
1693 (void __user *)regs->cp0_badvaddr);
1702 if (unaligned_action == UNALIGNED_ACTION_SHOW)
1703 show_registers(regs);
1704 pc = (unsigned int __user *)exception_epc(regs);
1707 if (!user_mode(regs))
1709 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
1715 die_if_kernel("Kernel unaligned instruction access", regs);
1716 force_sig(SIGBUS, current);
1719 * XXX On return from the signal handler we should advance the epc
1721 exception_exit(prev_state);
1724 #ifdef CONFIG_DEBUG_FS
1725 extern struct dentry *mips_debugfs_dir;
1726 static int __init debugfs_unaligned(void)
1730 if (!mips_debugfs_dir)
1732 d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
1733 mips_debugfs_dir, &unaligned_instructions);
1736 d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
1737 mips_debugfs_dir, &unaligned_action);
1742 __initcall(debugfs_unaligned);