2 * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
3 * Author: Chen Huacai, chenhc@lemote.com
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/init.h>
18 #include <linux/cpu.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/cpufreq.h>
22 #include <asm/processor.h>
24 #include <asm/clock.h>
25 #include <asm/tlbflush.h>
26 #include <asm/cacheflush.h>
31 DEFINE_PER_CPU(int, cpu_state);
32 DEFINE_PER_CPU(uint32_t, core0_c0count);
34 /* read a 32bit value from ipi register */
35 #define loongson3_ipi_read32(addr) readl(addr)
36 /* read a 64bit value from ipi register */
37 #define loongson3_ipi_read64(addr) readq(addr)
38 /* write a 32bit value to ipi register */
39 #define loongson3_ipi_write32(action, addr) \
41 writel(action, addr); \
44 /* write a 64bit value to ipi register */
45 #define loongson3_ipi_write64(action, addr) \
47 writeq(action, addr); \
51 static void *ipi_set0_regs[] = {
52 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0),
53 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0),
54 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0),
55 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0),
56 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0),
57 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0),
58 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0),
59 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0),
60 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0),
61 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0),
62 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0),
63 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0),
64 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0),
65 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0),
66 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0),
67 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0),
70 static void *ipi_clear0_regs[] = {
71 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0),
72 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0),
73 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0),
74 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0),
75 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0),
76 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0),
77 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0),
78 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0),
79 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0),
80 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0),
81 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0),
82 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0),
83 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0),
84 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0),
85 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0),
86 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0),
89 static void *ipi_status0_regs[] = {
90 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0),
91 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0),
92 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0),
93 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0),
94 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0),
95 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0),
96 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0),
97 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0),
98 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0),
99 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0),
100 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0),
101 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0),
102 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0),
103 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0),
104 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0),
105 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0),
108 static void *ipi_en0_regs[] = {
109 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0),
110 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0),
111 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0),
112 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0),
113 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0),
114 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0),
115 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0),
116 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0),
117 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0),
118 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0),
119 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0),
120 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0),
121 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0),
122 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0),
123 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0),
124 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0),
127 static void *ipi_mailbox_buf[] = {
128 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF),
129 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF),
130 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF),
131 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF),
132 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF),
133 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF),
134 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF),
135 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF),
136 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF),
137 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF),
138 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF),
139 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF),
140 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF),
141 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF),
142 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF),
143 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF),
147 * Simple enough, just poke the appropriate ipi register
149 static void loongson3_send_ipi_single(int cpu, unsigned int action)
151 loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
155 loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
159 for_each_cpu(i, mask)
160 loongson3_ipi_write32((u32)action, ipi_set0_regs[i]);
163 void loongson3_ipi_interrupt(struct pt_regs *regs)
165 int i, cpu = smp_processor_id();
166 unsigned int action, c0count;
168 /* Load the ipi register to figure out what we're supposed to do */
169 action = loongson3_ipi_read32(ipi_status0_regs[cpu]);
171 /* Clear the ipi register to clear the interrupt */
172 loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu]);
174 if (action & SMP_RESCHEDULE_YOURSELF)
177 if (action & SMP_CALL_FUNCTION)
178 smp_call_function_interrupt();
180 if (action & SMP_ASK_C0COUNT) {
182 c0count = read_c0_count();
183 for (i = 1; i < loongson_sysconf.nr_cpus; i++)
184 per_cpu(core0_c0count, i) = c0count;
188 #define MAX_LOOPS 1111
190 * SMP init and finish on secondary CPUs
192 static void loongson3_init_secondary(void)
196 unsigned int cpu = smp_processor_id();
197 unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
198 STATUSF_IP3 | STATUSF_IP2;
200 /* Set interrupt mask, but don't enable */
201 change_c0_status(ST0_IM, imask);
203 for (i = 0; i < loongson_sysconf.nr_cpus; i++)
204 loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]);
206 per_cpu(cpu_state, cpu) = CPU_ONLINE;
209 __get_cpu_var(core0_c0count) = 0;
210 loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
211 while (!__get_cpu_var(core0_c0count)) {
218 initcount = __get_cpu_var(core0_c0count) + i;
219 write_c0_count(initcount);
222 static void loongson3_smp_finish(void)
224 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
226 loongson3_ipi_write64(0,
227 (void *)(ipi_mailbox_buf[smp_processor_id()]+0x0));
228 pr_info("CPU#%d finished, CP0_ST=%x\n",
229 smp_processor_id(), read_c0_status());
232 static void __init loongson3_smp_setup(void)
236 init_cpu_possible(cpu_none_mask);
237 set_cpu_possible(0, true);
239 __cpu_number_map[0] = 0;
240 __cpu_logical_map[0] = 0;
242 /* For unified kernel, NR_CPUS is the maximum possible value,
243 * loongson_sysconf.nr_cpus is the really present value */
244 for (i = 1, num = 0; i < loongson_sysconf.nr_cpus; i++) {
245 set_cpu_possible(i, true);
246 __cpu_number_map[i] = ++num;
247 __cpu_logical_map[num] = i;
249 pr_info("Detected %i available secondary CPU(s)\n", num);
252 static void __init loongson3_prepare_cpus(unsigned int max_cpus)
254 init_cpu_present(cpu_possible_mask);
255 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
259 * Setup the PC, SP, and GP of a secondary processor and start it runing!
261 static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
263 unsigned long startargs[4];
265 pr_info("Booting CPU#%d...\n", cpu);
267 /* startargs[] are initial PC, SP and GP for secondary CPU */
268 startargs[0] = (unsigned long)&smp_bootstrap;
269 startargs[1] = (unsigned long)__KSTK_TOS(idle);
270 startargs[2] = (unsigned long)task_thread_info(idle);
273 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
274 cpu, startargs[0], startargs[1], startargs[2]);
276 loongson3_ipi_write64(startargs[3], (void *)(ipi_mailbox_buf[cpu]+0x18));
277 loongson3_ipi_write64(startargs[2], (void *)(ipi_mailbox_buf[cpu]+0x10));
278 loongson3_ipi_write64(startargs[1], (void *)(ipi_mailbox_buf[cpu]+0x8));
279 loongson3_ipi_write64(startargs[0], (void *)(ipi_mailbox_buf[cpu]+0x0));
282 #ifdef CONFIG_HOTPLUG_CPU
284 static int loongson3_cpu_disable(void)
287 unsigned int cpu = smp_processor_id();
292 set_cpu_online(cpu, false);
293 cpu_clear(cpu, cpu_callin_map);
294 local_irq_save(flags);
296 local_irq_restore(flags);
298 local_flush_tlb_all();
304 static void loongson3_cpu_die(unsigned int cpu)
306 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
312 /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
313 * flush all L1 entries at first. Then, another core (usually Core 0) can
314 * safely disable the clock of the target core. loongson3_play_dead() is
315 * called via CKSEG1 (uncached and unmmaped) */
316 static void loongson3_play_dead(int *state_addr)
319 register long cpuid, core, node, count;
320 register void *addr, *base, *initfunc;
322 __asm__ __volatile__(
325 " li %[addr], 0x80000000 \n" /* KSEG0 */
326 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
327 " cache 0, 1(%[addr]) \n"
328 " cache 0, 2(%[addr]) \n"
329 " cache 0, 3(%[addr]) \n"
330 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
331 " cache 1, 1(%[addr]) \n"
332 " cache 1, 2(%[addr]) \n"
333 " cache 1, 3(%[addr]) \n"
334 " addiu %[sets], %[sets], -1 \n"
335 " bnez %[sets], 1b \n"
336 " addiu %[addr], %[addr], 0x20 \n"
337 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
338 " sw %[val], (%[state_addr]) \n"
340 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
342 : [addr] "=&r" (addr), [val] "=&r" (val)
343 : [state_addr] "r" (state_addr),
344 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
346 __asm__ __volatile__(
350 " mfc0 %[cpuid], $15, 1 \n"
351 " andi %[cpuid], 0x3ff \n"
352 " dli %[base], 0x900000003ff01000 \n"
353 " andi %[core], %[cpuid], 0x3 \n"
354 " sll %[core], 8 \n" /* get core id */
355 " or %[base], %[base], %[core] \n"
356 " andi %[node], %[cpuid], 0xc \n"
357 " dsll %[node], 42 \n" /* get node id */
358 " or %[base], %[base], %[node] \n"
359 "1: li %[count], 0x100 \n" /* wait for init loop */
360 "2: bnez %[count], 2b \n" /* limit mailbox access */
361 " addiu %[count], -1 \n"
362 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
363 " beqz %[initfunc], 1b \n"
365 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
366 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
367 " ld $a1, 0x38(%[base]) \n"
368 " jr %[initfunc] \n" /* jump to initial PC */
371 : [core] "=&r" (core), [node] "=&r" (node),
372 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
373 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
381 unsigned int cpu = smp_processor_id();
382 void (*play_dead_at_ckseg1)(int *);
385 play_dead_at_ckseg1 =
386 (void *)CKSEG1ADDR((unsigned long)loongson3_play_dead);
387 state_addr = &per_cpu(cpu_state, cpu);
389 play_dead_at_ckseg1(state_addr);
392 #define CPU_POST_DEAD_FROZEN (CPU_POST_DEAD | CPU_TASKS_FROZEN)
393 static int loongson3_cpu_callback(struct notifier_block *nfb,
394 unsigned long action, void *hcpu)
396 unsigned int cpu = (unsigned long)hcpu;
400 case CPU_POST_DEAD_FROZEN:
401 pr_info("Disable clock for CPU#%d\n", cpu);
402 LOONGSON_CHIPCFG0 &= ~(1 << (12 + cpu));
405 case CPU_UP_PREPARE_FROZEN:
406 pr_info("Enable clock for CPU#%d\n", cpu);
407 LOONGSON_CHIPCFG0 |= 1 << (12 + cpu);
414 static int register_loongson3_notifier(void)
416 hotcpu_notifier(loongson3_cpu_callback, 0);
419 early_initcall(register_loongson3_notifier);
423 struct plat_smp_ops loongson3_smp_ops = {
424 .send_ipi_single = loongson3_send_ipi_single,
425 .send_ipi_mask = loongson3_send_ipi_mask,
426 .init_secondary = loongson3_init_secondary,
427 .smp_finish = loongson3_smp_finish,
428 .boot_secondary = loongson3_boot_secondary,
429 .smp_setup = loongson3_smp_setup,
430 .prepare_cpus = loongson3_prepare_cpus,
431 #ifdef CONFIG_HOTPLUG_CPU
432 .cpu_disable = loongson3_cpu_disable,
433 .cpu_die = loongson3_cpu_die,