2 * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
3 * Author: Chen Huacai, chenhc@lemote.com
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/init.h>
18 #include <linux/cpu.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/cpufreq.h>
22 #include <asm/processor.h>
24 #include <asm/clock.h>
25 #include <asm/tlbflush.h>
30 /* read a 32bit value from ipi register */
31 #define loongson3_ipi_read32(addr) readl(addr)
32 /* read a 64bit value from ipi register */
33 #define loongson3_ipi_read64(addr) readq(addr)
34 /* write a 32bit value to ipi register */
35 #define loongson3_ipi_write32(action, addr) \
37 writel(action, addr); \
40 /* write a 64bit value to ipi register */
41 #define loongson3_ipi_write64(action, addr) \
43 writeq(action, addr); \
47 static void *ipi_set0_regs[] = {
48 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0),
49 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0),
50 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0),
51 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0),
52 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0),
53 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0),
54 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0),
55 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0),
56 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0),
57 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0),
58 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0),
59 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0),
60 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0),
61 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0),
62 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0),
63 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0),
66 static void *ipi_clear0_regs[] = {
67 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0),
68 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0),
69 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0),
70 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0),
71 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0),
72 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0),
73 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0),
74 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0),
75 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0),
76 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0),
77 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0),
78 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0),
79 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0),
80 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0),
81 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0),
82 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0),
85 static void *ipi_status0_regs[] = {
86 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0),
87 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0),
88 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0),
89 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0),
90 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0),
91 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0),
92 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0),
93 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0),
94 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0),
95 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0),
96 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0),
97 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0),
98 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0),
99 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0),
100 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0),
101 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0),
104 static void *ipi_en0_regs[] = {
105 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0),
106 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0),
107 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0),
108 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0),
109 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0),
110 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0),
111 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0),
112 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0),
113 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0),
114 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0),
115 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0),
116 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0),
117 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0),
118 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0),
119 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0),
120 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0),
123 static void *ipi_mailbox_buf[] = {
124 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF),
125 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF),
126 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF),
127 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF),
128 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF),
129 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF),
130 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF),
131 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF),
132 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF),
133 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF),
134 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF),
135 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF),
136 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF),
137 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF),
138 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF),
139 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF),
143 * Simple enough, just poke the appropriate ipi register
145 static void loongson3_send_ipi_single(int cpu, unsigned int action)
147 loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
151 loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
155 for_each_cpu(i, mask)
156 loongson3_ipi_write32((u32)action, ipi_set0_regs[i]);
159 void loongson3_ipi_interrupt(struct pt_regs *regs)
161 int cpu = smp_processor_id();
164 /* Load the ipi register to figure out what we're supposed to do */
165 action = loongson3_ipi_read32(ipi_status0_regs[cpu]);
167 /* Clear the ipi register to clear the interrupt */
168 loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu]);
170 if (action & SMP_RESCHEDULE_YOURSELF)
173 if (action & SMP_CALL_FUNCTION)
174 smp_call_function_interrupt();
178 * SMP init and finish on secondary CPUs
180 static void loongson3_init_secondary(void)
183 unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
184 STATUSF_IP3 | STATUSF_IP2;
186 /* Set interrupt mask, but don't enable */
187 change_c0_status(ST0_IM, imask);
189 for (i = 0; i < loongson_sysconf.nr_cpus; i++)
190 loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]);
193 static void loongson3_smp_finish(void)
195 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
197 loongson3_ipi_write64(0,
198 (void *)(ipi_mailbox_buf[smp_processor_id()]+0x0));
199 pr_info("CPU#%d finished, CP0_ST=%x\n",
200 smp_processor_id(), read_c0_status());
203 static void __init loongson3_smp_setup(void)
207 init_cpu_possible(cpu_none_mask);
208 set_cpu_possible(0, true);
210 __cpu_number_map[0] = 0;
211 __cpu_logical_map[0] = 0;
213 /* For unified kernel, NR_CPUS is the maximum possible value,
214 * loongson_sysconf.nr_cpus is the really present value */
215 for (i = 1, num = 0; i < loongson_sysconf.nr_cpus; i++) {
216 set_cpu_possible(i, true);
217 __cpu_number_map[i] = ++num;
218 __cpu_logical_map[num] = i;
220 pr_info("Detected %i available secondary CPU(s)\n", num);
223 static void __init loongson3_prepare_cpus(unsigned int max_cpus)
228 * Setup the PC, SP, and GP of a secondary processor and start it runing!
230 static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
232 unsigned long startargs[4];
234 pr_info("Booting CPU#%d...\n", cpu);
236 /* startargs[] are initial PC, SP and GP for secondary CPU */
237 startargs[0] = (unsigned long)&smp_bootstrap;
238 startargs[1] = (unsigned long)__KSTK_TOS(idle);
239 startargs[2] = (unsigned long)task_thread_info(idle);
242 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
243 cpu, startargs[0], startargs[1], startargs[2]);
245 loongson3_ipi_write64(startargs[3], (void *)(ipi_mailbox_buf[cpu]+0x18));
246 loongson3_ipi_write64(startargs[2], (void *)(ipi_mailbox_buf[cpu]+0x10));
247 loongson3_ipi_write64(startargs[1], (void *)(ipi_mailbox_buf[cpu]+0x8));
248 loongson3_ipi_write64(startargs[0], (void *)(ipi_mailbox_buf[cpu]+0x0));
252 * Final cleanup after all secondaries booted
254 static void __init loongson3_cpus_done(void)
258 struct plat_smp_ops loongson3_smp_ops = {
259 .send_ipi_single = loongson3_send_ipi_single,
260 .send_ipi_mask = loongson3_send_ipi_mask,
261 .init_secondary = loongson3_init_secondary,
262 .smp_finish = loongson3_smp_finish,
263 .cpus_done = loongson3_cpus_done,
264 .boot_secondary = loongson3_boot_secondary,
265 .smp_setup = loongson3_smp_setup,
266 .prepare_cpus = loongson3_prepare_cpus,