arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/kconfig.h>
  39 #include <linux/percpu-defs.h>
  40 #include <linux/perf_event.h>
  41
  42 #include <asm/branch.h>
  43 #include <asm/inst.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/uaccess.h>
  47
  48 #include <asm/processor.h>
  49 #include <asm/fpu_emulator.h>
  50 #include <asm/fpu.h>
  51
  52 #include "ieee754.h"
  53
  54 /* Function which emulates a floating point instruction. */
  55
  56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  57         mips_instruction);
  58
  59 static int fpux_emu(struct pt_regs *,
  60         struct mips_fpu_struct *, mips_instruction, void *__user *);
  61
  62 /* Control registers */
  63
  64 #define FPCREG_RID      0       /* $0  = revision id */
  65 #define FPCREG_CSR      31      /* $31 = csr */
  66
  67 /* Determine rounding mode from the RM bits of the FCSR */
  68 #define modeindex(v) ((v) & FPU_CSR_RM)
  69
  70 /* convert condition code register number to csr bit */
  71 static const unsigned int fpucondbit[8] = {
  72         FPU_CSR_COND0,
  73         FPU_CSR_COND1,
  74         FPU_CSR_COND2,
  75         FPU_CSR_COND3,
  76         FPU_CSR_COND4,
  77         FPU_CSR_COND5,
  78         FPU_CSR_COND6,
  79         FPU_CSR_COND7
  80 };
  81
  82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  87
  88 /*
  89  * This functions translates a 32-bit microMIPS instruction
  90  * into a 32-bit MIPS32 instruction. Returns 0 on success
  91  * and SIGILL otherwise.
  92  */
  93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  94 {
  95         union mips_instruction insn = *insn_ptr;
  96         union mips_instruction mips32_insn = insn;
  97         int func, fmt, op;
  98
  99         switch (insn.mm_i_format.opcode) {
 100         case mm_ldc132_op:
 101                 mips32_insn.mm_i_format.opcode = ldc1_op;
 102                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 103                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 104                 break;
 105         case mm_lwc132_op:
 106                 mips32_insn.mm_i_format.opcode = lwc1_op;
 107                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 108                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 109                 break;
 110         case mm_sdc132_op:
 111                 mips32_insn.mm_i_format.opcode = sdc1_op;
 112                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 113                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 114                 break;
 115         case mm_swc132_op:
 116                 mips32_insn.mm_i_format.opcode = swc1_op;
 117                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 118                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 119                 break;
 120         case mm_pool32i_op:
 121                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 122                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 123                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 124                         mips32_insn.fb_format.opcode = cop1_op;
 125                         mips32_insn.fb_format.bc = bc_op;
 126                         mips32_insn.fb_format.flag =
 127                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 128                 } else
 129                         return SIGILL;
 130                 break;
 131         case mm_pool32f_op:
 132                 switch (insn.mm_fp0_format.func) {
 133                 case mm_32f_01_op:
 134                 case mm_32f_11_op:
 135                 case mm_32f_02_op:
 136                 case mm_32f_12_op:
 137                 case mm_32f_41_op:
 138                 case mm_32f_51_op:
 139                 case mm_32f_42_op:
 140                 case mm_32f_52_op:
 141                         op = insn.mm_fp0_format.func;
 142                         if (op == mm_32f_01_op)
 143                                 func = madd_s_op;
 144                         else if (op == mm_32f_11_op)
 145                                 func = madd_d_op;
 146                         else if (op == mm_32f_02_op)
 147                                 func = nmadd_s_op;
 148                         else if (op == mm_32f_12_op)
 149                                 func = nmadd_d_op;
 150                         else if (op == mm_32f_41_op)
 151                                 func = msub_s_op;
 152                         else if (op == mm_32f_51_op)
 153                                 func = msub_d_op;
 154                         else if (op == mm_32f_42_op)
 155                                 func = nmsub_s_op;
 156                         else
 157                                 func = nmsub_d_op;
 158                         mips32_insn.fp6_format.opcode = cop1x_op;
 159                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 160                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 161                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 162                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 163                         mips32_insn.fp6_format.func = func;
 164                         break;
 165                 case mm_32f_10_op:
 166                         func = -1;      /* Invalid */
 167                         op = insn.mm_fp5_format.op & 0x7;
 168                         if (op == mm_ldxc1_op)
 169                                 func = ldxc1_op;
 170                         else if (op == mm_sdxc1_op)
 171                                 func = sdxc1_op;
 172                         else if (op == mm_lwxc1_op)
 173                                 func = lwxc1_op;
 174                         else if (op == mm_swxc1_op)
 175                                 func = swxc1_op;
 176
 177                         if (func != -1) {
 178                                 mips32_insn.r_format.opcode = cop1x_op;
 179                                 mips32_insn.r_format.rs =
 180                                         insn.mm_fp5_format.base;
 181                                 mips32_insn.r_format.rt =
 182                                         insn.mm_fp5_format.index;
 183                                 mips32_insn.r_format.rd = 0;
 184                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 185                                 mips32_insn.r_format.func = func;
 186                         } else
 187                                 return SIGILL;
 188                         break;
 189                 case mm_32f_40_op:
 190                         op = -1;        /* Invalid */
 191                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 192                                 op = 1;
 193                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 194                                 op = 0;
 195                         if (op != -1) {
 196                                 mips32_insn.fp0_format.opcode = cop1_op;
 197                                 mips32_insn.fp0_format.fmt =
 198                                         sdps_format[insn.mm_fp2_format.fmt];
 199                                 mips32_insn.fp0_format.ft =
 200                                         (insn.mm_fp2_format.cc<<2) + op;
 201                                 mips32_insn.fp0_format.fs =
 202                                         insn.mm_fp2_format.fs;
 203                                 mips32_insn.fp0_format.fd =
 204                                         insn.mm_fp2_format.fd;
 205                                 mips32_insn.fp0_format.func = fmovc_op;
 206                         } else
 207                                 return SIGILL;
 208                         break;
 209                 case mm_32f_60_op:
 210                         func = -1;      /* Invalid */
 211                         if (insn.mm_fp0_format.op == mm_fadd_op)
 212                                 func = fadd_op;
 213                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 214                                 func = fsub_op;
 215                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 216                                 func = fmul_op;
 217                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 218                                 func = fdiv_op;
 219                         if (func != -1) {
 220                                 mips32_insn.fp0_format.opcode = cop1_op;
 221                                 mips32_insn.fp0_format.fmt =
 222                                         sdps_format[insn.mm_fp0_format.fmt];
 223                                 mips32_insn.fp0_format.ft =
 224                                         insn.mm_fp0_format.ft;
 225                                 mips32_insn.fp0_format.fs =
 226                                         insn.mm_fp0_format.fs;
 227                                 mips32_insn.fp0_format.fd =
 228                                         insn.mm_fp0_format.fd;
 229                                 mips32_insn.fp0_format.func = func;
 230                         } else
 231                                 return SIGILL;
 232                         break;
 233                 case mm_32f_70_op:
 234                         func = -1;      /* Invalid */
 235                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 236                                 func = fmovn_op;
 237                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 238                                 func = fmovz_op;
 239                         if (func != -1) {
 240                                 mips32_insn.fp0_format.opcode = cop1_op;
 241                                 mips32_insn.fp0_format.fmt =
 242                                         sdps_format[insn.mm_fp0_format.fmt];
 243                                 mips32_insn.fp0_format.ft =
 244                                         insn.mm_fp0_format.ft;
 245                                 mips32_insn.fp0_format.fs =
 246                                         insn.mm_fp0_format.fs;
 247                                 mips32_insn.fp0_format.fd =
 248                                         insn.mm_fp0_format.fd;
 249                                 mips32_insn.fp0_format.func = func;
 250                         } else
 251                                 return SIGILL;
 252                         break;
 253                 case mm_32f_73_op:    /* POOL32FXF */
 254                         switch (insn.mm_fp1_format.op) {
 255                         case mm_movf0_op:
 256                         case mm_movf1_op:
 257                         case mm_movt0_op:
 258                         case mm_movt1_op:
 259                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 260                                     mm_movf0_op)
 261                                         op = 0;
 262                                 else
 263                                         op = 1;
 264                                 mips32_insn.r_format.opcode = spec_op;
 265                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 266                                 mips32_insn.r_format.rt =
 267                                         (insn.mm_fp4_format.cc << 2) + op;
 268                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 269                                 mips32_insn.r_format.re = 0;
 270                                 mips32_insn.r_format.func = movc_op;
 271                                 break;
 272                         case mm_fcvtd0_op:
 273                         case mm_fcvtd1_op:
 274                         case mm_fcvts0_op:
 275                         case mm_fcvts1_op:
 276                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 277                                     mm_fcvtd0_op) {
 278                                         func = fcvtd_op;
 279                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 280                                 } else {
 281                                         func = fcvts_op;
 282                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 283                                 }
 284                                 mips32_insn.fp0_format.opcode = cop1_op;
 285                                 mips32_insn.fp0_format.fmt = fmt;
 286                                 mips32_insn.fp0_format.ft = 0;
 287                                 mips32_insn.fp0_format.fs =
 288                                         insn.mm_fp3_format.fs;
 289                                 mips32_insn.fp0_format.fd =
 290                                         insn.mm_fp3_format.rt;
 291                                 mips32_insn.fp0_format.func = func;
 292                                 break;
 293                         case mm_fmov0_op:
 294                         case mm_fmov1_op:
 295                         case mm_fabs0_op:
 296                         case mm_fabs1_op:
 297                         case mm_fneg0_op:
 298                         case mm_fneg1_op:
 299                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 300                                     mm_fmov0_op)
 301                                         func = fmov_op;
 302                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 303                                          mm_fabs0_op)
 304                                         func = fabs_op;
 305                                 else
 306                                         func = fneg_op;
 307                                 mips32_insn.fp0_format.opcode = cop1_op;
 308                                 mips32_insn.fp0_format.fmt =
 309                                         sdps_format[insn.mm_fp3_format.fmt];
 310                                 mips32_insn.fp0_format.ft = 0;
 311                                 mips32_insn.fp0_format.fs =
 312                                         insn.mm_fp3_format.fs;
 313                                 mips32_insn.fp0_format.fd =
 314                                         insn.mm_fp3_format.rt;
 315                                 mips32_insn.fp0_format.func = func;
 316                                 break;
 317                         case mm_ffloorl_op:
 318                         case mm_ffloorw_op:
 319                         case mm_fceill_op:
 320                         case mm_fceilw_op:
 321                         case mm_ftruncl_op:
 322                         case mm_ftruncw_op:
 323                         case mm_froundl_op:
 324                         case mm_froundw_op:
 325                         case mm_fcvtl_op:
 326                         case mm_fcvtw_op:
 327                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 328                                         func = ffloorl_op;
 329                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 330                                         func = ffloor_op;
 331                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 332                                         func = fceill_op;
 333                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 334                                         func = fceil_op;
 335                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 336                                         func = ftruncl_op;
 337                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 338                                         func = ftrunc_op;
 339                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 340                                         func = froundl_op;
 341                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 342                                         func = fround_op;
 343                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 344                                         func = fcvtl_op;
 345                                 else
 346                                         func = fcvtw_op;
 347                                 mips32_insn.fp0_format.opcode = cop1_op;
 348                                 mips32_insn.fp0_format.fmt =
 349                                         sd_format[insn.mm_fp1_format.fmt];
 350                                 mips32_insn.fp0_format.ft = 0;
 351                                 mips32_insn.fp0_format.fs =
 352                                         insn.mm_fp1_format.fs;
 353                                 mips32_insn.fp0_format.fd =
 354                                         insn.mm_fp1_format.rt;
 355                                 mips32_insn.fp0_format.func = func;
 356                                 break;
 357                         case mm_frsqrt_op:
 358                         case mm_fsqrt_op:
 359                         case mm_frecip_op:
 360                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 361                                         func = frsqrt_op;
 362                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 363                                         func = fsqrt_op;
 364                                 else
 365                                         func = frecip_op;
 366                                 mips32_insn.fp0_format.opcode = cop1_op;
 367                                 mips32_insn.fp0_format.fmt =
 368                                         sdps_format[insn.mm_fp1_format.fmt];
 369                                 mips32_insn.fp0_format.ft = 0;
 370                                 mips32_insn.fp0_format.fs =
 371                                         insn.mm_fp1_format.fs;
 372                                 mips32_insn.fp0_format.fd =
 373                                         insn.mm_fp1_format.rt;
 374                                 mips32_insn.fp0_format.func = func;
 375                                 break;
 376                         case mm_mfc1_op:
 377                         case mm_mtc1_op:
 378                         case mm_cfc1_op:
 379                         case mm_ctc1_op:
 380                         case mm_mfhc1_op:
 381                         case mm_mthc1_op:
 382                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 383                                         op = mfc_op;
 384                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 385                                         op = mtc_op;
 386                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 387                                         op = cfc_op;
 388                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 389                                         op = ctc_op;
 390                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 391                                         op = mfhc_op;
 392                                 else
 393                                         op = mthc_op;
 394                                 mips32_insn.fp1_format.opcode = cop1_op;
 395                                 mips32_insn.fp1_format.op = op;
 396                                 mips32_insn.fp1_format.rt =
 397                                         insn.mm_fp1_format.rt;
 398                                 mips32_insn.fp1_format.fs =
 399                                         insn.mm_fp1_format.fs;
 400                                 mips32_insn.fp1_format.fd = 0;
 401                                 mips32_insn.fp1_format.func = 0;
 402                                 break;
 403                         default:
 404                                 return SIGILL;
 405                         }
 406                         break;
 407                 case mm_32f_74_op:      /* c.cond.fmt */
 408                         mips32_insn.fp0_format.opcode = cop1_op;
 409                         mips32_insn.fp0_format.fmt =
 410                                 sdps_format[insn.mm_fp4_format.fmt];
 411                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 412                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 413                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 414                         mips32_insn.fp0_format.func =
 415                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 416                         break;
 417                 default:
 418                         return SIGILL;
 419                 }
 420                 break;
 421         default:
 422                 return SIGILL;
 423         }
 424
 425         *insn_ptr = mips32_insn;
 426         return 0;
 427 }
 428
 429 /*
 430  * Redundant with logic already in kernel/branch.c,
 431  * embedded in compute_return_epc.  At some point,
 432  * a single subroutine should be used across both
 433  * modules.
 434  */
 435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 436                          unsigned long *contpc)
 437 {
 438         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 439         unsigned int fcr31;
 440         unsigned int bit = 0;
 441
 442         switch (insn.i_format.opcode) {
 443         case spec_op:
 444                 switch (insn.r_format.func) {
 445                 case jalr_op:
 446                         regs->regs[insn.r_format.rd] =
 447                                 regs->cp0_epc + dec_insn.pc_inc +
 448                                 dec_insn.next_pc_inc;
 449                         /* Fall through */
 450                 case jr_op:
 451                         /* For R6, JR already emulated in jalr_op */
 452                         if (NO_R6EMU && insn.r_format.opcode == jr_op)
 453                                 break;
 454                         *contpc = regs->regs[insn.r_format.rs];
 455                         return 1;
 456                 }
 457                 break;
 458         case bcond_op:
 459                 switch (insn.i_format.rt) {
 460                 case bltzal_op:
 461                 case bltzall_op:
 462                         if (NO_R6EMU && (insn.i_format.rs ||
 463                             insn.i_format.rt == bltzall_op))
 464                                 break;
 465
 466                         regs->regs[31] = regs->cp0_epc +
 467                                 dec_insn.pc_inc +
 468                                 dec_insn.next_pc_inc;
 469                         /* Fall through */
 470                 case bltzl_op:
 471                         if (NO_R6EMU)
 472                                 break;
 473                 case bltz_op:
 474                         if ((long)regs->regs[insn.i_format.rs] < 0)
 475                                 *contpc = regs->cp0_epc +
 476                                         dec_insn.pc_inc +
 477                                         (insn.i_format.simmediate << 2);
 478                         else
 479                                 *contpc = regs->cp0_epc +
 480                                         dec_insn.pc_inc +
 481                                         dec_insn.next_pc_inc;
 482                         return 1;
 483                 case bgezal_op:
 484                 case bgezall_op:
 485                         if (NO_R6EMU && (insn.i_format.rs ||
 486                             insn.i_format.rt == bgezall_op))
 487                                 break;
 488
 489                         regs->regs[31] = regs->cp0_epc +
 490                                 dec_insn.pc_inc +
 491                                 dec_insn.next_pc_inc;
 492                         /* Fall through */
 493                 case bgezl_op:
 494                         if (NO_R6EMU)
 495                                 break;
 496                 case bgez_op:
 497                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 498                                 *contpc = regs->cp0_epc +
 499                                         dec_insn.pc_inc +
 500                                         (insn.i_format.simmediate << 2);
 501                         else
 502                                 *contpc = regs->cp0_epc +
 503                                         dec_insn.pc_inc +
 504                                         dec_insn.next_pc_inc;
 505                         return 1;
 506                 }
 507                 break;
 508         case jalx_op:
 509                 set_isa16_mode(bit);
 510         case jal_op:
 511                 regs->regs[31] = regs->cp0_epc +
 512                         dec_insn.pc_inc +
 513                         dec_insn.next_pc_inc;
 514                 /* Fall through */
 515         case j_op:
 516                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 517                 *contpc >>= 28;
 518                 *contpc <<= 28;
 519                 *contpc |= (insn.j_format.target << 2);
 520                 /* Set microMIPS mode bit: XOR for jalx. */
 521                 *contpc ^= bit;
 522                 return 1;
 523         case beql_op:
 524                 if (NO_R6EMU)
 525                         break;
 526         case beq_op:
 527                 if (regs->regs[insn.i_format.rs] ==
 528                     regs->regs[insn.i_format.rt])
 529                         *contpc = regs->cp0_epc +
 530                                 dec_insn.pc_inc +
 531                                 (insn.i_format.simmediate << 2);
 532                 else
 533                         *contpc = regs->cp0_epc +
 534                                 dec_insn.pc_inc +
 535                                 dec_insn.next_pc_inc;
 536                 return 1;
 537         case bnel_op:
 538                 if (NO_R6EMU)
 539                         break;
 540         case bne_op:
 541                 if (regs->regs[insn.i_format.rs] !=
 542                     regs->regs[insn.i_format.rt])
 543                         *contpc = regs->cp0_epc +
 544                                 dec_insn.pc_inc +
 545                                 (insn.i_format.simmediate << 2);
 546                 else
 547                         *contpc = regs->cp0_epc +
 548                                 dec_insn.pc_inc +
 549                                 dec_insn.next_pc_inc;
 550                 return 1;
 551         case blezl_op:
 552                 if (NO_R6EMU)
 553                         break;
 554         case blez_op:
 555
 556                 /*
 557                  * Compact branches for R6 for the
 558                  * blez and blezl opcodes.
 559                  * BLEZ  | rs = 0 | rt != 0  == BLEZALC
 560                  * BLEZ  | rs = rt != 0      == BGEZALC
 561                  * BLEZ  | rs != 0 | rt != 0 == BGEUC
 562                  * BLEZL | rs = 0 | rt != 0  == BLEZC
 563                  * BLEZL | rs = rt != 0      == BGEZC
 564                  * BLEZL | rs != 0 | rt != 0 == BGEC
 565                  *
 566                  * For real BLEZ{,L}, rt is always 0.
 567                  */
 568                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 569                         if ((insn.i_format.opcode == blez_op) &&
 570                             ((!insn.i_format.rs && insn.i_format.rt) ||
 571                              (insn.i_format.rs == insn.i_format.rt)))
 572                                 regs->regs[31] = regs->cp0_epc +
 573                                         dec_insn.pc_inc;
 574                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 575                                 dec_insn.next_pc_inc;
 576
 577                         return 1;
 578                 }
 579                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 580                         *contpc = regs->cp0_epc +
 581                                 dec_insn.pc_inc +
 582                                 (insn.i_format.simmediate << 2);
 583                 else
 584                         *contpc = regs->cp0_epc +
 585                                 dec_insn.pc_inc +
 586                                 dec_insn.next_pc_inc;
 587                 return 1;
 588         case bgtzl_op:
 589                 if (NO_R6EMU)
 590                         break;
 591         case bgtz_op:
 592                 /*
 593                  * Compact branches for R6 for the
 594                  * bgtz and bgtzl opcodes.
 595                  * BGTZ  | rs = 0 | rt != 0  == BGTZALC
 596                  * BGTZ  | rs = rt != 0      == BLTZALC
 597                  * BGTZ  | rs != 0 | rt != 0 == BLTUC
 598                  * BGTZL | rs = 0 | rt != 0  == BGTZC
 599                  * BGTZL | rs = rt != 0      == BLTZC
 600                  * BGTZL | rs != 0 | rt != 0 == BLTC
 601                  *
 602                  * *ZALC varint for BGTZ &&& rt != 0
 603                  * For real GTZ{,L}, rt is always 0.
 604                  */
 605                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 606                         if ((insn.i_format.opcode == blez_op) &&
 607                             ((!insn.i_format.rs && insn.i_format.rt) ||
 608                              (insn.i_format.rs == insn.i_format.rt)))
 609                                 regs->regs[31] = regs->cp0_epc +
 610                                         dec_insn.pc_inc;
 611                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 612                                 dec_insn.next_pc_inc;
 613
 614                         return 1;
 615                 }
 616
 617                 if ((long)regs->regs[insn.i_format.rs] > 0)
 618                         *contpc = regs->cp0_epc +
 619                                 dec_insn.pc_inc +
 620                                 (insn.i_format.simmediate << 2);
 621                 else
 622                         *contpc = regs->cp0_epc +
 623                                 dec_insn.pc_inc +
 624                                 dec_insn.next_pc_inc;
 625                 return 1;
 626         case cbcond0_op:
 627         case cbcond1_op:
 628                 if (!cpu_has_mips_r6)
 629                         break;
 630                 if (insn.i_format.rt && !insn.i_format.rs)
 631                         regs->regs[31] = regs->cp0_epc + 4;
 632                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 633                         dec_insn.next_pc_inc;
 634
 635                 return 1;
 636 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 637         case lwc2_op: /* This is bbit0 on Octeon */
 638                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 639                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 640                 else
 641                         *contpc = regs->cp0_epc + 8;
 642                 return 1;
 643         case ldc2_op: /* This is bbit032 on Octeon */
 644                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 645                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 646                 else
 647                         *contpc = regs->cp0_epc + 8;
 648                 return 1;
 649         case swc2_op: /* This is bbit1 on Octeon */
 650                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 651                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 652                 else
 653                         *contpc = regs->cp0_epc + 8;
 654                 return 1;
 655         case sdc2_op: /* This is bbit132 on Octeon */
 656                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 657                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 658                 else
 659                         *contpc = regs->cp0_epc + 8;
 660                 return 1;
 661 #else
 662         case bc6_op:
 663                 /*
 664                  * Only valid for MIPS R6 but we can still end up
 665                  * here from a broken userland so just tell emulator
 666                  * this is not a branch and let it break later on.
 667                  */
 668                 if  (!cpu_has_mips_r6)
 669                         break;
 670                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 671                         dec_insn.next_pc_inc;
 672
 673                 return 1;
 674 #endif
 675         case cop0_op:
 676         case cop1_op:
 677                 /* Need to check for R6 bc1nez and bc1eqz branches */
 678                 if (cpu_has_mips_r6 &&
 679                     ((insn.i_format.rs == bc1eqz_op) ||
 680                      (insn.i_format.rs == bc1nez_op))) {
 681                         bit = 0;
 682                         switch (insn.i_format.rs) {
 683                         case bc1eqz_op:
 684                                 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
 685                                     bit = 1;
 686                                 break;
 687                         case bc1nez_op:
 688                                 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
 689                                     bit = 1;
 690                                 break;
 691                         }
 692                         if (bit)
 693                                 *contpc = regs->cp0_epc +
 694                                         dec_insn.pc_inc +
 695                                         (insn.i_format.simmediate << 2);
 696                         else
 697                                 *contpc = regs->cp0_epc +
 698                                         dec_insn.pc_inc +
 699                                         dec_insn.next_pc_inc;
 700
 701                         return 1;
 702                 }
 703                 /* R2/R6 compatible cop1 instruction. Fall through */
 704         case cop2_op:
 705         case cop1x_op:
 706                 if (insn.i_format.rs == bc_op) {
 707                         preempt_disable();
 708                         if (is_fpu_owner())
 709                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 710                         else
 711                                 fcr31 = current->thread.fpu.fcr31;
 712                         preempt_enable();
 713
 714                         bit = (insn.i_format.rt >> 2);
 715                         bit += (bit != 0);
 716                         bit += 23;
 717                         switch (insn.i_format.rt & 3) {
 718                         case 0: /* bc1f */
 719                         case 2: /* bc1fl */
 720                                 if (~fcr31 & (1 << bit))
 721                                         *contpc = regs->cp0_epc +
 722                                                 dec_insn.pc_inc +
 723                                                 (insn.i_format.simmediate << 2);
 724                                 else
 725                                         *contpc = regs->cp0_epc +
 726                                                 dec_insn.pc_inc +
 727                                                 dec_insn.next_pc_inc;
 728                                 return 1;
 729                         case 1: /* bc1t */
 730                         case 3: /* bc1tl */
 731                                 if (fcr31 & (1 << bit))
 732                                         *contpc = regs->cp0_epc +
 733                                                 dec_insn.pc_inc +
 734                                                 (insn.i_format.simmediate << 2);
 735                                 else
 736                                         *contpc = regs->cp0_epc +
 737                                                 dec_insn.pc_inc +
 738                                                 dec_insn.next_pc_inc;
 739                                 return 1;
 740                         }
 741                 }
 742                 break;
 743         }
 744         return 0;
 745 }
 746
 747 /*
 748  * In the Linux kernel, we support selection of FPR format on the
 749  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 750  * is hardwired to zero, which would imply a 32-bit FPU even for
 751  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 752  * FPU emu is slow and bulky and optimizing this function offers fairly
 753  * sizeable benefits so we try to be clever and make this function return
 754  * a constant whenever possible, that is on 64-bit kernels without O32
 755  * compatibility enabled and on 32-bit without 64-bit FPU support.
 756  */
 757 static inline int cop1_64bit(struct pt_regs *xcp)
 758 {
 759         if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
 760                 return 1;
 761         else if (config_enabled(CONFIG_32BIT) &&
 762                  !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
 763                 return 0;
 764
 765         return !test_thread_flag(TIF_32BIT_FPREGS);
 766 }
 767
 768 static inline bool hybrid_fprs(void)
 769 {
 770         return test_thread_flag(TIF_HYBRID_FPREGS);
 771 }
 772
 773 #define SIFROMREG(si, x)                                                \
 774 do {                                                                    \
 775         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
 776                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
 777         else                                                            \
 778                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 779 } while (0)
 780
 781 #define SITOREG(si, x)                                                  \
 782 do {                                                                    \
 783         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
 784                 unsigned i;                                             \
 785                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 786                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 787                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 788         } else {                                                        \
 789                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 790         }                                                               \
 791 } while (0)
 792
 793 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 794
 795 #define SITOHREG(si, x)                                                 \
 796 do {                                                                    \
 797         unsigned i;                                                     \
 798         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 799         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 800                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 801 } while (0)
 802
 803 #define DIFROMREG(di, x)                                                \
 804         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 805
 806 #define DITOREG(di, x)                                                  \
 807 do {                                                                    \
 808         unsigned fpr, i;                                                \
 809         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 810         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 811         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 812                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 813 } while (0)
 814
 815 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 816 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 817 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 818 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 819
 820 /*
 821  * Emulate the single floating point instruction pointed at by EPC.
 822  * Two instructions if the instruction is in a branch delay slot.
 823  */
 824
 825 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 826                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 827 {
 828         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 829         unsigned int cond, cbit;
 830         mips_instruction ir;
 831         int likely, pc_inc;
 832         u32 __user *wva;
 833         u64 __user *dva;
 834         u32 value;
 835         u32 wval;
 836         u64 dval;
 837         int sig;
 838
 839         /*
 840          * These are giving gcc a gentle hint about what to expect in
 841          * dec_inst in order to do better optimization.
 842          */
 843         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 844                 unreachable();
 845
 846         /* XXX NEC Vr54xx bug workaround */
 847         if (delay_slot(xcp)) {
 848                 if (dec_insn.micro_mips_mode) {
 849                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 850                                 clear_delay_slot(xcp);
 851                 } else {
 852                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 853                                 clear_delay_slot(xcp);
 854                 }
 855         }
 856
 857         if (delay_slot(xcp)) {
 858                 /*
 859                  * The instruction to be emulated is in a branch delay slot
 860                  * which means that we have to  emulate the branch instruction
 861                  * BEFORE we do the cop1 instruction.
 862                  *
 863                  * This branch could be a COP1 branch, but in that case we
 864                  * would have had a trap for that instruction, and would not
 865                  * come through this route.
 866                  *
 867                  * Linux MIPS branch emulator operates on context, updating the
 868                  * cp0_epc.
 869                  */
 870                 ir = dec_insn.next_insn;  /* process delay slot instr */
 871                 pc_inc = dec_insn.next_pc_inc;
 872         } else {
 873                 ir = dec_insn.insn;       /* process current instr */
 874                 pc_inc = dec_insn.pc_inc;
 875         }
 876
 877         /*
 878          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 879          * instructions, we want to convert microMIPS FPU instructions
 880          * into MIPS32 instructions so that we could reuse all of the
 881          * FPU emulation code.
 882          *
 883          * NOTE: We cannot do this for branch instructions since they
 884          *       are not a subset. Example: Cannot emulate a 16-bit
 885          *       aligned target address with a MIPS32 instruction.
 886          */
 887         if (dec_insn.micro_mips_mode) {
 888                 /*
 889                  * If next instruction is a 16-bit instruction, then it
 890                  * it cannot be a FPU instruction. This could happen
 891                  * since we can be called for non-FPU instructions.
 892                  */
 893                 if ((pc_inc == 2) ||
 894                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 895                          == SIGILL))
 896                         return SIGILL;
 897         }
 898
 899 emul:
 900         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 901         MIPS_FPU_EMU_INC_STATS(emulated);
 902         switch (MIPSInst_OPCODE(ir)) {
 903         case ldc1_op:
 904                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 905                                      MIPSInst_SIMM(ir));
 906                 MIPS_FPU_EMU_INC_STATS(loads);
 907
 908                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
 909                         MIPS_FPU_EMU_INC_STATS(errors);
 910                         *fault_addr = dva;
 911                         return SIGBUS;
 912                 }
 913                 if (__get_user(dval, dva)) {
 914                         MIPS_FPU_EMU_INC_STATS(errors);
 915                         *fault_addr = dva;
 916                         return SIGSEGV;
 917                 }
 918                 DITOREG(dval, MIPSInst_RT(ir));
 919                 break;
 920
 921         case sdc1_op:
 922                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 923                                       MIPSInst_SIMM(ir));
 924                 MIPS_FPU_EMU_INC_STATS(stores);
 925                 DIFROMREG(dval, MIPSInst_RT(ir));
 926                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
 927                         MIPS_FPU_EMU_INC_STATS(errors);
 928                         *fault_addr = dva;
 929                         return SIGBUS;
 930                 }
 931                 if (__put_user(dval, dva)) {
 932                         MIPS_FPU_EMU_INC_STATS(errors);
 933                         *fault_addr = dva;
 934                         return SIGSEGV;
 935                 }
 936                 break;
 937
 938         case lwc1_op:
 939                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 940                                       MIPSInst_SIMM(ir));
 941                 MIPS_FPU_EMU_INC_STATS(loads);
 942                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
 943                         MIPS_FPU_EMU_INC_STATS(errors);
 944                         *fault_addr = wva;
 945                         return SIGBUS;
 946                 }
 947                 if (__get_user(wval, wva)) {
 948                         MIPS_FPU_EMU_INC_STATS(errors);
 949                         *fault_addr = wva;
 950                         return SIGSEGV;
 951                 }
 952                 SITOREG(wval, MIPSInst_RT(ir));
 953                 break;
 954
 955         case swc1_op:
 956                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 957                                       MIPSInst_SIMM(ir));
 958                 MIPS_FPU_EMU_INC_STATS(stores);
 959                 SIFROMREG(wval, MIPSInst_RT(ir));
 960                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
 961                         MIPS_FPU_EMU_INC_STATS(errors);
 962                         *fault_addr = wva;
 963                         return SIGBUS;
 964                 }
 965                 if (__put_user(wval, wva)) {
 966                         MIPS_FPU_EMU_INC_STATS(errors);
 967                         *fault_addr = wva;
 968                         return SIGSEGV;
 969                 }
 970                 break;
 971
 972         case cop1_op:
 973                 switch (MIPSInst_RS(ir)) {
 974                 case dmfc_op:
 975                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 976                                 return SIGILL;
 977
 978                         /* copregister fs -> gpr[rt] */
 979                         if (MIPSInst_RT(ir) != 0) {
 980                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
 981                                         MIPSInst_RD(ir));
 982                         }
 983                         break;
 984
 985                 case dmtc_op:
 986                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
 987                                 return SIGILL;
 988
 989                         /* copregister fs <- rt */
 990                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
 991                         break;
 992
 993                 case mfhc_op:
 994                         if (!cpu_has_mips_r2)
 995                                 goto sigill;
 996
 997                         /* copregister rd -> gpr[rt] */
 998                         if (MIPSInst_RT(ir) != 0) {
 999                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1000                                         MIPSInst_RD(ir));
1001                         }
1002                         break;
1003
1004                 case mthc_op:
1005                         if (!cpu_has_mips_r2)
1006                                 goto sigill;
1007
1008                         /* copregister rd <- gpr[rt] */
1009                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1010                         break;
1011
1012                 case mfc_op:
1013                         /* copregister rd -> gpr[rt] */
1014                         if (MIPSInst_RT(ir) != 0) {
1015                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1016                                         MIPSInst_RD(ir));
1017                         }
1018                         break;
1019
1020                 case mtc_op:
1021                         /* copregister rd <- rt */
1022                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1023                         break;
1024
1025                 case cfc_op:
1026                         /* cop control register rd -> gpr[rt] */
1027                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
1028                                 value = ctx->fcr31;
1029                                 value = (value & ~FPU_CSR_RM) | modeindex(value);
1030                                 pr_debug("%p gpr[%d]<-csr=%08x\n",
1031                                          (void *) (xcp->cp0_epc),
1032                                          MIPSInst_RT(ir), value);
1033                         }
1034                         else if (MIPSInst_RD(ir) == FPCREG_RID)
1035                                 value = 0;
1036                         else
1037                                 value = 0;
1038                         if (MIPSInst_RT(ir))
1039                                 xcp->regs[MIPSInst_RT(ir)] = value;
1040                         break;
1041
1042                 case ctc_op:
1043                         /* copregister rd <- rt */
1044                         if (MIPSInst_RT(ir) == 0)
1045                                 value = 0;
1046                         else
1047                                 value = xcp->regs[MIPSInst_RT(ir)];
1048
1049                         /* we only have one writable control reg
1050                          */
1051                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
1052                                 pr_debug("%p gpr[%d]->csr=%08x\n",
1053                                          (void *) (xcp->cp0_epc),
1054                                          MIPSInst_RT(ir), value);
1055
1056                                 /*
1057                                  * Don't write reserved bits,
1058                                  * and convert to ieee library modes
1059                                  */
1060                                 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1061                                              modeindex(value);
1062                         }
1063                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1064                                 return SIGFPE;
1065                         }
1066                         break;
1067
1068                 case bc_op:
1069                         if (delay_slot(xcp))
1070                                 return SIGILL;
1071
1072                         if (cpu_has_mips_4_5_r)
1073                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1074                         else
1075                                 cbit = FPU_CSR_COND;
1076                         cond = ctx->fcr31 & cbit;
1077
1078                         likely = 0;
1079                         switch (MIPSInst_RT(ir) & 3) {
1080                         case bcfl_op:
1081                                 likely = 1;
1082                         case bcf_op:
1083                                 cond = !cond;
1084                                 break;
1085                         case bctl_op:
1086                                 likely = 1;
1087                         case bct_op:
1088                                 break;
1089                         default:
1090                                 /* thats an illegal instruction */
1091                                 return SIGILL;
1092                         }
1093
1094                         set_delay_slot(xcp);
1095                         if (cond) {
1096                                 /*
1097                                  * Branch taken: emulate dslot instruction
1098                                  */
1099                                 xcp->cp0_epc += dec_insn.pc_inc;
1100
1101                                 contpc = MIPSInst_SIMM(ir);
1102                                 ir = dec_insn.next_insn;
1103                                 if (dec_insn.micro_mips_mode) {
1104                                         contpc = (xcp->cp0_epc + (contpc << 1));
1105
1106                                         /* If 16-bit instruction, not FPU. */
1107                                         if ((dec_insn.next_pc_inc == 2) ||
1108                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1109
1110                                                 /*
1111                                                  * Since this instruction will
1112                                                  * be put on the stack with
1113                                                  * 32-bit words, get around
1114                                                  * this problem by putting a
1115                                                  * NOP16 as the second one.
1116                                                  */
1117                                                 if (dec_insn.next_pc_inc == 2)
1118                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1119
1120                                                 /*
1121                                                  * Single step the non-CP1
1122                                                  * instruction in the dslot.
1123                                                  */
1124                                                 return mips_dsemul(xcp, ir, contpc);
1125                                         }
1126                                 } else
1127                                         contpc = (xcp->cp0_epc + (contpc << 2));
1128
1129                                 switch (MIPSInst_OPCODE(ir)) {
1130                                 case lwc1_op:
1131                                         goto emul;
1132
1133                                 case swc1_op:
1134                                         goto emul;
1135
1136                                 case ldc1_op:
1137                                 case sdc1_op:
1138                                         if (cpu_has_mips_2_3_4_5 ||
1139                                             cpu_has_mips64)
1140                                                 goto emul;
1141
1142                                         return SIGILL;
1143                                         goto emul;
1144
1145                                 case cop1_op:
1146                                         goto emul;
1147
1148                                 case cop1x_op:
1149                                         if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1150                                                 /* its one of ours */
1151                                                 goto emul;
1152
1153                                         return SIGILL;
1154
1155                                 case spec_op:
1156                                         if (!cpu_has_mips_4_5_r)
1157                                                 return SIGILL;
1158
1159                                         if (MIPSInst_FUNC(ir) == movc_op)
1160                                                 goto emul;
1161                                         break;
1162                                 }
1163
1164                                 /*
1165                                  * Single step the non-cp1
1166                                  * instruction in the dslot
1167                                  */
1168                                 return mips_dsemul(xcp, ir, contpc);
1169                         } else if (likely) {    /* branch not taken */
1170                                         /*
1171                                          * branch likely nullifies
1172                                          * dslot if not taken
1173                                          */
1174                                         xcp->cp0_epc += dec_insn.pc_inc;
1175                                         contpc += dec_insn.pc_inc;
1176                                         /*
1177                                          * else continue & execute
1178                                          * dslot as normal insn
1179                                          */
1180                                 }
1181                         break;
1182
1183                 default:
1184                         if (!(MIPSInst_RS(ir) & 0x10))
1185                                 return SIGILL;
1186
1187                         /* a real fpu computation instruction */
1188                         if ((sig = fpu_emu(xcp, ctx, ir)))
1189                                 return sig;
1190                 }
1191                 break;
1192
1193         case cop1x_op:
1194                 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1195                         return SIGILL;
1196
1197                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1198                 if (sig)
1199                         return sig;
1200                 break;
1201
1202         case spec_op:
1203                 if (!cpu_has_mips_4_5_r)
1204                         return SIGILL;
1205
1206                 if (MIPSInst_FUNC(ir) != movc_op)
1207                         return SIGILL;
1208                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1209                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1210                         xcp->regs[MIPSInst_RD(ir)] =
1211                                 xcp->regs[MIPSInst_RS(ir)];
1212                 break;
1213         default:
1214 sigill:
1215                 return SIGILL;
1216         }
1217
1218         /* we did it !! */
1219         xcp->cp0_epc = contpc;
1220         clear_delay_slot(xcp);
1221
1222         return 0;
1223 }
1224
1225 /*
1226  * Conversion table from MIPS compare ops 48-63
1227  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1228  */
1229 static const unsigned char cmptab[8] = {
1230         0,                      /* cmp_0 (sig) cmp_sf */
1231         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1232         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1233         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1234         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1235         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1236         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1237         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1238 };
1239
1240
1241 /*
1242  * Additional MIPS4 instructions
1243  */
1244
1245 #define DEF3OP(name, p, f1, f2, f3)                                     \
1246 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1247         union ieee754##p s, union ieee754##p t)                         \
1248 {                                                                       \
1249         struct _ieee754_csr ieee754_csr_save;                           \
1250         s = f1(s, t);                                                   \
1251         ieee754_csr_save = ieee754_csr;                                 \
1252         s = f2(s, r);                                                   \
1253         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1254         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1255         s = f3(s);                                                      \
1256         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1257         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1258         return s;                                                       \
1259 }
1260
1261 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1262 {
1263         return ieee754dp_div(ieee754dp_one(0), d);
1264 }
1265
1266 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1267 {
1268         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1269 }
1270
1271 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1272 {
1273         return ieee754sp_div(ieee754sp_one(0), s);
1274 }
1275
1276 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1277 {
1278         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1279 }
1280
1281 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1282 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1283 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1284 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1285 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1286 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1287 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1288 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1289
1290 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1291         mips_instruction ir, void *__user *fault_addr)
1292 {
1293         unsigned rcsr = 0;      /* resulting csr */
1294
1295         MIPS_FPU_EMU_INC_STATS(cp1xops);
1296
1297         switch (MIPSInst_FMA_FFMT(ir)) {
1298         case s_fmt:{            /* 0 */
1299
1300                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1301                 union ieee754sp fd, fr, fs, ft;
1302                 u32 __user *va;
1303                 u32 val;
1304
1305                 switch (MIPSInst_FUNC(ir)) {
1306                 case lwxc1_op:
1307                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1308                                 xcp->regs[MIPSInst_FT(ir)]);
1309
1310                         MIPS_FPU_EMU_INC_STATS(loads);
1311                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1312                                 MIPS_FPU_EMU_INC_STATS(errors);
1313                                 *fault_addr = va;
1314                                 return SIGBUS;
1315                         }
1316                         if (__get_user(val, va)) {
1317                                 MIPS_FPU_EMU_INC_STATS(errors);
1318                                 *fault_addr = va;
1319                                 return SIGSEGV;
1320                         }
1321                         SITOREG(val, MIPSInst_FD(ir));
1322                         break;
1323
1324                 case swxc1_op:
1325                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1326                                 xcp->regs[MIPSInst_FT(ir)]);
1327
1328                         MIPS_FPU_EMU_INC_STATS(stores);
1329
1330                         SIFROMREG(val, MIPSInst_FS(ir));
1331                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1332                                 MIPS_FPU_EMU_INC_STATS(errors);
1333                                 *fault_addr = va;
1334                                 return SIGBUS;
1335                         }
1336                         if (put_user(val, va)) {
1337                                 MIPS_FPU_EMU_INC_STATS(errors);
1338                                 *fault_addr = va;
1339                                 return SIGSEGV;
1340                         }
1341                         break;
1342
1343                 case madd_s_op:
1344                         handler = fpemu_sp_madd;
1345                         goto scoptop;
1346                 case msub_s_op:
1347                         handler = fpemu_sp_msub;
1348                         goto scoptop;
1349                 case nmadd_s_op:
1350                         handler = fpemu_sp_nmadd;
1351                         goto scoptop;
1352                 case nmsub_s_op:
1353                         handler = fpemu_sp_nmsub;
1354                         goto scoptop;
1355
1356                       scoptop:
1357                         SPFROMREG(fr, MIPSInst_FR(ir));
1358                         SPFROMREG(fs, MIPSInst_FS(ir));
1359                         SPFROMREG(ft, MIPSInst_FT(ir));
1360                         fd = (*handler) (fr, fs, ft);
1361                         SPTOREG(fd, MIPSInst_FD(ir));
1362
1363                       copcsr:
1364                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1365                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1366                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1367                         }
1368                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1369                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1370                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1371                         }
1372                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1373                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1374                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1375                         }
1376                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1377                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1378                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1379                         }
1380
1381                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1382                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1383                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1384                                    ctx->fcr31); */
1385                                 return SIGFPE;
1386                         }
1387
1388                         break;
1389
1390                 default:
1391                         return SIGILL;
1392                 }
1393                 break;
1394         }
1395
1396         case d_fmt:{            /* 1 */
1397                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1398                 union ieee754dp fd, fr, fs, ft;
1399                 u64 __user *va;
1400                 u64 val;
1401
1402                 switch (MIPSInst_FUNC(ir)) {
1403                 case ldxc1_op:
1404                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1405                                 xcp->regs[MIPSInst_FT(ir)]);
1406
1407                         MIPS_FPU_EMU_INC_STATS(loads);
1408                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1409                                 MIPS_FPU_EMU_INC_STATS(errors);
1410                                 *fault_addr = va;
1411                                 return SIGBUS;
1412                         }
1413                         if (__get_user(val, va)) {
1414                                 MIPS_FPU_EMU_INC_STATS(errors);
1415                                 *fault_addr = va;
1416                                 return SIGSEGV;
1417                         }
1418                         DITOREG(val, MIPSInst_FD(ir));
1419                         break;
1420
1421                 case sdxc1_op:
1422                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1423                                 xcp->regs[MIPSInst_FT(ir)]);
1424
1425                         MIPS_FPU_EMU_INC_STATS(stores);
1426                         DIFROMREG(val, MIPSInst_FS(ir));
1427                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1428                                 MIPS_FPU_EMU_INC_STATS(errors);
1429                                 *fault_addr = va;
1430                                 return SIGBUS;
1431                         }
1432                         if (__put_user(val, va)) {
1433                                 MIPS_FPU_EMU_INC_STATS(errors);
1434                                 *fault_addr = va;
1435                                 return SIGSEGV;
1436                         }
1437                         break;
1438
1439                 case madd_d_op:
1440                         handler = fpemu_dp_madd;
1441                         goto dcoptop;
1442                 case msub_d_op:
1443                         handler = fpemu_dp_msub;
1444                         goto dcoptop;
1445                 case nmadd_d_op:
1446                         handler = fpemu_dp_nmadd;
1447                         goto dcoptop;
1448                 case nmsub_d_op:
1449                         handler = fpemu_dp_nmsub;
1450                         goto dcoptop;
1451
1452                       dcoptop:
1453                         DPFROMREG(fr, MIPSInst_FR(ir));
1454                         DPFROMREG(fs, MIPSInst_FS(ir));
1455                         DPFROMREG(ft, MIPSInst_FT(ir));
1456                         fd = (*handler) (fr, fs, ft);
1457                         DPTOREG(fd, MIPSInst_FD(ir));
1458                         goto copcsr;
1459
1460                 default:
1461                         return SIGILL;
1462                 }
1463                 break;
1464         }
1465
1466         case 0x3:
1467                 if (MIPSInst_FUNC(ir) != pfetch_op)
1468                         return SIGILL;
1469
1470                 /* ignore prefx operation */
1471                 break;
1472
1473         default:
1474                 return SIGILL;
1475         }
1476
1477         return 0;
1478 }
1479
1480
1481
1482 /*
1483  * Emulate a single COP1 arithmetic instruction.
1484  */
1485 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1486         mips_instruction ir)
1487 {
1488         int rfmt;               /* resulting format */
1489         unsigned rcsr = 0;      /* resulting csr */
1490         unsigned int oldrm;
1491         unsigned int cbit;
1492         unsigned cond;
1493         union {
1494                 union ieee754dp d;
1495                 union ieee754sp s;
1496                 int w;
1497                 s64 l;
1498         } rv;                   /* resulting value */
1499         u64 bits;
1500
1501         MIPS_FPU_EMU_INC_STATS(cp1ops);
1502         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1503         case s_fmt: {           /* 0 */
1504                 union {
1505                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1506                         union ieee754sp(*u) (union ieee754sp);
1507                 } handler;
1508                 union ieee754sp fs, ft;
1509
1510                 switch (MIPSInst_FUNC(ir)) {
1511                         /* binary ops */
1512                 case fadd_op:
1513                         handler.b = ieee754sp_add;
1514                         goto scopbop;
1515                 case fsub_op:
1516                         handler.b = ieee754sp_sub;
1517                         goto scopbop;
1518                 case fmul_op:
1519                         handler.b = ieee754sp_mul;
1520                         goto scopbop;
1521                 case fdiv_op:
1522                         handler.b = ieee754sp_div;
1523                         goto scopbop;
1524
1525                         /* unary  ops */
1526                 case fsqrt_op:
1527                         if (!cpu_has_mips_4_5_r)
1528                                 return SIGILL;
1529
1530                         handler.u = ieee754sp_sqrt;
1531                         goto scopuop;
1532
1533                 /*
1534                  * Note that on some MIPS IV implementations such as the
1535                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1536                  * achieve full IEEE-754 accuracy - however this emulator does.
1537                  */
1538                 case frsqrt_op:
1539                         if (!cpu_has_mips_4_5_r2)
1540                                 return SIGILL;
1541
1542                         handler.u = fpemu_sp_rsqrt;
1543                         goto scopuop;
1544
1545                 case frecip_op:
1546                         if (!cpu_has_mips_4_5_r2)
1547                                 return SIGILL;
1548
1549                         handler.u = fpemu_sp_recip;
1550                         goto scopuop;
1551
1552                 case fmovc_op:
1553                         if (!cpu_has_mips_4_5_r)
1554                                 return SIGILL;
1555
1556                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1557                         if (((ctx->fcr31 & cond) != 0) !=
1558                                 ((MIPSInst_FT(ir) & 1) != 0))
1559                                 return 0;
1560                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1561                         break;
1562
1563                 case fmovz_op:
1564                         if (!cpu_has_mips_4_5_r)
1565                                 return SIGILL;
1566
1567                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1568                                 return 0;
1569                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1570                         break;
1571
1572                 case fmovn_op:
1573                         if (!cpu_has_mips_4_5_r)
1574                                 return SIGILL;
1575
1576                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1577                                 return 0;
1578                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1579                         break;
1580
1581                 case fabs_op:
1582                         handler.u = ieee754sp_abs;
1583                         goto scopuop;
1584
1585                 case fneg_op:
1586                         handler.u = ieee754sp_neg;
1587                         goto scopuop;
1588
1589                 case fmov_op:
1590                         /* an easy one */
1591                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1592                         goto copcsr;
1593
1594                         /* binary op on handler */
1595 scopbop:
1596                         SPFROMREG(fs, MIPSInst_FS(ir));
1597                         SPFROMREG(ft, MIPSInst_FT(ir));
1598
1599                         rv.s = (*handler.b) (fs, ft);
1600                         goto copcsr;
1601 scopuop:
1602                         SPFROMREG(fs, MIPSInst_FS(ir));
1603                         rv.s = (*handler.u) (fs);
1604                         goto copcsr;
1605 copcsr:
1606                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1607                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1608                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1609                         }
1610                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1611                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1612                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1613                         }
1614                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1615                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1616                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1617                         }
1618                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1619                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1620                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1621                         }
1622                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1623                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1624                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1625                         }
1626                         break;
1627
1628                         /* unary conv ops */
1629                 case fcvts_op:
1630                         return SIGILL;  /* not defined */
1631
1632                 case fcvtd_op:
1633                         SPFROMREG(fs, MIPSInst_FS(ir));
1634                         rv.d = ieee754dp_fsp(fs);
1635                         rfmt = d_fmt;
1636                         goto copcsr;
1637
1638                 case fcvtw_op:
1639                         SPFROMREG(fs, MIPSInst_FS(ir));
1640                         rv.w = ieee754sp_tint(fs);
1641                         rfmt = w_fmt;
1642                         goto copcsr;
1643
1644                 case fround_op:
1645                 case ftrunc_op:
1646                 case fceil_op:
1647                 case ffloor_op:
1648                         if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1649                                 return SIGILL;
1650
1651                         oldrm = ieee754_csr.rm;
1652                         SPFROMREG(fs, MIPSInst_FS(ir));
1653                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1654                         rv.w = ieee754sp_tint(fs);
1655                         ieee754_csr.rm = oldrm;
1656                         rfmt = w_fmt;
1657                         goto copcsr;
1658
1659                 case fcvtl_op:
1660                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1661                                 return SIGILL;
1662
1663                         SPFROMREG(fs, MIPSInst_FS(ir));
1664                         rv.l = ieee754sp_tlong(fs);
1665                         rfmt = l_fmt;
1666                         goto copcsr;
1667
1668                 case froundl_op:
1669                 case ftruncl_op:
1670                 case fceill_op:
1671                 case ffloorl_op:
1672                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1673                                 return SIGILL;
1674
1675                         oldrm = ieee754_csr.rm;
1676                         SPFROMREG(fs, MIPSInst_FS(ir));
1677                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1678                         rv.l = ieee754sp_tlong(fs);
1679                         ieee754_csr.rm = oldrm;
1680                         rfmt = l_fmt;
1681                         goto copcsr;
1682
1683                 default:
1684                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1685                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1686                                 union ieee754sp fs, ft;
1687
1688                                 SPFROMREG(fs, MIPSInst_FS(ir));
1689                                 SPFROMREG(ft, MIPSInst_FT(ir));
1690                                 rv.w = ieee754sp_cmp(fs, ft,
1691                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1692                                 rfmt = -1;
1693                                 if ((cmpop & 0x8) && ieee754_cxtest
1694                                         (IEEE754_INVALID_OPERATION))
1695                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1696                                 else
1697                                         goto copcsr;
1698
1699                         } else
1700                                 return SIGILL;
1701                         break;
1702                 }
1703                 break;
1704         }
1705
1706         case d_fmt: {
1707                 union ieee754dp fs, ft;
1708                 union {
1709                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1710                         union ieee754dp(*u) (union ieee754dp);
1711                 } handler;
1712
1713                 switch (MIPSInst_FUNC(ir)) {
1714                         /* binary ops */
1715                 case fadd_op:
1716                         handler.b = ieee754dp_add;
1717                         goto dcopbop;
1718                 case fsub_op:
1719                         handler.b = ieee754dp_sub;
1720                         goto dcopbop;
1721                 case fmul_op:
1722                         handler.b = ieee754dp_mul;
1723                         goto dcopbop;
1724                 case fdiv_op:
1725                         handler.b = ieee754dp_div;
1726                         goto dcopbop;
1727
1728                         /* unary  ops */
1729                 case fsqrt_op:
1730                         if (!cpu_has_mips_2_3_4_5_r)
1731                                 return SIGILL;
1732
1733                         handler.u = ieee754dp_sqrt;
1734                         goto dcopuop;
1735                 /*
1736                  * Note that on some MIPS IV implementations such as the
1737                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1738                  * achieve full IEEE-754 accuracy - however this emulator does.
1739                  */
1740                 case frsqrt_op:
1741                         if (!cpu_has_mips_4_5_r2)
1742                                 return SIGILL;
1743
1744                         handler.u = fpemu_dp_rsqrt;
1745                         goto dcopuop;
1746                 case frecip_op:
1747                         if (!cpu_has_mips_4_5_r2)
1748                                 return SIGILL;
1749
1750                         handler.u = fpemu_dp_recip;
1751                         goto dcopuop;
1752                 case fmovc_op:
1753                         if (!cpu_has_mips_4_5_r)
1754                                 return SIGILL;
1755
1756                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1757                         if (((ctx->fcr31 & cond) != 0) !=
1758                                 ((MIPSInst_FT(ir) & 1) != 0))
1759                                 return 0;
1760                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1761                         break;
1762                 case fmovz_op:
1763                         if (!cpu_has_mips_4_5_r)
1764                                 return SIGILL;
1765
1766                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1767                                 return 0;
1768                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1769                         break;
1770                 case fmovn_op:
1771                         if (!cpu_has_mips_4_5_r)
1772                                 return SIGILL;
1773
1774                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1775                                 return 0;
1776                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1777                         break;
1778                 case fabs_op:
1779                         handler.u = ieee754dp_abs;
1780                         goto dcopuop;
1781
1782                 case fneg_op:
1783                         handler.u = ieee754dp_neg;
1784                         goto dcopuop;
1785
1786                 case fmov_op:
1787                         /* an easy one */
1788                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1789                         goto copcsr;
1790
1791                         /* binary op on handler */
1792 dcopbop:
1793                         DPFROMREG(fs, MIPSInst_FS(ir));
1794                         DPFROMREG(ft, MIPSInst_FT(ir));
1795
1796                         rv.d = (*handler.b) (fs, ft);
1797                         goto copcsr;
1798 dcopuop:
1799                         DPFROMREG(fs, MIPSInst_FS(ir));
1800                         rv.d = (*handler.u) (fs);
1801                         goto copcsr;
1802
1803                 /*
1804                  * unary conv ops
1805                  */
1806                 case fcvts_op:
1807                         DPFROMREG(fs, MIPSInst_FS(ir));
1808                         rv.s = ieee754sp_fdp(fs);
1809                         rfmt = s_fmt;
1810                         goto copcsr;
1811
1812                 case fcvtd_op:
1813                         return SIGILL;  /* not defined */
1814
1815                 case fcvtw_op:
1816                         DPFROMREG(fs, MIPSInst_FS(ir));
1817                         rv.w = ieee754dp_tint(fs);      /* wrong */
1818                         rfmt = w_fmt;
1819                         goto copcsr;
1820
1821                 case fround_op:
1822                 case ftrunc_op:
1823                 case fceil_op:
1824                 case ffloor_op:
1825                         if (!cpu_has_mips_2_3_4_5_r)
1826                                 return SIGILL;
1827
1828                         oldrm = ieee754_csr.rm;
1829                         DPFROMREG(fs, MIPSInst_FS(ir));
1830                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1831                         rv.w = ieee754dp_tint(fs);
1832                         ieee754_csr.rm = oldrm;
1833                         rfmt = w_fmt;
1834                         goto copcsr;
1835
1836                 case fcvtl_op:
1837                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1838                                 return SIGILL;
1839
1840                         DPFROMREG(fs, MIPSInst_FS(ir));
1841                         rv.l = ieee754dp_tlong(fs);
1842                         rfmt = l_fmt;
1843                         goto copcsr;
1844
1845                 case froundl_op:
1846                 case ftruncl_op:
1847                 case fceill_op:
1848                 case ffloorl_op:
1849                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1850                                 return SIGILL;
1851
1852                         oldrm = ieee754_csr.rm;
1853                         DPFROMREG(fs, MIPSInst_FS(ir));
1854                         ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1855                         rv.l = ieee754dp_tlong(fs);
1856                         ieee754_csr.rm = oldrm;
1857                         rfmt = l_fmt;
1858                         goto copcsr;
1859
1860                 default:
1861                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1862                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1863                                 union ieee754dp fs, ft;
1864
1865                                 DPFROMREG(fs, MIPSInst_FS(ir));
1866                                 DPFROMREG(ft, MIPSInst_FT(ir));
1867                                 rv.w = ieee754dp_cmp(fs, ft,
1868                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1869                                 rfmt = -1;
1870                                 if ((cmpop & 0x8)
1871                                         &&
1872                                         ieee754_cxtest
1873                                         (IEEE754_INVALID_OPERATION))
1874                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1875                                 else
1876                                         goto copcsr;
1877
1878                         }
1879                         else {
1880                                 return SIGILL;
1881                         }
1882                         break;
1883                 }
1884                 break;
1885
1886         case w_fmt:
1887                 switch (MIPSInst_FUNC(ir)) {
1888                 case fcvts_op:
1889                         /* convert word to single precision real */
1890                         SPFROMREG(fs, MIPSInst_FS(ir));
1891                         rv.s = ieee754sp_fint(fs.bits);
1892                         rfmt = s_fmt;
1893                         goto copcsr;
1894                 case fcvtd_op:
1895                         /* convert word to double precision real */
1896                         SPFROMREG(fs, MIPSInst_FS(ir));
1897                         rv.d = ieee754dp_fint(fs.bits);
1898                         rfmt = d_fmt;
1899                         goto copcsr;
1900                 default:
1901                         return SIGILL;
1902                 }
1903                 break;
1904         }
1905
1906         case l_fmt:
1907
1908                 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1909                         return SIGILL;
1910
1911                 DIFROMREG(bits, MIPSInst_FS(ir));
1912
1913                 switch (MIPSInst_FUNC(ir)) {
1914                 case fcvts_op:
1915                         /* convert long to single precision real */
1916                         rv.s = ieee754sp_flong(bits);
1917                         rfmt = s_fmt;
1918                         goto copcsr;
1919                 case fcvtd_op:
1920                         /* convert long to double precision real */
1921                         rv.d = ieee754dp_flong(bits);
1922                         rfmt = d_fmt;
1923                         goto copcsr;
1924                 default:
1925                         return SIGILL;
1926                 }
1927                 break;
1928
1929         default:
1930                 return SIGILL;
1931         }
1932
1933         /*
1934          * Update the fpu CSR register for this operation.
1935          * If an exception is required, generate a tidy SIGFPE exception,
1936          * without updating the result register.
1937          * Note: cause exception bits do not accumulate, they are rewritten
1938          * for each op; only the flag/sticky bits accumulate.
1939          */
1940         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1941         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1942                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1943                 return SIGFPE;
1944         }
1945
1946         /*
1947          * Now we can safely write the result back to the register file.
1948          */
1949         switch (rfmt) {
1950         case -1:
1951
1952                 if (cpu_has_mips_4_5_r)
1953                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1954                 else
1955                         cbit = FPU_CSR_COND;
1956                 if (rv.w)
1957                         ctx->fcr31 |= cbit;
1958                 else
1959                         ctx->fcr31 &= ~cbit;
1960                 break;
1961
1962         case d_fmt:
1963                 DPTOREG(rv.d, MIPSInst_FD(ir));
1964                 break;
1965         case s_fmt:
1966                 SPTOREG(rv.s, MIPSInst_FD(ir));
1967                 break;
1968         case w_fmt:
1969                 SITOREG(rv.w, MIPSInst_FD(ir));
1970                 break;
1971         case l_fmt:
1972                 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1973                         return SIGILL;
1974
1975                 DITOREG(rv.l, MIPSInst_FD(ir));
1976                 break;
1977         default:
1978                 return SIGILL;
1979         }
1980
1981         return 0;
1982 }
1983
1984 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1985         int has_fpu, void *__user *fault_addr)
1986 {
1987         unsigned long oldepc, prevepc;
1988         struct mm_decoded_insn dec_insn;
1989         u16 instr[4];
1990         u16 *instr_ptr;
1991         int sig = 0;
1992
1993         oldepc = xcp->cp0_epc;
1994         do {
1995                 prevepc = xcp->cp0_epc;
1996
1997                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1998                         /*
1999                          * Get next 2 microMIPS instructions and convert them
2000                          * into 32-bit instructions.
2001                          */
2002                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2003                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2004                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2005                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2006                                 MIPS_FPU_EMU_INC_STATS(errors);
2007                                 return SIGBUS;
2008                         }
2009                         instr_ptr = instr;
2010
2011                         /* Get first instruction. */
2012                         if (mm_insn_16bit(*instr_ptr)) {
2013                                 /* Duplicate the half-word. */
2014                                 dec_insn.insn = (*instr_ptr << 16) |
2015                                         (*instr_ptr);
2016                                 /* 16-bit instruction. */
2017                                 dec_insn.pc_inc = 2;
2018                                 instr_ptr += 1;
2019                         } else {
2020                                 dec_insn.insn = (*instr_ptr << 16) |
2021                                         *(instr_ptr+1);
2022                                 /* 32-bit instruction. */
2023                                 dec_insn.pc_inc = 4;
2024                                 instr_ptr += 2;
2025                         }
2026                         /* Get second instruction. */
2027                         if (mm_insn_16bit(*instr_ptr)) {
2028                                 /* Duplicate the half-word. */
2029                                 dec_insn.next_insn = (*instr_ptr << 16) |
2030                                         (*instr_ptr);
2031                                 /* 16-bit instruction. */
2032                                 dec_insn.next_pc_inc = 2;
2033                         } else {
2034                                 dec_insn.next_insn = (*instr_ptr << 16) |
2035                                         *(instr_ptr+1);
2036                                 /* 32-bit instruction. */
2037                                 dec_insn.next_pc_inc = 4;
2038                         }
2039                         dec_insn.micro_mips_mode = 1;
2040                 } else {
2041                         if ((get_user(dec_insn.insn,
2042                             (mips_instruction __user *) xcp->cp0_epc)) ||
2043                             (get_user(dec_insn.next_insn,
2044                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2045                                 MIPS_FPU_EMU_INC_STATS(errors);
2046                                 return SIGBUS;
2047                         }
2048                         dec_insn.pc_inc = 4;
2049                         dec_insn.next_pc_inc = 4;
2050                         dec_insn.micro_mips_mode = 0;
2051                 }
2052
2053                 if ((dec_insn.insn == 0) ||
2054                    ((dec_insn.pc_inc == 2) &&
2055                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2056                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2057                 else {
2058                         /*
2059                          * The 'ieee754_csr' is an alias of
2060                          * ctx->fcr31.  No need to copy ctx->fcr31 to
2061                          * ieee754_csr.  But ieee754_csr.rm is ieee
2062                          * library modes. (not mips rounding mode)
2063                          */
2064                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2065                 }
2066
2067                 if (has_fpu)
2068                         break;
2069                 if (sig)
2070                         break;
2071
2072                 cond_resched();
2073         } while (xcp->cp0_epc > prevepc);
2074
2075         /* SIGILL indicates a non-fpu instruction */
2076         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2077                 /* but if EPC has advanced, then ignore it */
2078                 sig = 0;
2079
2080         return sig;
2081 }