2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
54 /* Function which emulates a floating point instruction. */
56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 static int fpux_emu(struct pt_regs *,
60 struct mips_fpu_struct *, mips_instruction, void *__user *);
62 /* Control registers */
64 #define FPCREG_RID 0 /* $0 = revision id */
65 #define FPCREG_CSR 31 /* $31 = csr */
67 /* Determine rounding mode from the RM bits of the FCSR */
68 #define modeindex(v) ((v) & FPU_CSR_RM)
70 /* convert condition code register number to csr bit */
71 static const unsigned int fpucondbit[8] = {
82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89 * This functions translates a 32-bit microMIPS instruction
90 * into a 32-bit MIPS32 instruction. Returns 0 on success
91 * and SIGILL otherwise.
93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
95 union mips_instruction insn = *insn_ptr;
96 union mips_instruction mips32_insn = insn;
99 switch (insn.mm_i_format.opcode) {
101 mips32_insn.mm_i_format.opcode = ldc1_op;
102 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
103 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 mips32_insn.mm_i_format.opcode = lwc1_op;
107 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
108 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 mips32_insn.mm_i_format.opcode = sdc1_op;
112 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
113 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 mips32_insn.mm_i_format.opcode = swc1_op;
117 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
118 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 /* NOTE: offset is << by 1 if in microMIPS mode. */
122 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
123 (insn.mm_i_format.rt == mm_bc1t_op)) {
124 mips32_insn.fb_format.opcode = cop1_op;
125 mips32_insn.fb_format.bc = bc_op;
126 mips32_insn.fb_format.flag =
127 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
132 switch (insn.mm_fp0_format.func) {
141 op = insn.mm_fp0_format.func;
142 if (op == mm_32f_01_op)
144 else if (op == mm_32f_11_op)
146 else if (op == mm_32f_02_op)
148 else if (op == mm_32f_12_op)
150 else if (op == mm_32f_41_op)
152 else if (op == mm_32f_51_op)
154 else if (op == mm_32f_42_op)
158 mips32_insn.fp6_format.opcode = cop1x_op;
159 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
160 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
161 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
162 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
163 mips32_insn.fp6_format.func = func;
166 func = -1; /* Invalid */
167 op = insn.mm_fp5_format.op & 0x7;
168 if (op == mm_ldxc1_op)
170 else if (op == mm_sdxc1_op)
172 else if (op == mm_lwxc1_op)
174 else if (op == mm_swxc1_op)
178 mips32_insn.r_format.opcode = cop1x_op;
179 mips32_insn.r_format.rs =
180 insn.mm_fp5_format.base;
181 mips32_insn.r_format.rt =
182 insn.mm_fp5_format.index;
183 mips32_insn.r_format.rd = 0;
184 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
185 mips32_insn.r_format.func = func;
190 op = -1; /* Invalid */
191 if (insn.mm_fp2_format.op == mm_fmovt_op)
193 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 mips32_insn.fp0_format.opcode = cop1_op;
197 mips32_insn.fp0_format.fmt =
198 sdps_format[insn.mm_fp2_format.fmt];
199 mips32_insn.fp0_format.ft =
200 (insn.mm_fp2_format.cc<<2) + op;
201 mips32_insn.fp0_format.fs =
202 insn.mm_fp2_format.fs;
203 mips32_insn.fp0_format.fd =
204 insn.mm_fp2_format.fd;
205 mips32_insn.fp0_format.func = fmovc_op;
210 func = -1; /* Invalid */
211 if (insn.mm_fp0_format.op == mm_fadd_op)
213 else if (insn.mm_fp0_format.op == mm_fsub_op)
215 else if (insn.mm_fp0_format.op == mm_fmul_op)
217 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 mips32_insn.fp0_format.opcode = cop1_op;
221 mips32_insn.fp0_format.fmt =
222 sdps_format[insn.mm_fp0_format.fmt];
223 mips32_insn.fp0_format.ft =
224 insn.mm_fp0_format.ft;
225 mips32_insn.fp0_format.fs =
226 insn.mm_fp0_format.fs;
227 mips32_insn.fp0_format.fd =
228 insn.mm_fp0_format.fd;
229 mips32_insn.fp0_format.func = func;
234 func = -1; /* Invalid */
235 if (insn.mm_fp0_format.op == mm_fmovn_op)
237 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 mips32_insn.fp0_format.opcode = cop1_op;
241 mips32_insn.fp0_format.fmt =
242 sdps_format[insn.mm_fp0_format.fmt];
243 mips32_insn.fp0_format.ft =
244 insn.mm_fp0_format.ft;
245 mips32_insn.fp0_format.fs =
246 insn.mm_fp0_format.fs;
247 mips32_insn.fp0_format.fd =
248 insn.mm_fp0_format.fd;
249 mips32_insn.fp0_format.func = func;
253 case mm_32f_73_op: /* POOL32FXF */
254 switch (insn.mm_fp1_format.op) {
259 if ((insn.mm_fp1_format.op & 0x7f) ==
264 mips32_insn.r_format.opcode = spec_op;
265 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
266 mips32_insn.r_format.rt =
267 (insn.mm_fp4_format.cc << 2) + op;
268 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
269 mips32_insn.r_format.re = 0;
270 mips32_insn.r_format.func = movc_op;
276 if ((insn.mm_fp1_format.op & 0x7f) ==
279 fmt = swl_format[insn.mm_fp3_format.fmt];
282 fmt = dwl_format[insn.mm_fp3_format.fmt];
284 mips32_insn.fp0_format.opcode = cop1_op;
285 mips32_insn.fp0_format.fmt = fmt;
286 mips32_insn.fp0_format.ft = 0;
287 mips32_insn.fp0_format.fs =
288 insn.mm_fp3_format.fs;
289 mips32_insn.fp0_format.fd =
290 insn.mm_fp3_format.rt;
291 mips32_insn.fp0_format.func = func;
299 if ((insn.mm_fp1_format.op & 0x7f) ==
302 else if ((insn.mm_fp1_format.op & 0x7f) ==
307 mips32_insn.fp0_format.opcode = cop1_op;
308 mips32_insn.fp0_format.fmt =
309 sdps_format[insn.mm_fp3_format.fmt];
310 mips32_insn.fp0_format.ft = 0;
311 mips32_insn.fp0_format.fs =
312 insn.mm_fp3_format.fs;
313 mips32_insn.fp0_format.fd =
314 insn.mm_fp3_format.rt;
315 mips32_insn.fp0_format.func = func;
327 if (insn.mm_fp1_format.op == mm_ffloorl_op)
329 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
331 else if (insn.mm_fp1_format.op == mm_fceill_op)
333 else if (insn.mm_fp1_format.op == mm_fceilw_op)
335 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
337 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
339 else if (insn.mm_fp1_format.op == mm_froundl_op)
341 else if (insn.mm_fp1_format.op == mm_froundw_op)
343 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sd_format[insn.mm_fp1_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp1_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp1_format.rt;
355 mips32_insn.fp0_format.func = func;
360 if (insn.mm_fp1_format.op == mm_frsqrt_op)
362 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
366 mips32_insn.fp0_format.opcode = cop1_op;
367 mips32_insn.fp0_format.fmt =
368 sdps_format[insn.mm_fp1_format.fmt];
369 mips32_insn.fp0_format.ft = 0;
370 mips32_insn.fp0_format.fs =
371 insn.mm_fp1_format.fs;
372 mips32_insn.fp0_format.fd =
373 insn.mm_fp1_format.rt;
374 mips32_insn.fp0_format.func = func;
382 if (insn.mm_fp1_format.op == mm_mfc1_op)
384 else if (insn.mm_fp1_format.op == mm_mtc1_op)
386 else if (insn.mm_fp1_format.op == mm_cfc1_op)
388 else if (insn.mm_fp1_format.op == mm_ctc1_op)
390 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
394 mips32_insn.fp1_format.opcode = cop1_op;
395 mips32_insn.fp1_format.op = op;
396 mips32_insn.fp1_format.rt =
397 insn.mm_fp1_format.rt;
398 mips32_insn.fp1_format.fs =
399 insn.mm_fp1_format.fs;
400 mips32_insn.fp1_format.fd = 0;
401 mips32_insn.fp1_format.func = 0;
407 case mm_32f_74_op: /* c.cond.fmt */
408 mips32_insn.fp0_format.opcode = cop1_op;
409 mips32_insn.fp0_format.fmt =
410 sdps_format[insn.mm_fp4_format.fmt];
411 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
412 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
413 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
414 mips32_insn.fp0_format.func =
415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
425 *insn_ptr = mips32_insn;
430 * Redundant with logic already in kernel/branch.c,
431 * embedded in compute_return_epc. At some point,
432 * a single subroutine should be used across both
435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
436 unsigned long *contpc)
438 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
440 unsigned int bit = 0;
442 switch (insn.i_format.opcode) {
444 switch (insn.r_format.func) {
446 regs->regs[insn.r_format.rd] =
447 regs->cp0_epc + dec_insn.pc_inc +
448 dec_insn.next_pc_inc;
451 *contpc = regs->regs[insn.r_format.rs];
456 switch (insn.i_format.rt) {
459 regs->regs[31] = regs->cp0_epc +
461 dec_insn.next_pc_inc;
465 if ((long)regs->regs[insn.i_format.rs] < 0)
466 *contpc = regs->cp0_epc +
468 (insn.i_format.simmediate << 2);
470 *contpc = regs->cp0_epc +
472 dec_insn.next_pc_inc;
476 regs->regs[31] = regs->cp0_epc +
478 dec_insn.next_pc_inc;
482 if ((long)regs->regs[insn.i_format.rs] >= 0)
483 *contpc = regs->cp0_epc +
485 (insn.i_format.simmediate << 2);
487 *contpc = regs->cp0_epc +
489 dec_insn.next_pc_inc;
496 regs->regs[31] = regs->cp0_epc +
498 dec_insn.next_pc_inc;
501 *contpc = regs->cp0_epc + dec_insn.pc_inc;
504 *contpc |= (insn.j_format.target << 2);
505 /* Set microMIPS mode bit: XOR for jalx. */
510 if (regs->regs[insn.i_format.rs] ==
511 regs->regs[insn.i_format.rt])
512 *contpc = regs->cp0_epc +
514 (insn.i_format.simmediate << 2);
516 *contpc = regs->cp0_epc +
518 dec_insn.next_pc_inc;
522 if (regs->regs[insn.i_format.rs] !=
523 regs->regs[insn.i_format.rt])
524 *contpc = regs->cp0_epc +
526 (insn.i_format.simmediate << 2);
528 *contpc = regs->cp0_epc +
530 dec_insn.next_pc_inc;
534 if ((long)regs->regs[insn.i_format.rs] <= 0)
535 *contpc = regs->cp0_epc +
537 (insn.i_format.simmediate << 2);
539 *contpc = regs->cp0_epc +
541 dec_insn.next_pc_inc;
545 if ((long)regs->regs[insn.i_format.rs] > 0)
546 *contpc = regs->cp0_epc +
548 (insn.i_format.simmediate << 2);
550 *contpc = regs->cp0_epc +
552 dec_insn.next_pc_inc;
554 #ifdef CONFIG_CPU_CAVIUM_OCTEON
555 case lwc2_op: /* This is bbit0 on Octeon */
556 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
557 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
559 *contpc = regs->cp0_epc + 8;
561 case ldc2_op: /* This is bbit032 on Octeon */
562 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
563 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
565 *contpc = regs->cp0_epc + 8;
567 case swc2_op: /* This is bbit1 on Octeon */
568 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
569 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
571 *contpc = regs->cp0_epc + 8;
573 case sdc2_op: /* This is bbit132 on Octeon */
574 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
575 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
577 *contpc = regs->cp0_epc + 8;
584 if (insn.i_format.rs == bc_op) {
587 fcr31 = read_32bit_cp1_register(CP1_STATUS);
589 fcr31 = current->thread.fpu.fcr31;
592 bit = (insn.i_format.rt >> 2);
595 switch (insn.i_format.rt & 3) {
598 if (~fcr31 & (1 << bit))
599 *contpc = regs->cp0_epc +
601 (insn.i_format.simmediate << 2);
603 *contpc = regs->cp0_epc +
605 dec_insn.next_pc_inc;
609 if (fcr31 & (1 << bit))
610 *contpc = regs->cp0_epc +
612 (insn.i_format.simmediate << 2);
614 *contpc = regs->cp0_epc +
616 dec_insn.next_pc_inc;
626 * In the Linux kernel, we support selection of FPR format on the
627 * basis of the Status.FR bit. If an FPU is not present, the FR bit
628 * is hardwired to zero, which would imply a 32-bit FPU even for
629 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
630 * FPU emu is slow and bulky and optimizing this function offers fairly
631 * sizeable benefits so we try to be clever and make this function return
632 * a constant whenever possible, that is on 64-bit kernels without O32
633 * compatibility enabled and on 32-bit without 64-bit FPU support.
635 static inline int cop1_64bit(struct pt_regs *xcp)
637 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
639 else if (config_enabled(CONFIG_32BIT) &&
640 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
643 return !test_thread_flag(TIF_32BIT_FPREGS);
646 static inline bool hybrid_fprs(void)
648 return test_thread_flag(TIF_HYBRID_FPREGS);
651 #define SIFROMREG(si, x) \
653 if (cop1_64bit(xcp) && !hybrid_fprs()) \
654 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
656 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
659 #define SITOREG(si, x) \
661 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
663 set_fpr32(&ctx->fpr[x], 0, si); \
664 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
665 set_fpr32(&ctx->fpr[x], i, 0); \
667 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
671 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
673 #define SITOHREG(si, x) \
676 set_fpr32(&ctx->fpr[x], 1, si); \
677 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
678 set_fpr32(&ctx->fpr[x], i, 0); \
681 #define DIFROMREG(di, x) \
682 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
684 #define DITOREG(di, x) \
687 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
688 set_fpr64(&ctx->fpr[fpr], 0, di); \
689 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
690 set_fpr64(&ctx->fpr[fpr], i, 0); \
693 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
694 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
695 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
696 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
699 * Emulate the single floating point instruction pointed at by EPC.
700 * Two instructions if the instruction is in a branch delay slot.
703 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
704 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
706 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
707 unsigned int cond, cbit;
718 * These are giving gcc a gentle hint about what to expect in
719 * dec_inst in order to do better optimization.
721 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
724 /* XXX NEC Vr54xx bug workaround */
725 if (delay_slot(xcp)) {
726 if (dec_insn.micro_mips_mode) {
727 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
728 clear_delay_slot(xcp);
730 if (!isBranchInstr(xcp, dec_insn, &contpc))
731 clear_delay_slot(xcp);
735 if (delay_slot(xcp)) {
737 * The instruction to be emulated is in a branch delay slot
738 * which means that we have to emulate the branch instruction
739 * BEFORE we do the cop1 instruction.
741 * This branch could be a COP1 branch, but in that case we
742 * would have had a trap for that instruction, and would not
743 * come through this route.
745 * Linux MIPS branch emulator operates on context, updating the
748 ir = dec_insn.next_insn; /* process delay slot instr */
749 pc_inc = dec_insn.next_pc_inc;
751 ir = dec_insn.insn; /* process current instr */
752 pc_inc = dec_insn.pc_inc;
756 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
757 * instructions, we want to convert microMIPS FPU instructions
758 * into MIPS32 instructions so that we could reuse all of the
759 * FPU emulation code.
761 * NOTE: We cannot do this for branch instructions since they
762 * are not a subset. Example: Cannot emulate a 16-bit
763 * aligned target address with a MIPS32 instruction.
765 if (dec_insn.micro_mips_mode) {
767 * If next instruction is a 16-bit instruction, then it
768 * it cannot be a FPU instruction. This could happen
769 * since we can be called for non-FPU instructions.
772 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
778 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
779 MIPS_FPU_EMU_INC_STATS(emulated);
780 switch (MIPSInst_OPCODE(ir)) {
782 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
784 MIPS_FPU_EMU_INC_STATS(loads);
786 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
787 MIPS_FPU_EMU_INC_STATS(errors);
791 if (__get_user(dval, dva)) {
792 MIPS_FPU_EMU_INC_STATS(errors);
796 DITOREG(dval, MIPSInst_RT(ir));
800 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
802 MIPS_FPU_EMU_INC_STATS(stores);
803 DIFROMREG(dval, MIPSInst_RT(ir));
804 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
805 MIPS_FPU_EMU_INC_STATS(errors);
809 if (__put_user(dval, dva)) {
810 MIPS_FPU_EMU_INC_STATS(errors);
817 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
819 MIPS_FPU_EMU_INC_STATS(loads);
820 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
821 MIPS_FPU_EMU_INC_STATS(errors);
825 if (__get_user(wval, wva)) {
826 MIPS_FPU_EMU_INC_STATS(errors);
830 SITOREG(wval, MIPSInst_RT(ir));
834 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
836 MIPS_FPU_EMU_INC_STATS(stores);
837 SIFROMREG(wval, MIPSInst_RT(ir));
838 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
839 MIPS_FPU_EMU_INC_STATS(errors);
843 if (__put_user(wval, wva)) {
844 MIPS_FPU_EMU_INC_STATS(errors);
851 switch (MIPSInst_RS(ir)) {
853 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
856 /* copregister fs -> gpr[rt] */
857 if (MIPSInst_RT(ir) != 0) {
858 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
864 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
867 /* copregister fs <- rt */
868 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
872 if (!cpu_has_mips_r2)
875 /* copregister rd -> gpr[rt] */
876 if (MIPSInst_RT(ir) != 0) {
877 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
883 if (!cpu_has_mips_r2)
886 /* copregister rd <- gpr[rt] */
887 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
891 /* copregister rd -> gpr[rt] */
892 if (MIPSInst_RT(ir) != 0) {
893 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
899 /* copregister rd <- rt */
900 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
904 /* cop control register rd -> gpr[rt] */
905 if (MIPSInst_RD(ir) == FPCREG_CSR) {
907 value = (value & ~FPU_CSR_RM) | modeindex(value);
908 pr_debug("%p gpr[%d]<-csr=%08x\n",
909 (void *) (xcp->cp0_epc),
910 MIPSInst_RT(ir), value);
912 else if (MIPSInst_RD(ir) == FPCREG_RID)
917 xcp->regs[MIPSInst_RT(ir)] = value;
921 /* copregister rd <- rt */
922 if (MIPSInst_RT(ir) == 0)
925 value = xcp->regs[MIPSInst_RT(ir)];
927 /* we only have one writable control reg
929 if (MIPSInst_RD(ir) == FPCREG_CSR) {
930 pr_debug("%p gpr[%d]->csr=%08x\n",
931 (void *) (xcp->cp0_epc),
932 MIPSInst_RT(ir), value);
935 * Don't write reserved bits,
936 * and convert to ieee library modes
938 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
941 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
950 if (cpu_has_mips_4_5_r)
951 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
954 cond = ctx->fcr31 & cbit;
957 switch (MIPSInst_RT(ir) & 3) {
968 /* thats an illegal instruction */
975 * Branch taken: emulate dslot instruction
977 xcp->cp0_epc += dec_insn.pc_inc;
979 contpc = MIPSInst_SIMM(ir);
980 ir = dec_insn.next_insn;
981 if (dec_insn.micro_mips_mode) {
982 contpc = (xcp->cp0_epc + (contpc << 1));
984 /* If 16-bit instruction, not FPU. */
985 if ((dec_insn.next_pc_inc == 2) ||
986 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
989 * Since this instruction will
990 * be put on the stack with
991 * 32-bit words, get around
992 * this problem by putting a
993 * NOP16 as the second one.
995 if (dec_insn.next_pc_inc == 2)
996 ir = (ir & (~0xffff)) | MM_NOP16;
999 * Single step the non-CP1
1000 * instruction in the dslot.
1002 return mips_dsemul(xcp, ir, contpc);
1005 contpc = (xcp->cp0_epc + (contpc << 2));
1007 switch (MIPSInst_OPCODE(ir)) {
1016 if (cpu_has_mips_2_3_4_5 ||
1027 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1028 /* its one of ours */
1034 if (!cpu_has_mips_4_5_r)
1037 if (MIPSInst_FUNC(ir) == movc_op)
1043 * Single step the non-cp1
1044 * instruction in the dslot
1046 return mips_dsemul(xcp, ir, contpc);
1047 } else if (likely) { /* branch not taken */
1049 * branch likely nullifies
1050 * dslot if not taken
1052 xcp->cp0_epc += dec_insn.pc_inc;
1053 contpc += dec_insn.pc_inc;
1055 * else continue & execute
1056 * dslot as normal insn
1062 if (!(MIPSInst_RS(ir) & 0x10))
1065 /* a real fpu computation instruction */
1066 if ((sig = fpu_emu(xcp, ctx, ir)))
1072 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1075 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1081 if (!cpu_has_mips_4_5_r)
1084 if (MIPSInst_FUNC(ir) != movc_op)
1086 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1087 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1088 xcp->regs[MIPSInst_RD(ir)] =
1089 xcp->regs[MIPSInst_RS(ir)];
1097 xcp->cp0_epc = contpc;
1098 clear_delay_slot(xcp);
1104 * Conversion table from MIPS compare ops 48-63
1105 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1107 static const unsigned char cmptab[8] = {
1108 0, /* cmp_0 (sig) cmp_sf */
1109 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1110 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1111 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1112 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1113 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1114 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1115 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1120 * Additional MIPS4 instructions
1123 #define DEF3OP(name, p, f1, f2, f3) \
1124 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1125 union ieee754##p s, union ieee754##p t) \
1127 struct _ieee754_csr ieee754_csr_save; \
1129 ieee754_csr_save = ieee754_csr; \
1131 ieee754_csr_save.cx |= ieee754_csr.cx; \
1132 ieee754_csr_save.sx |= ieee754_csr.sx; \
1134 ieee754_csr.cx |= ieee754_csr_save.cx; \
1135 ieee754_csr.sx |= ieee754_csr_save.sx; \
1139 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1141 return ieee754dp_div(ieee754dp_one(0), d);
1144 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1146 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1149 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1151 return ieee754sp_div(ieee754sp_one(0), s);
1154 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1156 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1159 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1160 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1161 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1162 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1163 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1164 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1165 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1166 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1168 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1169 mips_instruction ir, void *__user *fault_addr)
1171 unsigned rcsr = 0; /* resulting csr */
1173 MIPS_FPU_EMU_INC_STATS(cp1xops);
1175 switch (MIPSInst_FMA_FFMT(ir)) {
1176 case s_fmt:{ /* 0 */
1178 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1179 union ieee754sp fd, fr, fs, ft;
1183 switch (MIPSInst_FUNC(ir)) {
1185 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1186 xcp->regs[MIPSInst_FT(ir)]);
1188 MIPS_FPU_EMU_INC_STATS(loads);
1189 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1190 MIPS_FPU_EMU_INC_STATS(errors);
1194 if (__get_user(val, va)) {
1195 MIPS_FPU_EMU_INC_STATS(errors);
1199 SITOREG(val, MIPSInst_FD(ir));
1203 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1204 xcp->regs[MIPSInst_FT(ir)]);
1206 MIPS_FPU_EMU_INC_STATS(stores);
1208 SIFROMREG(val, MIPSInst_FS(ir));
1209 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1210 MIPS_FPU_EMU_INC_STATS(errors);
1214 if (put_user(val, va)) {
1215 MIPS_FPU_EMU_INC_STATS(errors);
1222 handler = fpemu_sp_madd;
1225 handler = fpemu_sp_msub;
1228 handler = fpemu_sp_nmadd;
1231 handler = fpemu_sp_nmsub;
1235 SPFROMREG(fr, MIPSInst_FR(ir));
1236 SPFROMREG(fs, MIPSInst_FS(ir));
1237 SPFROMREG(ft, MIPSInst_FT(ir));
1238 fd = (*handler) (fr, fs, ft);
1239 SPTOREG(fd, MIPSInst_FD(ir));
1242 if (ieee754_cxtest(IEEE754_INEXACT)) {
1243 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1244 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1246 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1247 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1248 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1250 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1251 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1252 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1254 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1255 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1256 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1259 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1260 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1261 /*printk ("SIGFPE: FPU csr = %08x\n",
1274 case d_fmt:{ /* 1 */
1275 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1276 union ieee754dp fd, fr, fs, ft;
1280 switch (MIPSInst_FUNC(ir)) {
1282 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1283 xcp->regs[MIPSInst_FT(ir)]);
1285 MIPS_FPU_EMU_INC_STATS(loads);
1286 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1287 MIPS_FPU_EMU_INC_STATS(errors);
1291 if (__get_user(val, va)) {
1292 MIPS_FPU_EMU_INC_STATS(errors);
1296 DITOREG(val, MIPSInst_FD(ir));
1300 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1301 xcp->regs[MIPSInst_FT(ir)]);
1303 MIPS_FPU_EMU_INC_STATS(stores);
1304 DIFROMREG(val, MIPSInst_FS(ir));
1305 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1306 MIPS_FPU_EMU_INC_STATS(errors);
1310 if (__put_user(val, va)) {
1311 MIPS_FPU_EMU_INC_STATS(errors);
1318 handler = fpemu_dp_madd;
1321 handler = fpemu_dp_msub;
1324 handler = fpemu_dp_nmadd;
1327 handler = fpemu_dp_nmsub;
1331 DPFROMREG(fr, MIPSInst_FR(ir));
1332 DPFROMREG(fs, MIPSInst_FS(ir));
1333 DPFROMREG(ft, MIPSInst_FT(ir));
1334 fd = (*handler) (fr, fs, ft);
1335 DPTOREG(fd, MIPSInst_FD(ir));
1345 if (MIPSInst_FUNC(ir) != pfetch_op)
1348 /* ignore prefx operation */
1361 * Emulate a single COP1 arithmetic instruction.
1363 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1364 mips_instruction ir)
1366 int rfmt; /* resulting format */
1367 unsigned rcsr = 0; /* resulting csr */
1376 } rv; /* resulting value */
1379 MIPS_FPU_EMU_INC_STATS(cp1ops);
1380 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1381 case s_fmt: { /* 0 */
1383 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1384 union ieee754sp(*u) (union ieee754sp);
1386 union ieee754sp fs, ft;
1388 switch (MIPSInst_FUNC(ir)) {
1391 handler.b = ieee754sp_add;
1394 handler.b = ieee754sp_sub;
1397 handler.b = ieee754sp_mul;
1400 handler.b = ieee754sp_div;
1405 if (!cpu_has_mips_4_5_r)
1408 handler.u = ieee754sp_sqrt;
1412 * Note that on some MIPS IV implementations such as the
1413 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1414 * achieve full IEEE-754 accuracy - however this emulator does.
1417 if (!cpu_has_mips_4_5_r2)
1420 handler.u = fpemu_sp_rsqrt;
1424 if (!cpu_has_mips_4_5_r2)
1427 handler.u = fpemu_sp_recip;
1431 if (!cpu_has_mips_4_5_r)
1434 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1435 if (((ctx->fcr31 & cond) != 0) !=
1436 ((MIPSInst_FT(ir) & 1) != 0))
1438 SPFROMREG(rv.s, MIPSInst_FS(ir));
1442 if (!cpu_has_mips_4_5_r)
1445 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1447 SPFROMREG(rv.s, MIPSInst_FS(ir));
1451 if (!cpu_has_mips_4_5_r)
1454 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1456 SPFROMREG(rv.s, MIPSInst_FS(ir));
1460 handler.u = ieee754sp_abs;
1464 handler.u = ieee754sp_neg;
1469 SPFROMREG(rv.s, MIPSInst_FS(ir));
1472 /* binary op on handler */
1474 SPFROMREG(fs, MIPSInst_FS(ir));
1475 SPFROMREG(ft, MIPSInst_FT(ir));
1477 rv.s = (*handler.b) (fs, ft);
1480 SPFROMREG(fs, MIPSInst_FS(ir));
1481 rv.s = (*handler.u) (fs);
1484 if (ieee754_cxtest(IEEE754_INEXACT)) {
1485 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1486 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1488 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1489 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1490 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1492 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1493 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1494 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1496 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1497 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1498 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1500 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1501 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1502 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1506 /* unary conv ops */
1508 return SIGILL; /* not defined */
1511 SPFROMREG(fs, MIPSInst_FS(ir));
1512 rv.d = ieee754dp_fsp(fs);
1517 SPFROMREG(fs, MIPSInst_FS(ir));
1518 rv.w = ieee754sp_tint(fs);
1526 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1529 oldrm = ieee754_csr.rm;
1530 SPFROMREG(fs, MIPSInst_FS(ir));
1531 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1532 rv.w = ieee754sp_tint(fs);
1533 ieee754_csr.rm = oldrm;
1538 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1541 SPFROMREG(fs, MIPSInst_FS(ir));
1542 rv.l = ieee754sp_tlong(fs);
1550 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1553 oldrm = ieee754_csr.rm;
1554 SPFROMREG(fs, MIPSInst_FS(ir));
1555 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1556 rv.l = ieee754sp_tlong(fs);
1557 ieee754_csr.rm = oldrm;
1562 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1563 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1564 union ieee754sp fs, ft;
1566 SPFROMREG(fs, MIPSInst_FS(ir));
1567 SPFROMREG(ft, MIPSInst_FT(ir));
1568 rv.w = ieee754sp_cmp(fs, ft,
1569 cmptab[cmpop & 0x7], cmpop & 0x8);
1571 if ((cmpop & 0x8) && ieee754_cxtest
1572 (IEEE754_INVALID_OPERATION))
1573 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1585 union ieee754dp fs, ft;
1587 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1588 union ieee754dp(*u) (union ieee754dp);
1591 switch (MIPSInst_FUNC(ir)) {
1594 handler.b = ieee754dp_add;
1597 handler.b = ieee754dp_sub;
1600 handler.b = ieee754dp_mul;
1603 handler.b = ieee754dp_div;
1608 if (!cpu_has_mips_2_3_4_5_r)
1611 handler.u = ieee754dp_sqrt;
1614 * Note that on some MIPS IV implementations such as the
1615 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1616 * achieve full IEEE-754 accuracy - however this emulator does.
1619 if (!cpu_has_mips_4_5_r2)
1622 handler.u = fpemu_dp_rsqrt;
1625 if (!cpu_has_mips_4_5_r2)
1628 handler.u = fpemu_dp_recip;
1631 if (!cpu_has_mips_4_5_r)
1634 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1635 if (((ctx->fcr31 & cond) != 0) !=
1636 ((MIPSInst_FT(ir) & 1) != 0))
1638 DPFROMREG(rv.d, MIPSInst_FS(ir));
1641 if (!cpu_has_mips_4_5_r)
1644 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1646 DPFROMREG(rv.d, MIPSInst_FS(ir));
1649 if (!cpu_has_mips_4_5_r)
1652 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1654 DPFROMREG(rv.d, MIPSInst_FS(ir));
1657 handler.u = ieee754dp_abs;
1661 handler.u = ieee754dp_neg;
1666 DPFROMREG(rv.d, MIPSInst_FS(ir));
1669 /* binary op on handler */
1671 DPFROMREG(fs, MIPSInst_FS(ir));
1672 DPFROMREG(ft, MIPSInst_FT(ir));
1674 rv.d = (*handler.b) (fs, ft);
1677 DPFROMREG(fs, MIPSInst_FS(ir));
1678 rv.d = (*handler.u) (fs);
1685 DPFROMREG(fs, MIPSInst_FS(ir));
1686 rv.s = ieee754sp_fdp(fs);
1691 return SIGILL; /* not defined */
1694 DPFROMREG(fs, MIPSInst_FS(ir));
1695 rv.w = ieee754dp_tint(fs); /* wrong */
1703 if (!cpu_has_mips_2_3_4_5_r)
1706 oldrm = ieee754_csr.rm;
1707 DPFROMREG(fs, MIPSInst_FS(ir));
1708 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1709 rv.w = ieee754dp_tint(fs);
1710 ieee754_csr.rm = oldrm;
1715 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1718 DPFROMREG(fs, MIPSInst_FS(ir));
1719 rv.l = ieee754dp_tlong(fs);
1727 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1730 oldrm = ieee754_csr.rm;
1731 DPFROMREG(fs, MIPSInst_FS(ir));
1732 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1733 rv.l = ieee754dp_tlong(fs);
1734 ieee754_csr.rm = oldrm;
1739 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1740 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1741 union ieee754dp fs, ft;
1743 DPFROMREG(fs, MIPSInst_FS(ir));
1744 DPFROMREG(ft, MIPSInst_FT(ir));
1745 rv.w = ieee754dp_cmp(fs, ft,
1746 cmptab[cmpop & 0x7], cmpop & 0x8);
1751 (IEEE754_INVALID_OPERATION))
1752 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1765 switch (MIPSInst_FUNC(ir)) {
1767 /* convert word to single precision real */
1768 SPFROMREG(fs, MIPSInst_FS(ir));
1769 rv.s = ieee754sp_fint(fs.bits);
1773 /* convert word to double precision real */
1774 SPFROMREG(fs, MIPSInst_FS(ir));
1775 rv.d = ieee754dp_fint(fs.bits);
1786 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1789 DIFROMREG(bits, MIPSInst_FS(ir));
1791 switch (MIPSInst_FUNC(ir)) {
1793 /* convert long to single precision real */
1794 rv.s = ieee754sp_flong(bits);
1798 /* convert long to double precision real */
1799 rv.d = ieee754dp_flong(bits);
1812 * Update the fpu CSR register for this operation.
1813 * If an exception is required, generate a tidy SIGFPE exception,
1814 * without updating the result register.
1815 * Note: cause exception bits do not accumulate, they are rewritten
1816 * for each op; only the flag/sticky bits accumulate.
1818 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1819 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1820 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1825 * Now we can safely write the result back to the register file.
1830 if (cpu_has_mips_4_5_r)
1831 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1833 cbit = FPU_CSR_COND;
1837 ctx->fcr31 &= ~cbit;
1841 DPTOREG(rv.d, MIPSInst_FD(ir));
1844 SPTOREG(rv.s, MIPSInst_FD(ir));
1847 SITOREG(rv.w, MIPSInst_FD(ir));
1850 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1853 DITOREG(rv.l, MIPSInst_FD(ir));
1862 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1863 int has_fpu, void *__user *fault_addr)
1865 unsigned long oldepc, prevepc;
1866 struct mm_decoded_insn dec_insn;
1871 oldepc = xcp->cp0_epc;
1873 prevepc = xcp->cp0_epc;
1875 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1877 * Get next 2 microMIPS instructions and convert them
1878 * into 32-bit instructions.
1880 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
1881 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
1882 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
1883 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
1884 MIPS_FPU_EMU_INC_STATS(errors);
1889 /* Get first instruction. */
1890 if (mm_insn_16bit(*instr_ptr)) {
1891 /* Duplicate the half-word. */
1892 dec_insn.insn = (*instr_ptr << 16) |
1894 /* 16-bit instruction. */
1895 dec_insn.pc_inc = 2;
1898 dec_insn.insn = (*instr_ptr << 16) |
1900 /* 32-bit instruction. */
1901 dec_insn.pc_inc = 4;
1904 /* Get second instruction. */
1905 if (mm_insn_16bit(*instr_ptr)) {
1906 /* Duplicate the half-word. */
1907 dec_insn.next_insn = (*instr_ptr << 16) |
1909 /* 16-bit instruction. */
1910 dec_insn.next_pc_inc = 2;
1912 dec_insn.next_insn = (*instr_ptr << 16) |
1914 /* 32-bit instruction. */
1915 dec_insn.next_pc_inc = 4;
1917 dec_insn.micro_mips_mode = 1;
1919 if ((get_user(dec_insn.insn,
1920 (mips_instruction __user *) xcp->cp0_epc)) ||
1921 (get_user(dec_insn.next_insn,
1922 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
1923 MIPS_FPU_EMU_INC_STATS(errors);
1926 dec_insn.pc_inc = 4;
1927 dec_insn.next_pc_inc = 4;
1928 dec_insn.micro_mips_mode = 0;
1931 if ((dec_insn.insn == 0) ||
1932 ((dec_insn.pc_inc == 2) &&
1933 ((dec_insn.insn & 0xffff) == MM_NOP16)))
1934 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1937 * The 'ieee754_csr' is an alias of
1938 * ctx->fcr31. No need to copy ctx->fcr31 to
1939 * ieee754_csr. But ieee754_csr.rm is ieee
1940 * library modes. (not mips rounding mode)
1942 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1951 } while (xcp->cp0_epc > prevepc);
1953 /* SIGILL indicates a non-fpu instruction */
1954 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1955 /* but if EPC has advanced, then ignore it */