2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/processor.h>
49 #include <asm/fpu_emulator.h>
54 /* Function which emulates a floating point instruction. */
56 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 static int fpux_emu(struct pt_regs *,
60 struct mips_fpu_struct *, mips_instruction, void *__user *);
62 /* Control registers */
64 #define FPCREG_RID 0 /* $0 = revision id */
65 #define FPCREG_CSR 31 /* $31 = csr */
67 /* Determine rounding mode from the RM bits of the FCSR */
68 #define modeindex(v) ((v) & FPU_CSR_RM)
70 /* convert condition code register number to csr bit */
71 static const unsigned int fpucondbit[8] = {
82 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
83 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
84 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
85 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
86 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89 * This functions translates a 32-bit microMIPS instruction
90 * into a 32-bit MIPS32 instruction. Returns 0 on success
91 * and SIGILL otherwise.
93 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
95 union mips_instruction insn = *insn_ptr;
96 union mips_instruction mips32_insn = insn;
99 switch (insn.mm_i_format.opcode) {
101 mips32_insn.mm_i_format.opcode = ldc1_op;
102 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
103 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 mips32_insn.mm_i_format.opcode = lwc1_op;
107 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
108 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 mips32_insn.mm_i_format.opcode = sdc1_op;
112 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
113 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 mips32_insn.mm_i_format.opcode = swc1_op;
117 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
118 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 /* NOTE: offset is << by 1 if in microMIPS mode. */
122 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
123 (insn.mm_i_format.rt == mm_bc1t_op)) {
124 mips32_insn.fb_format.opcode = cop1_op;
125 mips32_insn.fb_format.bc = bc_op;
126 mips32_insn.fb_format.flag =
127 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
132 switch (insn.mm_fp0_format.func) {
141 op = insn.mm_fp0_format.func;
142 if (op == mm_32f_01_op)
144 else if (op == mm_32f_11_op)
146 else if (op == mm_32f_02_op)
148 else if (op == mm_32f_12_op)
150 else if (op == mm_32f_41_op)
152 else if (op == mm_32f_51_op)
154 else if (op == mm_32f_42_op)
158 mips32_insn.fp6_format.opcode = cop1x_op;
159 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
160 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
161 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
162 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
163 mips32_insn.fp6_format.func = func;
166 func = -1; /* Invalid */
167 op = insn.mm_fp5_format.op & 0x7;
168 if (op == mm_ldxc1_op)
170 else if (op == mm_sdxc1_op)
172 else if (op == mm_lwxc1_op)
174 else if (op == mm_swxc1_op)
178 mips32_insn.r_format.opcode = cop1x_op;
179 mips32_insn.r_format.rs =
180 insn.mm_fp5_format.base;
181 mips32_insn.r_format.rt =
182 insn.mm_fp5_format.index;
183 mips32_insn.r_format.rd = 0;
184 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
185 mips32_insn.r_format.func = func;
190 op = -1; /* Invalid */
191 if (insn.mm_fp2_format.op == mm_fmovt_op)
193 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 mips32_insn.fp0_format.opcode = cop1_op;
197 mips32_insn.fp0_format.fmt =
198 sdps_format[insn.mm_fp2_format.fmt];
199 mips32_insn.fp0_format.ft =
200 (insn.mm_fp2_format.cc<<2) + op;
201 mips32_insn.fp0_format.fs =
202 insn.mm_fp2_format.fs;
203 mips32_insn.fp0_format.fd =
204 insn.mm_fp2_format.fd;
205 mips32_insn.fp0_format.func = fmovc_op;
210 func = -1; /* Invalid */
211 if (insn.mm_fp0_format.op == mm_fadd_op)
213 else if (insn.mm_fp0_format.op == mm_fsub_op)
215 else if (insn.mm_fp0_format.op == mm_fmul_op)
217 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 mips32_insn.fp0_format.opcode = cop1_op;
221 mips32_insn.fp0_format.fmt =
222 sdps_format[insn.mm_fp0_format.fmt];
223 mips32_insn.fp0_format.ft =
224 insn.mm_fp0_format.ft;
225 mips32_insn.fp0_format.fs =
226 insn.mm_fp0_format.fs;
227 mips32_insn.fp0_format.fd =
228 insn.mm_fp0_format.fd;
229 mips32_insn.fp0_format.func = func;
234 func = -1; /* Invalid */
235 if (insn.mm_fp0_format.op == mm_fmovn_op)
237 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 mips32_insn.fp0_format.opcode = cop1_op;
241 mips32_insn.fp0_format.fmt =
242 sdps_format[insn.mm_fp0_format.fmt];
243 mips32_insn.fp0_format.ft =
244 insn.mm_fp0_format.ft;
245 mips32_insn.fp0_format.fs =
246 insn.mm_fp0_format.fs;
247 mips32_insn.fp0_format.fd =
248 insn.mm_fp0_format.fd;
249 mips32_insn.fp0_format.func = func;
253 case mm_32f_73_op: /* POOL32FXF */
254 switch (insn.mm_fp1_format.op) {
259 if ((insn.mm_fp1_format.op & 0x7f) ==
264 mips32_insn.r_format.opcode = spec_op;
265 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
266 mips32_insn.r_format.rt =
267 (insn.mm_fp4_format.cc << 2) + op;
268 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
269 mips32_insn.r_format.re = 0;
270 mips32_insn.r_format.func = movc_op;
276 if ((insn.mm_fp1_format.op & 0x7f) ==
279 fmt = swl_format[insn.mm_fp3_format.fmt];
282 fmt = dwl_format[insn.mm_fp3_format.fmt];
284 mips32_insn.fp0_format.opcode = cop1_op;
285 mips32_insn.fp0_format.fmt = fmt;
286 mips32_insn.fp0_format.ft = 0;
287 mips32_insn.fp0_format.fs =
288 insn.mm_fp3_format.fs;
289 mips32_insn.fp0_format.fd =
290 insn.mm_fp3_format.rt;
291 mips32_insn.fp0_format.func = func;
299 if ((insn.mm_fp1_format.op & 0x7f) ==
302 else if ((insn.mm_fp1_format.op & 0x7f) ==
307 mips32_insn.fp0_format.opcode = cop1_op;
308 mips32_insn.fp0_format.fmt =
309 sdps_format[insn.mm_fp3_format.fmt];
310 mips32_insn.fp0_format.ft = 0;
311 mips32_insn.fp0_format.fs =
312 insn.mm_fp3_format.fs;
313 mips32_insn.fp0_format.fd =
314 insn.mm_fp3_format.rt;
315 mips32_insn.fp0_format.func = func;
327 if (insn.mm_fp1_format.op == mm_ffloorl_op)
329 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
331 else if (insn.mm_fp1_format.op == mm_fceill_op)
333 else if (insn.mm_fp1_format.op == mm_fceilw_op)
335 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
337 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
339 else if (insn.mm_fp1_format.op == mm_froundl_op)
341 else if (insn.mm_fp1_format.op == mm_froundw_op)
343 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sd_format[insn.mm_fp1_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp1_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp1_format.rt;
355 mips32_insn.fp0_format.func = func;
360 if (insn.mm_fp1_format.op == mm_frsqrt_op)
362 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
366 mips32_insn.fp0_format.opcode = cop1_op;
367 mips32_insn.fp0_format.fmt =
368 sdps_format[insn.mm_fp1_format.fmt];
369 mips32_insn.fp0_format.ft = 0;
370 mips32_insn.fp0_format.fs =
371 insn.mm_fp1_format.fs;
372 mips32_insn.fp0_format.fd =
373 insn.mm_fp1_format.rt;
374 mips32_insn.fp0_format.func = func;
382 if (insn.mm_fp1_format.op == mm_mfc1_op)
384 else if (insn.mm_fp1_format.op == mm_mtc1_op)
386 else if (insn.mm_fp1_format.op == mm_cfc1_op)
388 else if (insn.mm_fp1_format.op == mm_ctc1_op)
390 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
394 mips32_insn.fp1_format.opcode = cop1_op;
395 mips32_insn.fp1_format.op = op;
396 mips32_insn.fp1_format.rt =
397 insn.mm_fp1_format.rt;
398 mips32_insn.fp1_format.fs =
399 insn.mm_fp1_format.fs;
400 mips32_insn.fp1_format.fd = 0;
401 mips32_insn.fp1_format.func = 0;
407 case mm_32f_74_op: /* c.cond.fmt */
408 mips32_insn.fp0_format.opcode = cop1_op;
409 mips32_insn.fp0_format.fmt =
410 sdps_format[insn.mm_fp4_format.fmt];
411 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
412 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
413 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
414 mips32_insn.fp0_format.func =
415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
425 *insn_ptr = mips32_insn;
430 * Redundant with logic already in kernel/branch.c,
431 * embedded in compute_return_epc. At some point,
432 * a single subroutine should be used across both
435 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
436 unsigned long *contpc)
438 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
440 unsigned int bit = 0;
442 switch (insn.i_format.opcode) {
444 switch (insn.r_format.func) {
446 regs->regs[insn.r_format.rd] =
447 regs->cp0_epc + dec_insn.pc_inc +
448 dec_insn.next_pc_inc;
451 *contpc = regs->regs[insn.r_format.rs];
456 switch (insn.i_format.rt) {
459 regs->regs[31] = regs->cp0_epc +
461 dec_insn.next_pc_inc;
465 if ((long)regs->regs[insn.i_format.rs] < 0)
466 *contpc = regs->cp0_epc +
468 (insn.i_format.simmediate << 2);
470 *contpc = regs->cp0_epc +
472 dec_insn.next_pc_inc;
476 regs->regs[31] = regs->cp0_epc +
478 dec_insn.next_pc_inc;
482 if ((long)regs->regs[insn.i_format.rs] >= 0)
483 *contpc = regs->cp0_epc +
485 (insn.i_format.simmediate << 2);
487 *contpc = regs->cp0_epc +
489 dec_insn.next_pc_inc;
496 regs->regs[31] = regs->cp0_epc +
498 dec_insn.next_pc_inc;
501 *contpc = regs->cp0_epc + dec_insn.pc_inc;
504 *contpc |= (insn.j_format.target << 2);
505 /* Set microMIPS mode bit: XOR for jalx. */
510 if (regs->regs[insn.i_format.rs] ==
511 regs->regs[insn.i_format.rt])
512 *contpc = regs->cp0_epc +
514 (insn.i_format.simmediate << 2);
516 *contpc = regs->cp0_epc +
518 dec_insn.next_pc_inc;
522 if (regs->regs[insn.i_format.rs] !=
523 regs->regs[insn.i_format.rt])
524 *contpc = regs->cp0_epc +
526 (insn.i_format.simmediate << 2);
528 *contpc = regs->cp0_epc +
530 dec_insn.next_pc_inc;
534 if ((long)regs->regs[insn.i_format.rs] <= 0)
535 *contpc = regs->cp0_epc +
537 (insn.i_format.simmediate << 2);
539 *contpc = regs->cp0_epc +
541 dec_insn.next_pc_inc;
545 if ((long)regs->regs[insn.i_format.rs] > 0)
546 *contpc = regs->cp0_epc +
548 (insn.i_format.simmediate << 2);
550 *contpc = regs->cp0_epc +
552 dec_insn.next_pc_inc;
554 #ifdef CONFIG_CPU_CAVIUM_OCTEON
555 case lwc2_op: /* This is bbit0 on Octeon */
556 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
557 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
559 *contpc = regs->cp0_epc + 8;
561 case ldc2_op: /* This is bbit032 on Octeon */
562 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
563 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
565 *contpc = regs->cp0_epc + 8;
567 case swc2_op: /* This is bbit1 on Octeon */
568 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
569 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
571 *contpc = regs->cp0_epc + 8;
573 case sdc2_op: /* This is bbit132 on Octeon */
574 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
575 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
577 *contpc = regs->cp0_epc + 8;
584 if (insn.i_format.rs == bc_op) {
591 "\t.set pop" : "=r" (fcr31));
593 fcr31 = current->thread.fpu.fcr31;
596 bit = (insn.i_format.rt >> 2);
599 switch (insn.i_format.rt & 3) {
602 if (~fcr31 & (1 << bit))
603 *contpc = regs->cp0_epc +
605 (insn.i_format.simmediate << 2);
607 *contpc = regs->cp0_epc +
609 dec_insn.next_pc_inc;
613 if (fcr31 & (1 << bit))
614 *contpc = regs->cp0_epc +
616 (insn.i_format.simmediate << 2);
618 *contpc = regs->cp0_epc +
620 dec_insn.next_pc_inc;
630 * In the Linux kernel, we support selection of FPR format on the
631 * basis of the Status.FR bit. If an FPU is not present, the FR bit
632 * is hardwired to zero, which would imply a 32-bit FPU even for
633 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
634 * FPU emu is slow and bulky and optimizing this function offers fairly
635 * sizeable benefits so we try to be clever and make this function return
636 * a constant whenever possible, that is on 64-bit kernels without O32
637 * compatibility enabled and on 32-bit without 64-bit FPU support.
639 static inline int cop1_64bit(struct pt_regs *xcp)
641 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
643 else if (config_enabled(CONFIG_32BIT) &&
644 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
647 return !test_thread_flag(TIF_32BIT_FPREGS);
650 #define SIFROMREG(si, x) \
652 if (cop1_64bit(xcp)) \
653 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
655 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
658 #define SITOREG(si, x) \
660 if (cop1_64bit(xcp)) { \
662 set_fpr32(&ctx->fpr[x], 0, si); \
663 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
664 set_fpr32(&ctx->fpr[x], i, 0); \
666 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
670 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
672 #define SITOHREG(si, x) \
675 set_fpr32(&ctx->fpr[x], 1, si); \
676 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
677 set_fpr32(&ctx->fpr[x], i, 0); \
680 #define DIFROMREG(di, x) \
681 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
683 #define DITOREG(di, x) \
686 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
687 set_fpr64(&ctx->fpr[fpr], 0, di); \
688 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
689 set_fpr64(&ctx->fpr[fpr], i, 0); \
692 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
693 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
694 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
695 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
698 * Emulate the single floating point instruction pointed at by EPC.
699 * Two instructions if the instruction is in a branch delay slot.
702 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
703 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
705 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
706 unsigned int cond, cbit;
717 * These are giving gcc a gentle hint about what to expect in
718 * dec_inst in order to do better optimization.
720 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
723 /* XXX NEC Vr54xx bug workaround */
724 if (delay_slot(xcp)) {
725 if (dec_insn.micro_mips_mode) {
726 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
727 clear_delay_slot(xcp);
729 if (!isBranchInstr(xcp, dec_insn, &contpc))
730 clear_delay_slot(xcp);
734 if (delay_slot(xcp)) {
736 * The instruction to be emulated is in a branch delay slot
737 * which means that we have to emulate the branch instruction
738 * BEFORE we do the cop1 instruction.
740 * This branch could be a COP1 branch, but in that case we
741 * would have had a trap for that instruction, and would not
742 * come through this route.
744 * Linux MIPS branch emulator operates on context, updating the
747 ir = dec_insn.next_insn; /* process delay slot instr */
748 pc_inc = dec_insn.next_pc_inc;
750 ir = dec_insn.insn; /* process current instr */
751 pc_inc = dec_insn.pc_inc;
755 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
756 * instructions, we want to convert microMIPS FPU instructions
757 * into MIPS32 instructions so that we could reuse all of the
758 * FPU emulation code.
760 * NOTE: We cannot do this for branch instructions since they
761 * are not a subset. Example: Cannot emulate a 16-bit
762 * aligned target address with a MIPS32 instruction.
764 if (dec_insn.micro_mips_mode) {
766 * If next instruction is a 16-bit instruction, then it
767 * it cannot be a FPU instruction. This could happen
768 * since we can be called for non-FPU instructions.
771 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
777 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
778 MIPS_FPU_EMU_INC_STATS(emulated);
779 switch (MIPSInst_OPCODE(ir)) {
781 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
783 MIPS_FPU_EMU_INC_STATS(loads);
785 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
786 MIPS_FPU_EMU_INC_STATS(errors);
790 if (__get_user(dval, dva)) {
791 MIPS_FPU_EMU_INC_STATS(errors);
795 DITOREG(dval, MIPSInst_RT(ir));
799 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
801 MIPS_FPU_EMU_INC_STATS(stores);
802 DIFROMREG(dval, MIPSInst_RT(ir));
803 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
804 MIPS_FPU_EMU_INC_STATS(errors);
808 if (__put_user(dval, dva)) {
809 MIPS_FPU_EMU_INC_STATS(errors);
816 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
818 MIPS_FPU_EMU_INC_STATS(loads);
819 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
820 MIPS_FPU_EMU_INC_STATS(errors);
824 if (__get_user(wval, wva)) {
825 MIPS_FPU_EMU_INC_STATS(errors);
829 SITOREG(wval, MIPSInst_RT(ir));
833 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
835 MIPS_FPU_EMU_INC_STATS(stores);
836 SIFROMREG(wval, MIPSInst_RT(ir));
837 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
838 MIPS_FPU_EMU_INC_STATS(errors);
842 if (__put_user(wval, wva)) {
843 MIPS_FPU_EMU_INC_STATS(errors);
850 switch (MIPSInst_RS(ir)) {
852 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
855 /* copregister fs -> gpr[rt] */
856 if (MIPSInst_RT(ir) != 0) {
857 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
863 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
866 /* copregister fs <- rt */
867 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
871 if (!cpu_has_mips_r2)
874 /* copregister rd -> gpr[rt] */
875 if (MIPSInst_RT(ir) != 0) {
876 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
882 if (!cpu_has_mips_r2)
885 /* copregister rd <- gpr[rt] */
886 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
890 /* copregister rd -> gpr[rt] */
891 if (MIPSInst_RT(ir) != 0) {
892 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
898 /* copregister rd <- rt */
899 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
903 /* cop control register rd -> gpr[rt] */
904 if (MIPSInst_RD(ir) == FPCREG_CSR) {
906 value = (value & ~FPU_CSR_RM) | modeindex(value);
907 pr_debug("%p gpr[%d]<-csr=%08x\n",
908 (void *) (xcp->cp0_epc),
909 MIPSInst_RT(ir), value);
911 else if (MIPSInst_RD(ir) == FPCREG_RID)
916 xcp->regs[MIPSInst_RT(ir)] = value;
920 /* copregister rd <- rt */
921 if (MIPSInst_RT(ir) == 0)
924 value = xcp->regs[MIPSInst_RT(ir)];
926 /* we only have one writable control reg
928 if (MIPSInst_RD(ir) == FPCREG_CSR) {
929 pr_debug("%p gpr[%d]->csr=%08x\n",
930 (void *) (xcp->cp0_epc),
931 MIPSInst_RT(ir), value);
934 * Don't write reserved bits,
935 * and convert to ieee library modes
937 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
940 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
949 if (cpu_has_mips_4_5_r)
950 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
953 cond = ctx->fcr31 & cbit;
956 switch (MIPSInst_RT(ir) & 3) {
967 /* thats an illegal instruction */
974 * Branch taken: emulate dslot instruction
976 xcp->cp0_epc += dec_insn.pc_inc;
978 contpc = MIPSInst_SIMM(ir);
979 ir = dec_insn.next_insn;
980 if (dec_insn.micro_mips_mode) {
981 contpc = (xcp->cp0_epc + (contpc << 1));
983 /* If 16-bit instruction, not FPU. */
984 if ((dec_insn.next_pc_inc == 2) ||
985 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
988 * Since this instruction will
989 * be put on the stack with
990 * 32-bit words, get around
991 * this problem by putting a
992 * NOP16 as the second one.
994 if (dec_insn.next_pc_inc == 2)
995 ir = (ir & (~0xffff)) | MM_NOP16;
998 * Single step the non-CP1
999 * instruction in the dslot.
1001 return mips_dsemul(xcp, ir, contpc);
1004 contpc = (xcp->cp0_epc + (contpc << 2));
1006 switch (MIPSInst_OPCODE(ir)) {
1015 if (cpu_has_mips_2_3_4_5 ||
1026 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1027 /* its one of ours */
1033 if (!cpu_has_mips_4_5_r)
1036 if (MIPSInst_FUNC(ir) == movc_op)
1042 * Single step the non-cp1
1043 * instruction in the dslot
1045 return mips_dsemul(xcp, ir, contpc);
1046 } else if (likely) { /* branch not taken */
1048 * branch likely nullifies
1049 * dslot if not taken
1051 xcp->cp0_epc += dec_insn.pc_inc;
1052 contpc += dec_insn.pc_inc;
1054 * else continue & execute
1055 * dslot as normal insn
1061 if (!(MIPSInst_RS(ir) & 0x10))
1064 /* a real fpu computation instruction */
1065 if ((sig = fpu_emu(xcp, ctx, ir)))
1071 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1074 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1080 if (!cpu_has_mips_4_5_r)
1083 if (MIPSInst_FUNC(ir) != movc_op)
1085 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1086 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1087 xcp->regs[MIPSInst_RD(ir)] =
1088 xcp->regs[MIPSInst_RS(ir)];
1096 xcp->cp0_epc = contpc;
1097 clear_delay_slot(xcp);
1103 * Conversion table from MIPS compare ops 48-63
1104 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1106 static const unsigned char cmptab[8] = {
1107 0, /* cmp_0 (sig) cmp_sf */
1108 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1109 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1110 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1111 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1112 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1113 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1114 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1119 * Additional MIPS4 instructions
1122 #define DEF3OP(name, p, f1, f2, f3) \
1123 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1124 union ieee754##p s, union ieee754##p t) \
1126 struct _ieee754_csr ieee754_csr_save; \
1128 ieee754_csr_save = ieee754_csr; \
1130 ieee754_csr_save.cx |= ieee754_csr.cx; \
1131 ieee754_csr_save.sx |= ieee754_csr.sx; \
1133 ieee754_csr.cx |= ieee754_csr_save.cx; \
1134 ieee754_csr.sx |= ieee754_csr_save.sx; \
1138 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1140 return ieee754dp_div(ieee754dp_one(0), d);
1143 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1145 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1148 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1150 return ieee754sp_div(ieee754sp_one(0), s);
1153 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1155 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1158 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1159 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1160 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1161 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1162 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1163 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1164 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1165 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1167 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1168 mips_instruction ir, void *__user *fault_addr)
1170 unsigned rcsr = 0; /* resulting csr */
1172 MIPS_FPU_EMU_INC_STATS(cp1xops);
1174 switch (MIPSInst_FMA_FFMT(ir)) {
1175 case s_fmt:{ /* 0 */
1177 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1178 union ieee754sp fd, fr, fs, ft;
1182 switch (MIPSInst_FUNC(ir)) {
1184 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1185 xcp->regs[MIPSInst_FT(ir)]);
1187 MIPS_FPU_EMU_INC_STATS(loads);
1188 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1189 MIPS_FPU_EMU_INC_STATS(errors);
1193 if (__get_user(val, va)) {
1194 MIPS_FPU_EMU_INC_STATS(errors);
1198 SITOREG(val, MIPSInst_FD(ir));
1202 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1203 xcp->regs[MIPSInst_FT(ir)]);
1205 MIPS_FPU_EMU_INC_STATS(stores);
1207 SIFROMREG(val, MIPSInst_FS(ir));
1208 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1209 MIPS_FPU_EMU_INC_STATS(errors);
1213 if (put_user(val, va)) {
1214 MIPS_FPU_EMU_INC_STATS(errors);
1221 handler = fpemu_sp_madd;
1224 handler = fpemu_sp_msub;
1227 handler = fpemu_sp_nmadd;
1230 handler = fpemu_sp_nmsub;
1234 SPFROMREG(fr, MIPSInst_FR(ir));
1235 SPFROMREG(fs, MIPSInst_FS(ir));
1236 SPFROMREG(ft, MIPSInst_FT(ir));
1237 fd = (*handler) (fr, fs, ft);
1238 SPTOREG(fd, MIPSInst_FD(ir));
1241 if (ieee754_cxtest(IEEE754_INEXACT)) {
1242 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1243 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1245 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1246 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1247 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1249 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1250 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1251 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1253 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1254 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1255 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1258 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1259 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1260 /*printk ("SIGFPE: FPU csr = %08x\n",
1273 case d_fmt:{ /* 1 */
1274 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1275 union ieee754dp fd, fr, fs, ft;
1279 switch (MIPSInst_FUNC(ir)) {
1281 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1282 xcp->regs[MIPSInst_FT(ir)]);
1284 MIPS_FPU_EMU_INC_STATS(loads);
1285 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1286 MIPS_FPU_EMU_INC_STATS(errors);
1290 if (__get_user(val, va)) {
1291 MIPS_FPU_EMU_INC_STATS(errors);
1295 DITOREG(val, MIPSInst_FD(ir));
1299 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1300 xcp->regs[MIPSInst_FT(ir)]);
1302 MIPS_FPU_EMU_INC_STATS(stores);
1303 DIFROMREG(val, MIPSInst_FS(ir));
1304 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1305 MIPS_FPU_EMU_INC_STATS(errors);
1309 if (__put_user(val, va)) {
1310 MIPS_FPU_EMU_INC_STATS(errors);
1317 handler = fpemu_dp_madd;
1320 handler = fpemu_dp_msub;
1323 handler = fpemu_dp_nmadd;
1326 handler = fpemu_dp_nmsub;
1330 DPFROMREG(fr, MIPSInst_FR(ir));
1331 DPFROMREG(fs, MIPSInst_FS(ir));
1332 DPFROMREG(ft, MIPSInst_FT(ir));
1333 fd = (*handler) (fr, fs, ft);
1334 DPTOREG(fd, MIPSInst_FD(ir));
1344 if (MIPSInst_FUNC(ir) != pfetch_op)
1347 /* ignore prefx operation */
1360 * Emulate a single COP1 arithmetic instruction.
1362 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1363 mips_instruction ir)
1365 int rfmt; /* resulting format */
1366 unsigned rcsr = 0; /* resulting csr */
1375 } rv; /* resulting value */
1378 MIPS_FPU_EMU_INC_STATS(cp1ops);
1379 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1380 case s_fmt: { /* 0 */
1382 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1383 union ieee754sp(*u) (union ieee754sp);
1385 union ieee754sp fs, ft;
1387 switch (MIPSInst_FUNC(ir)) {
1390 handler.b = ieee754sp_add;
1393 handler.b = ieee754sp_sub;
1396 handler.b = ieee754sp_mul;
1399 handler.b = ieee754sp_div;
1404 if (!cpu_has_mips_4_5_r)
1407 handler.u = ieee754sp_sqrt;
1411 * Note that on some MIPS IV implementations such as the
1412 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1413 * achieve full IEEE-754 accuracy - however this emulator does.
1416 if (!cpu_has_mips_4_5_r2)
1419 handler.u = fpemu_sp_rsqrt;
1423 if (!cpu_has_mips_4_5_r2)
1426 handler.u = fpemu_sp_recip;
1430 if (!cpu_has_mips_4_5_r)
1433 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1434 if (((ctx->fcr31 & cond) != 0) !=
1435 ((MIPSInst_FT(ir) & 1) != 0))
1437 SPFROMREG(rv.s, MIPSInst_FS(ir));
1441 if (!cpu_has_mips_4_5_r)
1444 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1446 SPFROMREG(rv.s, MIPSInst_FS(ir));
1450 if (!cpu_has_mips_4_5_r)
1453 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1455 SPFROMREG(rv.s, MIPSInst_FS(ir));
1459 handler.u = ieee754sp_abs;
1463 handler.u = ieee754sp_neg;
1468 SPFROMREG(rv.s, MIPSInst_FS(ir));
1471 /* binary op on handler */
1473 SPFROMREG(fs, MIPSInst_FS(ir));
1474 SPFROMREG(ft, MIPSInst_FT(ir));
1476 rv.s = (*handler.b) (fs, ft);
1479 SPFROMREG(fs, MIPSInst_FS(ir));
1480 rv.s = (*handler.u) (fs);
1483 if (ieee754_cxtest(IEEE754_INEXACT)) {
1484 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1485 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1487 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1488 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1489 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1491 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1492 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1493 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1495 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1496 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1497 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1499 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1500 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1501 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1505 /* unary conv ops */
1507 return SIGILL; /* not defined */
1510 SPFROMREG(fs, MIPSInst_FS(ir));
1511 rv.d = ieee754dp_fsp(fs);
1516 SPFROMREG(fs, MIPSInst_FS(ir));
1517 rv.w = ieee754sp_tint(fs);
1525 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64)
1528 oldrm = ieee754_csr.rm;
1529 SPFROMREG(fs, MIPSInst_FS(ir));
1530 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1531 rv.w = ieee754sp_tint(fs);
1532 ieee754_csr.rm = oldrm;
1537 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1540 SPFROMREG(fs, MIPSInst_FS(ir));
1541 rv.l = ieee754sp_tlong(fs);
1549 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1552 oldrm = ieee754_csr.rm;
1553 SPFROMREG(fs, MIPSInst_FS(ir));
1554 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1555 rv.l = ieee754sp_tlong(fs);
1556 ieee754_csr.rm = oldrm;
1561 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1562 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1563 union ieee754sp fs, ft;
1565 SPFROMREG(fs, MIPSInst_FS(ir));
1566 SPFROMREG(ft, MIPSInst_FT(ir));
1567 rv.w = ieee754sp_cmp(fs, ft,
1568 cmptab[cmpop & 0x7], cmpop & 0x8);
1570 if ((cmpop & 0x8) && ieee754_cxtest
1571 (IEEE754_INVALID_OPERATION))
1572 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1584 union ieee754dp fs, ft;
1586 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1587 union ieee754dp(*u) (union ieee754dp);
1590 switch (MIPSInst_FUNC(ir)) {
1593 handler.b = ieee754dp_add;
1596 handler.b = ieee754dp_sub;
1599 handler.b = ieee754dp_mul;
1602 handler.b = ieee754dp_div;
1607 if (!cpu_has_mips_2_3_4_5_r)
1610 handler.u = ieee754dp_sqrt;
1613 * Note that on some MIPS IV implementations such as the
1614 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1615 * achieve full IEEE-754 accuracy - however this emulator does.
1618 if (!cpu_has_mips_4_5_r2)
1621 handler.u = fpemu_dp_rsqrt;
1624 if (!cpu_has_mips_4_5_r2)
1627 handler.u = fpemu_dp_recip;
1630 if (!cpu_has_mips_4_5_r)
1633 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1634 if (((ctx->fcr31 & cond) != 0) !=
1635 ((MIPSInst_FT(ir) & 1) != 0))
1637 DPFROMREG(rv.d, MIPSInst_FS(ir));
1640 if (!cpu_has_mips_4_5_r)
1643 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1645 DPFROMREG(rv.d, MIPSInst_FS(ir));
1648 if (!cpu_has_mips_4_5_r)
1651 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1653 DPFROMREG(rv.d, MIPSInst_FS(ir));
1656 handler.u = ieee754dp_abs;
1660 handler.u = ieee754dp_neg;
1665 DPFROMREG(rv.d, MIPSInst_FS(ir));
1668 /* binary op on handler */
1670 DPFROMREG(fs, MIPSInst_FS(ir));
1671 DPFROMREG(ft, MIPSInst_FT(ir));
1673 rv.d = (*handler.b) (fs, ft);
1676 DPFROMREG(fs, MIPSInst_FS(ir));
1677 rv.d = (*handler.u) (fs);
1684 DPFROMREG(fs, MIPSInst_FS(ir));
1685 rv.s = ieee754sp_fdp(fs);
1690 return SIGILL; /* not defined */
1693 DPFROMREG(fs, MIPSInst_FS(ir));
1694 rv.w = ieee754dp_tint(fs); /* wrong */
1702 if (!cpu_has_mips_2_3_4_5_r)
1705 oldrm = ieee754_csr.rm;
1706 DPFROMREG(fs, MIPSInst_FS(ir));
1707 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1708 rv.w = ieee754dp_tint(fs);
1709 ieee754_csr.rm = oldrm;
1714 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1717 DPFROMREG(fs, MIPSInst_FS(ir));
1718 rv.l = ieee754dp_tlong(fs);
1726 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1729 oldrm = ieee754_csr.rm;
1730 DPFROMREG(fs, MIPSInst_FS(ir));
1731 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1732 rv.l = ieee754dp_tlong(fs);
1733 ieee754_csr.rm = oldrm;
1738 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1739 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1740 union ieee754dp fs, ft;
1742 DPFROMREG(fs, MIPSInst_FS(ir));
1743 DPFROMREG(ft, MIPSInst_FT(ir));
1744 rv.w = ieee754dp_cmp(fs, ft,
1745 cmptab[cmpop & 0x7], cmpop & 0x8);
1750 (IEEE754_INVALID_OPERATION))
1751 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1764 switch (MIPSInst_FUNC(ir)) {
1766 /* convert word to single precision real */
1767 SPFROMREG(fs, MIPSInst_FS(ir));
1768 rv.s = ieee754sp_fint(fs.bits);
1772 /* convert word to double precision real */
1773 SPFROMREG(fs, MIPSInst_FS(ir));
1774 rv.d = ieee754dp_fint(fs.bits);
1785 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1788 DIFROMREG(bits, MIPSInst_FS(ir));
1790 switch (MIPSInst_FUNC(ir)) {
1792 /* convert long to single precision real */
1793 rv.s = ieee754sp_flong(bits);
1797 /* convert long to double precision real */
1798 rv.d = ieee754dp_flong(bits);
1811 * Update the fpu CSR register for this operation.
1812 * If an exception is required, generate a tidy SIGFPE exception,
1813 * without updating the result register.
1814 * Note: cause exception bits do not accumulate, they are rewritten
1815 * for each op; only the flag/sticky bits accumulate.
1817 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1818 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1819 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
1824 * Now we can safely write the result back to the register file.
1829 if (cpu_has_mips_4_5_r)
1830 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
1832 cbit = FPU_CSR_COND;
1836 ctx->fcr31 &= ~cbit;
1840 DPTOREG(rv.d, MIPSInst_FD(ir));
1843 SPTOREG(rv.s, MIPSInst_FD(ir));
1846 SITOREG(rv.w, MIPSInst_FD(ir));
1849 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1852 DITOREG(rv.l, MIPSInst_FD(ir));
1861 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1862 int has_fpu, void *__user *fault_addr)
1864 unsigned long oldepc, prevepc;
1865 struct mm_decoded_insn dec_insn;
1870 oldepc = xcp->cp0_epc;
1872 prevepc = xcp->cp0_epc;
1874 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
1876 * Get next 2 microMIPS instructions and convert them
1877 * into 32-bit instructions.
1879 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
1880 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
1881 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
1882 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
1883 MIPS_FPU_EMU_INC_STATS(errors);
1888 /* Get first instruction. */
1889 if (mm_insn_16bit(*instr_ptr)) {
1890 /* Duplicate the half-word. */
1891 dec_insn.insn = (*instr_ptr << 16) |
1893 /* 16-bit instruction. */
1894 dec_insn.pc_inc = 2;
1897 dec_insn.insn = (*instr_ptr << 16) |
1899 /* 32-bit instruction. */
1900 dec_insn.pc_inc = 4;
1903 /* Get second instruction. */
1904 if (mm_insn_16bit(*instr_ptr)) {
1905 /* Duplicate the half-word. */
1906 dec_insn.next_insn = (*instr_ptr << 16) |
1908 /* 16-bit instruction. */
1909 dec_insn.next_pc_inc = 2;
1911 dec_insn.next_insn = (*instr_ptr << 16) |
1913 /* 32-bit instruction. */
1914 dec_insn.next_pc_inc = 4;
1916 dec_insn.micro_mips_mode = 1;
1918 if ((get_user(dec_insn.insn,
1919 (mips_instruction __user *) xcp->cp0_epc)) ||
1920 (get_user(dec_insn.next_insn,
1921 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
1922 MIPS_FPU_EMU_INC_STATS(errors);
1925 dec_insn.pc_inc = 4;
1926 dec_insn.next_pc_inc = 4;
1927 dec_insn.micro_mips_mode = 0;
1930 if ((dec_insn.insn == 0) ||
1931 ((dec_insn.pc_inc == 2) &&
1932 ((dec_insn.insn & 0xffff) == MM_NOP16)))
1933 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1936 * The 'ieee754_csr' is an alias of
1937 * ctx->fcr31. No need to copy ctx->fcr31 to
1938 * ieee754_csr. But ieee754_csr.rm is ieee
1939 * library modes. (not mips rounding mode)
1941 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1950 } while (xcp->cp0_epc > prevepc);
1952 /* SIGILL indicates a non-fpu instruction */
1953 if (sig == SIGILL && xcp->cp0_epc != oldepc)
1954 /* but if EPC has advanced, then ignore it */