arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/mm.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/bcache.h>
  18 #include <asm/bootinfo.h>
  19 #include <asm/cacheops.h>
  20 #include <asm/cpu.h>
  21 #include <asm/cpu-features.h>
  22 #include <asm/io.h>
  23 #include <asm/page.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/r4kcache.h>
  26 #include <asm/system.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/war.h>
  29
  30 static unsigned long icache_size, dcache_size, scache_size;
  31
  32 /*
  33  * Dummy cache handling routines for machines without boardcaches
  34  */
  35 static void no_sc_noop(void) {}
  36
  37 static struct bcache_ops no_sc_ops = {
  38         .bc_enable = (void *)no_sc_noop,
  39         .bc_disable = (void *)no_sc_noop,
  40         .bc_wback_inv = (void *)no_sc_noop,
  41         .bc_inv = (void *)no_sc_noop
  42 };
  43
  44 struct bcache_ops *bcops = &no_sc_ops;
  45
  46 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x2010)
  47 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x2020)
  48
  49 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  50 do {                                                                    \
  51         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  52                 *(volatile unsigned long *)CKSEG1;                      \
  53         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  54                 __asm__ __volatile__("nop;nop;nop;nop");                \
  55 } while (0)
  56
  57 static void (*r4k_blast_dcache_page)(unsigned long addr);
  58
  59 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
  60 {
  61         R4600_HIT_CACHEOP_WAR_IMPL;
  62         blast_dcache32_page(addr);
  63 }
  64
  65 static inline void r4k_blast_dcache_page_setup(void)
  66 {
  67         unsigned long  dc_lsize = cpu_dcache_line_size();
  68
  69         if (dc_lsize == 16)
  70                 r4k_blast_dcache_page = blast_dcache16_page;
  71         else if (dc_lsize == 32)
  72                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
  73 }
  74
  75 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
  76
  77 static inline void r4k_blast_dcache_page_indexed_setup(void)
  78 {
  79         unsigned long dc_lsize = cpu_dcache_line_size();
  80
  81         if (dc_lsize == 16)
  82                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  83         else if (dc_lsize == 32)
  84                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
  85 }
  86
  87 static void (* r4k_blast_dcache)(void);
  88
  89 static inline void r4k_blast_dcache_setup(void)
  90 {
  91         unsigned long dc_lsize = cpu_dcache_line_size();
  92
  93         if (dc_lsize == 16)
  94                 r4k_blast_dcache = blast_dcache16;
  95         else if (dc_lsize == 32)
  96                 r4k_blast_dcache = blast_dcache32;
  97 }
  98
  99 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 100 #define JUMP_TO_ALIGN(order) \
 101         __asm__ __volatile__( \
 102                 "b\t1f\n\t" \
 103                 ".align\t" #order "\n\t" \
 104                 "1:\n\t" \
 105                 )
 106 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 107 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 108
 109 static inline void blast_r4600_v1_icache32(void)
 110 {
 111         unsigned long flags;
 112
 113         local_irq_save(flags);
 114         blast_icache32();
 115         local_irq_restore(flags);
 116 }
 117
 118 static inline void tx49_blast_icache32(void)
 119 {
 120         unsigned long start = INDEX_BASE;
 121         unsigned long end = start + current_cpu_data.icache.waysize;
 122         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 123         unsigned long ws_end = current_cpu_data.icache.ways <<
 124                                current_cpu_data.icache.waybit;
 125         unsigned long ws, addr;
 126
 127         CACHE32_UNROLL32_ALIGN2;
 128         /* I'm in even chunk.  blast odd chunks */
 129         for (ws = 0; ws < ws_end; ws += ws_inc)
 130                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 131                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 132         CACHE32_UNROLL32_ALIGN;
 133         /* I'm in odd chunk.  blast even chunks */
 134         for (ws = 0; ws < ws_end; ws += ws_inc)
 135                 for (addr = start; addr < end; addr += 0x400 * 2)
 136                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 137 }
 138
 139 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 140 {
 141         unsigned long flags;
 142
 143         local_irq_save(flags);
 144         blast_icache32_page_indexed(page);
 145         local_irq_restore(flags);
 146 }
 147
 148 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 149 {
 150         unsigned long start = page;
 151         unsigned long end = start + PAGE_SIZE;
 152         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 153         unsigned long ws_end = current_cpu_data.icache.ways <<
 154                                current_cpu_data.icache.waybit;
 155         unsigned long ws, addr;
 156
 157         CACHE32_UNROLL32_ALIGN2;
 158         /* I'm in even chunk.  blast odd chunks */
 159         for (ws = 0; ws < ws_end; ws += ws_inc)
 160                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 161                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 162         CACHE32_UNROLL32_ALIGN;
 163         /* I'm in odd chunk.  blast even chunks */
 164         for (ws = 0; ws < ws_end; ws += ws_inc)
 165                 for (addr = start; addr < end; addr += 0x400 * 2)
 166                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 167 }
 168
 169 static void (* r4k_blast_icache_page)(unsigned long addr);
 170
 171 static inline void r4k_blast_icache_page_setup(void)
 172 {
 173         unsigned long ic_lsize = cpu_icache_line_size();
 174
 175         if (ic_lsize == 16)
 176                 r4k_blast_icache_page = blast_icache16_page;
 177         else if (ic_lsize == 32)
 178                 r4k_blast_icache_page = blast_icache32_page;
 179         else if (ic_lsize == 64)
 180                 r4k_blast_icache_page = blast_icache64_page;
 181 }
 182
 183
 184 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 185
 186 static inline void r4k_blast_icache_page_indexed_setup(void)
 187 {
 188         unsigned long ic_lsize = cpu_icache_line_size();
 189
 190         if (ic_lsize == 16)
 191                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 192         else if (ic_lsize == 32) {
 193                 if (TX49XX_ICACHE_INDEX_INV_WAR)
 194                         r4k_blast_icache_page_indexed =
 195                                 tx49_blast_icache32_page_indexed;
 196                 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 197                         r4k_blast_icache_page_indexed =
 198                                 blast_icache32_r4600_v1_page_indexed;
 199                 else
 200                         r4k_blast_icache_page_indexed =
 201                                 blast_icache32_page_indexed;
 202         } else if (ic_lsize == 64)
 203                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 204 }
 205
 206 static void (* r4k_blast_icache)(void);
 207
 208 static inline void r4k_blast_icache_setup(void)
 209 {
 210         unsigned long ic_lsize = cpu_icache_line_size();
 211
 212         if (ic_lsize == 16)
 213                 r4k_blast_icache = blast_icache16;
 214         else if (ic_lsize == 32) {
 215                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 216                         r4k_blast_icache = blast_r4600_v1_icache32;
 217                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 218                         r4k_blast_icache = tx49_blast_icache32;
 219                 else
 220                         r4k_blast_icache = blast_icache32;
 221         } else if (ic_lsize == 64)
 222                 r4k_blast_icache = blast_icache64;
 223 }
 224
 225 static void (* r4k_blast_scache_page)(unsigned long addr);
 226
 227 static inline void r4k_blast_scache_page_setup(void)
 228 {
 229         unsigned long sc_lsize = cpu_scache_line_size();
 230
 231         if (sc_lsize == 16)
 232                 r4k_blast_scache_page = blast_scache16_page;
 233         else if (sc_lsize == 32)
 234                 r4k_blast_scache_page = blast_scache32_page;
 235         else if (sc_lsize == 64)
 236                 r4k_blast_scache_page = blast_scache64_page;
 237         else if (sc_lsize == 128)
 238                 r4k_blast_scache_page = blast_scache128_page;
 239 }
 240
 241 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 242
 243 static inline void r4k_blast_scache_page_indexed_setup(void)
 244 {
 245         unsigned long sc_lsize = cpu_scache_line_size();
 246
 247         if (sc_lsize == 16)
 248                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 249         else if (sc_lsize == 32)
 250                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 251         else if (sc_lsize == 64)
 252                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 253         else if (sc_lsize == 128)
 254                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 255 }
 256
 257 static void (* r4k_blast_scache)(void);
 258
 259 static inline void r4k_blast_scache_setup(void)
 260 {
 261         unsigned long sc_lsize = cpu_scache_line_size();
 262
 263         if (sc_lsize == 16)
 264                 r4k_blast_scache = blast_scache16;
 265         else if (sc_lsize == 32)
 266                 r4k_blast_scache = blast_scache32;
 267         else if (sc_lsize == 64)
 268                 r4k_blast_scache = blast_scache64;
 269         else if (sc_lsize == 128)
 270                 r4k_blast_scache = blast_scache128;
 271 }
 272
 273 /*
 274  * This is former mm's flush_cache_all() which really should be
 275  * flush_cache_vunmap these days ...
 276  */
 277 static inline void local_r4k_flush_cache_all(void * args)
 278 {
 279         r4k_blast_dcache();
 280         r4k_blast_icache();
 281 }
 282
 283 static void r4k_flush_cache_all(void)
 284 {
 285         if (!cpu_has_dc_aliases)
 286                 return;
 287
 288         on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
 289 }
 290
 291 static inline void local_r4k___flush_cache_all(void * args)
 292 {
 293         r4k_blast_dcache();
 294         r4k_blast_icache();
 295
 296         switch (current_cpu_data.cputype) {
 297         case CPU_R4000SC:
 298         case CPU_R4000MC:
 299         case CPU_R4400SC:
 300         case CPU_R4400MC:
 301         case CPU_R10000:
 302         case CPU_R12000:
 303                 r4k_blast_scache();
 304         }
 305 }
 306
 307 static void r4k___flush_cache_all(void)
 308 {
 309         on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
 310 }
 311
 312 static inline void local_r4k_flush_cache_range(void * args)
 313 {
 314         struct vm_area_struct *vma = args;
 315         int exec;
 316
 317         if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
 318                 return;
 319
 320         exec = vma->vm_flags & VM_EXEC;
 321         if (cpu_has_dc_aliases || exec)
 322                 r4k_blast_dcache();
 323         if (exec)
 324                 r4k_blast_icache();
 325 }
 326
 327 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 328         unsigned long start, unsigned long end)
 329 {
 330         on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
 331 }
 332
 333 static inline void local_r4k_flush_cache_mm(void * args)
 334 {
 335         struct mm_struct *mm = args;
 336
 337         if (!cpu_context(smp_processor_id(), mm))
 338                 return;
 339
 340         r4k_blast_dcache();
 341         r4k_blast_icache();
 342
 343         /*
 344          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 345          * only flush the primary caches but R10000 and R12000 behave sane ...
 346          */
 347         if (current_cpu_data.cputype == CPU_R4000SC ||
 348             current_cpu_data.cputype == CPU_R4000MC ||
 349             current_cpu_data.cputype == CPU_R4400SC ||
 350             current_cpu_data.cputype == CPU_R4400MC)
 351                 r4k_blast_scache();
 352 }
 353
 354 static void r4k_flush_cache_mm(struct mm_struct *mm)
 355 {
 356         if (!cpu_has_dc_aliases)
 357                 return;
 358
 359         on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
 360 }
 361
 362 struct flush_cache_page_args {
 363         struct vm_area_struct *vma;
 364         unsigned long page;
 365 };
 366
 367 static inline void local_r4k_flush_cache_page(void *args)
 368 {
 369         struct flush_cache_page_args *fcp_args = args;
 370         struct vm_area_struct *vma = fcp_args->vma;
 371         unsigned long page = fcp_args->page;
 372         int exec = vma->vm_flags & VM_EXEC;
 373         struct mm_struct *mm = vma->vm_mm;
 374         pgd_t *pgdp;
 375         pud_t *pudp;
 376         pmd_t *pmdp;
 377         pte_t *ptep;
 378
 379         /*
 380          * If ownes no valid ASID yet, cannot possibly have gotten
 381          * this page into the cache.
 382          */
 383         if (cpu_context(smp_processor_id(), mm) == 0)
 384                 return;
 385
 386         page &= PAGE_MASK;
 387         pgdp = pgd_offset(mm, page);
 388         pudp = pud_offset(pgdp, page);
 389         pmdp = pmd_offset(pudp, page);
 390         ptep = pte_offset(pmdp, page);
 391
 392         /*
 393          * If the page isn't marked valid, the page cannot possibly be
 394          * in the cache.
 395          */
 396         if (!(pte_val(*ptep) & _PAGE_PRESENT))
 397                 return;
 398
 399         /*
 400          * Doing flushes for another ASID than the current one is
 401          * too difficult since stupid R4k caches do a TLB translation
 402          * for every cache flush operation.  So we do indexed flushes
 403          * in that case, which doesn't overly flush the cache too much.
 404          */
 405         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
 406                 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 407                         r4k_blast_dcache_page(page);
 408                         if (exec && !cpu_icache_snoops_remote_store)
 409                                 r4k_blast_scache_page(page);
 410                 }
 411                 if (exec)
 412                         r4k_blast_icache_page(page);
 413
 414                 return;
 415         }
 416
 417         /*
 418          * Do indexed flush, too much work to get the (possible) TLB refills
 419          * to work correctly.
 420          */
 421         page = INDEX_BASE + (page & (dcache_size - 1));
 422         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 423                 r4k_blast_dcache_page_indexed(page);
 424                 if (exec && !cpu_icache_snoops_remote_store)
 425                         r4k_blast_scache_page_indexed(page);
 426         }
 427         if (exec) {
 428                 if (cpu_has_vtag_icache) {
 429                         int cpu = smp_processor_id();
 430
 431                         if (cpu_context(cpu, mm) != 0)
 432                                 drop_mmu_context(mm, cpu);
 433                 } else
 434                         r4k_blast_icache_page_indexed(page);
 435         }
 436 }
 437
 438 static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
 439 {
 440         struct flush_cache_page_args args;
 441
 442         args.vma = vma;
 443         args.page = page;
 444
 445         on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
 446 }
 447
 448 static inline void local_r4k_flush_data_cache_page(void * addr)
 449 {
 450         r4k_blast_dcache_page((unsigned long) addr);
 451 }
 452
 453 static void r4k_flush_data_cache_page(unsigned long addr)
 454 {
 455         on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
 456 }
 457
 458 struct flush_icache_range_args {
 459         unsigned long start;
 460         unsigned long end;
 461 };
 462
 463 static inline void local_r4k_flush_icache_range(void *args)
 464 {
 465         struct flush_icache_range_args *fir_args = args;
 466         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 467         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 468         unsigned long sc_lsize = current_cpu_data.scache.linesz;
 469         unsigned long start = fir_args->start;
 470         unsigned long end = fir_args->end;
 471         unsigned long addr, aend;
 472
 473         if (!cpu_has_ic_fills_f_dc) {
 474                 if (end - start > dcache_size) {
 475                         r4k_blast_dcache();
 476                 } else {
 477                         addr = start & ~(dc_lsize - 1);
 478                         aend = (end - 1) & ~(dc_lsize - 1);
 479
 480                         while (1) {
 481                                 /* Hit_Writeback_Inv_D */
 482                                 protected_writeback_dcache_line(addr);
 483                                 if (addr == aend)
 484                                         break;
 485                                 addr += dc_lsize;
 486                         }
 487                 }
 488
 489                 if (!cpu_icache_snoops_remote_store) {
 490                         if (end - start > scache_size) {
 491                                 r4k_blast_scache();
 492                         } else {
 493                                 addr = start & ~(sc_lsize - 1);
 494                                 aend = (end - 1) & ~(sc_lsize - 1);
 495
 496                                 while (1) {
 497                                         /* Hit_Writeback_Inv_D */
 498                                         protected_writeback_scache_line(addr);
 499                                         if (addr == aend)
 500                                                 break;
 501                                         addr += sc_lsize;
 502                                 }
 503                         }
 504                 }
 505         }
 506
 507         if (end - start > icache_size)
 508                 r4k_blast_icache();
 509         else {
 510                 addr = start & ~(ic_lsize - 1);
 511                 aend = (end - 1) & ~(ic_lsize - 1);
 512                 while (1) {
 513                         /* Hit_Invalidate_I */
 514                         protected_flush_icache_line(addr);
 515                         if (addr == aend)
 516                                 break;
 517                         addr += ic_lsize;
 518                 }
 519         }
 520 }
 521
 522 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 523 {
 524         struct flush_icache_range_args args;
 525
 526         args.start = start;
 527         args.end = end;
 528
 529         on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
 530 }
 531
 532 /*
 533  * Ok, this seriously sucks.  We use them to flush a user page but don't
 534  * know the virtual address, so we have to blast away the whole icache
 535  * which is significantly more expensive than the real thing.  Otoh we at
 536  * least know the kernel address of the page so we can flush it
 537  * selectivly.
 538  */
 539
 540 struct flush_icache_page_args {
 541         struct vm_area_struct *vma;
 542         struct page *page;
 543 };
 544
 545 static inline void local_r4k_flush_icache_page(void *args)
 546 {
 547         struct flush_icache_page_args *fip_args = args;
 548         struct vm_area_struct *vma = fip_args->vma;
 549         struct page *page = fip_args->page;
 550
 551         /*
 552          * Tricky ...  Because we don't know the virtual address we've got the
 553          * choice of either invalidating the entire primary and secondary
 554          * caches or invalidating the secondary caches also.  With the subset
 555          * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
 556          * secondary cache will result in any entries in the primary caches
 557          * also getting invalidated which hopefully is a bit more economical.
 558          */
 559         if (cpu_has_subset_pcaches) {
 560                 unsigned long addr = (unsigned long) page_address(page);
 561
 562                 r4k_blast_scache_page(addr);
 563                 ClearPageDcacheDirty(page);
 564
 565                 return;
 566         }
 567
 568         if (!cpu_has_ic_fills_f_dc) {
 569                 unsigned long addr = (unsigned long) page_address(page);
 570                 r4k_blast_dcache_page(addr);
 571                 if (!cpu_icache_snoops_remote_store)
 572                         r4k_blast_scache_page(addr);
 573                 ClearPageDcacheDirty(page);
 574         }
 575
 576         /*
 577          * We're not sure of the virtual address(es) involved here, so
 578          * we have to flush the entire I-cache.
 579          */
 580         if (cpu_has_vtag_icache) {
 581                 int cpu = smp_processor_id();
 582
 583                 if (cpu_context(cpu, vma->vm_mm) != 0)
 584                         drop_mmu_context(vma->vm_mm, cpu);
 585         } else
 586                 r4k_blast_icache();
 587 }
 588
 589 static void r4k_flush_icache_page(struct vm_area_struct *vma,
 590         struct page *page)
 591 {
 592         struct flush_icache_page_args args;
 593
 594         /*
 595          * If there's no context yet, or the page isn't executable, no I-cache
 596          * flush is needed.
 597          */
 598         if (!(vma->vm_flags & VM_EXEC))
 599                 return;
 600
 601         args.vma = vma;
 602         args.page = page;
 603
 604         on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
 605 }
 606
 607
 608 #ifdef CONFIG_DMA_NONCOHERENT
 609
 610 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 611 {
 612         unsigned long end, a;
 613
 614         /* Catch bad driver code */
 615         BUG_ON(size == 0);
 616
 617         if (cpu_has_subset_pcaches) {
 618                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 619
 620                 if (size >= scache_size) {
 621                         r4k_blast_scache();
 622                         return;
 623                 }
 624
 625                 a = addr & ~(sc_lsize - 1);
 626                 end = (addr + size - 1) & ~(sc_lsize - 1);
 627                 while (1) {
 628                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 629                         if (a == end)
 630                                 break;
 631                         a += sc_lsize;
 632                 }
 633                 return;
 634         }
 635
 636         /*
 637          * Either no secondary cache or the available caches don't have the
 638          * subset property so we have to flush the primary caches
 639          * explicitly
 640          */
 641         if (size >= dcache_size) {
 642                 r4k_blast_dcache();
 643         } else {
 644                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 645
 646                 R4600_HIT_CACHEOP_WAR_IMPL;
 647                 a = addr & ~(dc_lsize - 1);
 648                 end = (addr + size - 1) & ~(dc_lsize - 1);
 649                 while (1) {
 650                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 651                         if (a == end)
 652                                 break;
 653                         a += dc_lsize;
 654                 }
 655         }
 656
 657         bc_wback_inv(addr, size);
 658 }
 659
 660 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 661 {
 662         unsigned long end, a;
 663
 664         /* Catch bad driver code */
 665         BUG_ON(size == 0);
 666
 667         if (cpu_has_subset_pcaches) {
 668                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 669
 670                 if (size >= scache_size) {
 671                         r4k_blast_scache();
 672                         return;
 673                 }
 674
 675                 a = addr & ~(sc_lsize - 1);
 676                 end = (addr + size - 1) & ~(sc_lsize - 1);
 677                 while (1) {
 678                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 679                         if (a == end)
 680                                 break;
 681                         a += sc_lsize;
 682                 }
 683                 return;
 684         }
 685
 686         if (size >= dcache_size) {
 687                 r4k_blast_dcache();
 688         } else {
 689                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 690
 691                 R4600_HIT_CACHEOP_WAR_IMPL;
 692                 a = addr & ~(dc_lsize - 1);
 693                 end = (addr + size - 1) & ~(dc_lsize - 1);
 694                 while (1) {
 695                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 696                         if (a == end)
 697                                 break;
 698                         a += dc_lsize;
 699                 }
 700         }
 701
 702         bc_inv(addr, size);
 703 }
 704 #endif /* CONFIG_DMA_NONCOHERENT */
 705
 706 /*
 707  * While we're protected against bad userland addresses we don't care
 708  * very much about what happens in that case.  Usually a segmentation
 709  * fault will dump the process later on anyway ...
 710  */
 711 static void local_r4k_flush_cache_sigtramp(void * arg)
 712 {
 713         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 714         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 715         unsigned long sc_lsize = current_cpu_data.scache.linesz;
 716         unsigned long addr = (unsigned long) arg;
 717
 718         R4600_HIT_CACHEOP_WAR_IMPL;
 719         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 720         if (!cpu_icache_snoops_remote_store)
 721                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 722         protected_flush_icache_line(addr & ~(ic_lsize - 1));
 723         if (MIPS4K_ICACHE_REFILL_WAR) {
 724                 __asm__ __volatile__ (
 725                         ".set push\n\t"
 726                         ".set noat\n\t"
 727                         ".set mips3\n\t"
 728 #ifdef CONFIG_32BIT
 729                         "la     $at,1f\n\t"
 730 #endif
 731 #ifdef CONFIG_64BIT
 732                         "dla    $at,1f\n\t"
 733 #endif
 734                         "cache  %0,($at)\n\t"
 735                         "nop; nop; nop\n"
 736                         "1:\n\t"
 737                         ".set pop"
 738                         :
 739                         : "i" (Hit_Invalidate_I));
 740         }
 741         if (MIPS_CACHE_SYNC_WAR)
 742                 __asm__ __volatile__ ("sync");
 743 }
 744
 745 static void r4k_flush_cache_sigtramp(unsigned long addr)
 746 {
 747         on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
 748 }
 749
 750 static void r4k_flush_icache_all(void)
 751 {
 752         if (cpu_has_vtag_icache)
 753                 r4k_blast_icache();
 754 }
 755
 756 static inline void rm7k_erratum31(void)
 757 {
 758         const unsigned long ic_lsize = 32;
 759         unsigned long addr;
 760
 761         /* RM7000 erratum #31. The icache is screwed at startup. */
 762         write_c0_taglo(0);
 763         write_c0_taghi(0);
 764
 765         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 766                 __asm__ __volatile__ (
 767                         ".set noreorder\n\t"
 768                         ".set mips3\n\t"
 769                         "cache\t%1, 0(%0)\n\t"
 770                         "cache\t%1, 0x1000(%0)\n\t"
 771                         "cache\t%1, 0x2000(%0)\n\t"
 772                         "cache\t%1, 0x3000(%0)\n\t"
 773                         "cache\t%2, 0(%0)\n\t"
 774                         "cache\t%2, 0x1000(%0)\n\t"
 775                         "cache\t%2, 0x2000(%0)\n\t"
 776                         "cache\t%2, 0x3000(%0)\n\t"
 777                         "cache\t%1, 0(%0)\n\t"
 778                         "cache\t%1, 0x1000(%0)\n\t"
 779                         "cache\t%1, 0x2000(%0)\n\t"
 780                         "cache\t%1, 0x3000(%0)\n\t"
 781                         ".set\tmips0\n\t"
 782                         ".set\treorder\n\t"
 783                         :
 784                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 785         }
 786 }
 787
 788 static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
 789         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 790 };
 791
 792 static void __init probe_pcache(void)
 793 {
 794         struct cpuinfo_mips *c = &current_cpu_data;
 795         unsigned int config = read_c0_config();
 796         unsigned int prid = read_c0_prid();
 797         unsigned long config1;
 798         unsigned int lsize;
 799
 800         switch (c->cputype) {
 801         case CPU_R4600:                 /* QED style two way caches? */
 802         case CPU_R4700:
 803         case CPU_R5000:
 804         case CPU_NEVADA:
 805                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 806                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 807                 c->icache.ways = 2;
 808                 c->icache.waybit = ffs(icache_size/2) - 1;
 809
 810                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 811                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 812                 c->dcache.ways = 2;
 813                 c->dcache.waybit= ffs(dcache_size/2) - 1;
 814
 815                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 816                 break;
 817
 818         case CPU_R5432:
 819         case CPU_R5500:
 820                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 821                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 822                 c->icache.ways = 2;
 823                 c->icache.waybit= 0;
 824
 825                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 826                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 827                 c->dcache.ways = 2;
 828                 c->dcache.waybit = 0;
 829
 830                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 831                 break;
 832
 833         case CPU_TX49XX:
 834                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 835                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 836                 c->icache.ways = 4;
 837                 c->icache.waybit= 0;
 838
 839                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 840                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 841                 c->dcache.ways = 4;
 842                 c->dcache.waybit = 0;
 843
 844                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 845                 break;
 846
 847         case CPU_R4000PC:
 848         case CPU_R4000SC:
 849         case CPU_R4000MC:
 850         case CPU_R4400PC:
 851         case CPU_R4400SC:
 852         case CPU_R4400MC:
 853         case CPU_R4300:
 854                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 855                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 856                 c->icache.ways = 1;
 857                 c->icache.waybit = 0;   /* doesn't matter */
 858
 859                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 860                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 861                 c->dcache.ways = 1;
 862                 c->dcache.waybit = 0;   /* does not matter */
 863
 864                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 865                 break;
 866
 867         case CPU_R10000:
 868         case CPU_R12000:
 869                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 870                 c->icache.linesz = 64;
 871                 c->icache.ways = 2;
 872                 c->icache.waybit = 0;
 873
 874                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 875                 c->dcache.linesz = 32;
 876                 c->dcache.ways = 2;
 877                 c->dcache.waybit = 0;
 878
 879                 c->options |= MIPS_CPU_PREFETCH;
 880                 break;
 881
 882         case CPU_VR4133:
 883                 write_c0_config(config & ~CONF_EB);
 884         case CPU_VR4131:
 885                 /* Workaround for cache instruction bug of VR4131 */
 886                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 887                     c->processor_id == 0x0c82U) {
 888                         config &= ~0x00000030U;
 889                         config |= 0x00410000U;
 890                         write_c0_config(config);
 891                 }
 892                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 893                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 894                 c->icache.ways = 2;
 895                 c->icache.waybit = ffs(icache_size/2) - 1;
 896
 897                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 898                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 899                 c->dcache.ways = 2;
 900                 c->dcache.waybit = ffs(dcache_size/2) - 1;
 901
 902                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 903                 break;
 904
 905         case CPU_VR41XX:
 906         case CPU_VR4111:
 907         case CPU_VR4121:
 908         case CPU_VR4122:
 909         case CPU_VR4181:
 910         case CPU_VR4181A:
 911                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 912                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 913                 c->icache.ways = 1;
 914                 c->icache.waybit = 0;   /* doesn't matter */
 915
 916                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 917                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 918                 c->dcache.ways = 1;
 919                 c->dcache.waybit = 0;   /* does not matter */
 920
 921                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 922                 break;
 923
 924         case CPU_RM7000:
 925                 rm7k_erratum31();
 926
 927         case CPU_RM9000:
 928                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 929                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 930                 c->icache.ways = 4;
 931                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
 932
 933                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 934                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 935                 c->dcache.ways = 4;
 936                 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
 937
 938 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
 939                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 940 #endif
 941                 c->options |= MIPS_CPU_PREFETCH;
 942                 break;
 943
 944         default:
 945                 if (!(config & MIPS_CONF_M))
 946                         panic("Don't know how to probe P-caches on this cpu.");
 947
 948                 /*
 949                  * So we seem to be a MIPS32 or MIPS64 CPU
 950                  * So let's probe the I-cache ...
 951                  */
 952                 config1 = read_c0_config1();
 953
 954                 if ((lsize = ((config1 >> 19) & 7)))
 955                         c->icache.linesz = 2 << lsize;
 956                 else
 957                         c->icache.linesz = lsize;
 958                 c->icache.sets = 64 << ((config1 >> 22) & 7);
 959                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 960
 961                 icache_size = c->icache.sets *
 962                               c->icache.ways *
 963                               c->icache.linesz;
 964                 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
 965
 966                 if (config & 0x8)               /* VI bit */
 967                         c->icache.flags |= MIPS_CACHE_VTAG;
 968
 969                 /*
 970                  * Now probe the MIPS32 / MIPS64 data cache.
 971                  */
 972                 c->dcache.flags = 0;
 973
 974                 if ((lsize = ((config1 >> 10) & 7)))
 975                         c->dcache.linesz = 2 << lsize;
 976                 else
 977                         c->dcache.linesz= lsize;
 978                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
 979                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 980
 981                 dcache_size = c->dcache.sets *
 982                               c->dcache.ways *
 983                               c->dcache.linesz;
 984                 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
 985
 986                 c->options |= MIPS_CPU_PREFETCH;
 987                 break;
 988         }
 989
 990         /*
 991          * Processor configuration sanity check for the R4000SC erratum
 992          * #5.  With page sizes larger than 32kB there is no possibility
 993          * to get a VCE exception anymore so we don't care about this
 994          * misconfiguration.  The case is rather theoretical anyway;
 995          * presumably no vendor is shipping his hardware in the "bad"
 996          * configuration.
 997          */
 998         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
 999             !(config & CONF_SC) && c->icache.linesz != 16 &&
1000             PAGE_SIZE <= 0x8000)
1001                 panic("Improper R4000SC processor configuration detected");
1002
1003         /* compute a couple of other cache variables */
1004         c->icache.waysize = icache_size / c->icache.ways;
1005         c->dcache.waysize = dcache_size / c->dcache.ways;
1006
1007         c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
1008         c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
1009
1010         /*
1011          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
1012          * 2-way virtually indexed so normally would suffer from aliases.  So
1013          * normally they'd suffer from aliases but magic in the hardware deals
1014          * with that for us so we don't need to take care ourselves.
1015          */
1016         switch (c->cputype) {
1017         case CPU_20KC:
1018         case CPU_25KF:
1019         case CPU_R10000:
1020         case CPU_R12000:
1021         case CPU_SB1:
1022                 break;
1023         case CPU_24K:
1024                 if (!(read_c0_config7() & (1 << 16)))
1025         default:
1026                         if (c->dcache.waysize > PAGE_SIZE)
1027                                 c->dcache.flags |= MIPS_CACHE_ALIASES;
1028         }
1029
1030         switch (c->cputype) {
1031         case CPU_20KC:
1032                 /*
1033                  * Some older 20Kc chips doesn't have the 'VI' bit in
1034                  * the config register.
1035                  */
1036                 c->icache.flags |= MIPS_CACHE_VTAG;
1037                 break;
1038
1039         case CPU_AU1500:
1040                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1041                 break;
1042         }
1043
1044         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1045                icache_size >> 10,
1046                cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
1047                way_string[c->icache.ways], c->icache.linesz);
1048
1049         printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
1050                dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
1051 }
1052
1053 /*
1054  * If you even _breathe_ on this function, look at the gcc output and make sure
1055  * it does not pop things on and off the stack for the cache sizing loop that
1056  * executes in KSEG1 space or else you will crash and burn badly.  You have
1057  * been warned.
1058  */
1059 static int __init probe_scache(void)
1060 {
1061         extern unsigned long stext;
1062         unsigned long flags, addr, begin, end, pow2;
1063         unsigned int config = read_c0_config();
1064         struct cpuinfo_mips *c = &current_cpu_data;
1065         int tmp;
1066
1067         if (config & CONF_SC)
1068                 return 0;
1069
1070         begin = (unsigned long) &stext;
1071         begin &= ~((4 * 1024 * 1024) - 1);
1072         end = begin + (4 * 1024 * 1024);
1073
1074         /*
1075          * This is such a bitch, you'd think they would make it easy to do
1076          * this.  Away you daemons of stupidity!
1077          */
1078         local_irq_save(flags);
1079
1080         /* Fill each size-multiple cache line with a valid tag. */
1081         pow2 = (64 * 1024);
1082         for (addr = begin; addr < end; addr = (begin + pow2)) {
1083                 unsigned long *p = (unsigned long *) addr;
1084                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1085                 pow2 <<= 1;
1086         }
1087
1088         /* Load first line with zero (therefore invalid) tag. */
1089         write_c0_taglo(0);
1090         write_c0_taghi(0);
1091         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1092         cache_op(Index_Store_Tag_I, begin);
1093         cache_op(Index_Store_Tag_D, begin);
1094         cache_op(Index_Store_Tag_SD, begin);
1095
1096         /* Now search for the wrap around point. */
1097         pow2 = (128 * 1024);
1098         tmp = 0;
1099         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1100                 cache_op(Index_Load_Tag_SD, addr);
1101                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1102                 if (!read_c0_taglo())
1103                         break;
1104                 pow2 <<= 1;
1105         }
1106         local_irq_restore(flags);
1107         addr -= begin;
1108
1109         scache_size = addr;
1110         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1111         c->scache.ways = 1;
1112         c->dcache.waybit = 0;           /* does not matter */
1113
1114         return 1;
1115 }
1116
1117 typedef int (*probe_func_t)(unsigned long);
1118 extern int r5k_sc_init(void);
1119 extern int rm7k_sc_init(void);
1120
1121 static void __init setup_scache(void)
1122 {
1123         struct cpuinfo_mips *c = &current_cpu_data;
1124         unsigned int config = read_c0_config();
1125         probe_func_t probe_scache_kseg1;
1126         int sc_present = 0;
1127
1128         /*
1129          * Do the probing thing on R4000SC and R4400SC processors.  Other
1130          * processors don't have a S-cache that would be relevant to the
1131          * Linux memory managment.
1132          */
1133         switch (c->cputype) {
1134         case CPU_R4000SC:
1135         case CPU_R4000MC:
1136         case CPU_R4400SC:
1137         case CPU_R4400MC:
1138                 probe_scache_kseg1 = (probe_func_t) (CKSEG1ADDR(&probe_scache));
1139                 sc_present = probe_scache_kseg1(config);
1140                 if (sc_present)
1141                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1142                 break;
1143
1144         case CPU_R10000:
1145         case CPU_R12000:
1146                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1147                 c->scache.linesz = 64 << ((config >> 13) & 1);
1148                 c->scache.ways = 2;
1149                 c->scache.waybit= 0;
1150                 sc_present = 1;
1151                 break;
1152
1153         case CPU_R5000:
1154         case CPU_NEVADA:
1155 #ifdef CONFIG_R5000_CPU_SCACHE
1156                 r5k_sc_init();
1157 #endif
1158                 return;
1159
1160         case CPU_RM7000:
1161         case CPU_RM9000:
1162 #ifdef CONFIG_RM7000_CPU_SCACHE
1163                 rm7k_sc_init();
1164 #endif
1165                 return;
1166
1167         default:
1168                 sc_present = 0;
1169         }
1170
1171         if (!sc_present)
1172                 return;
1173
1174         if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1175              c->isa_level == MIPS_CPU_ISA_M64) &&
1176             !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1177                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1178
1179         /* compute a couple of other cache variables */
1180         c->scache.waysize = scache_size / c->scache.ways;
1181
1182         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1183
1184         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1185                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1186
1187         c->options |= MIPS_CPU_SUBSET_CACHES;
1188 }
1189
1190 static inline void coherency_setup(void)
1191 {
1192         change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1193
1194         /*
1195          * c0_status.cu=0 specifies that updates by the sc instruction use
1196          * the coherency mode specified by the TLB; 1 means cachable
1197          * coherent update on write will be used.  Not all processors have
1198          * this bit and; some wire it to zero, others like Toshiba had the
1199          * silly idea of putting something else there ...
1200          */
1201         switch (current_cpu_data.cputype) {
1202         case CPU_R4000PC:
1203         case CPU_R4000SC:
1204         case CPU_R4000MC:
1205         case CPU_R4400PC:
1206         case CPU_R4400SC:
1207         case CPU_R4400MC:
1208                 clear_c0_config(CONF_CU);
1209                 break;
1210         }
1211 }
1212
1213 void __init ld_mmu_r4xx0(void)
1214 {
1215         extern void build_clear_page(void);
1216         extern void build_copy_page(void);
1217         extern char except_vec2_generic;
1218         struct cpuinfo_mips *c = &current_cpu_data;
1219
1220         /* Default cache error handler for R4000 and R5000 family */
1221         memcpy((void *)(CAC_BASE   + 0x100), &except_vec2_generic, 0x80);
1222         memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
1223
1224         probe_pcache();
1225         setup_scache();
1226
1227         r4k_blast_dcache_page_setup();
1228         r4k_blast_dcache_page_indexed_setup();
1229         r4k_blast_dcache_setup();
1230         r4k_blast_icache_page_setup();
1231         r4k_blast_icache_page_indexed_setup();
1232         r4k_blast_icache_setup();
1233         r4k_blast_scache_page_setup();
1234         r4k_blast_scache_page_indexed_setup();
1235         r4k_blast_scache_setup();
1236
1237         /*
1238          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1239          * This code supports virtually indexed processors and will be
1240          * unnecessarily inefficient on physically indexed processors.
1241          */
1242         shm_align_mask = max_t( unsigned long,
1243                                 c->dcache.sets * c->dcache.linesz - 1,
1244                                 PAGE_SIZE - 1);
1245
1246         flush_cache_all         = r4k_flush_cache_all;
1247         __flush_cache_all       = r4k___flush_cache_all;
1248         flush_cache_mm          = r4k_flush_cache_mm;
1249         flush_cache_page        = r4k_flush_cache_page;
1250         flush_icache_page       = r4k_flush_icache_page;
1251         flush_cache_range       = r4k_flush_cache_range;
1252
1253         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1254         flush_icache_all        = r4k_flush_icache_all;
1255         flush_data_cache_page   = r4k_flush_data_cache_page;
1256         flush_icache_range      = r4k_flush_icache_range;
1257
1258 #ifdef CONFIG_DMA_NONCOHERENT
1259         _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1260         _dma_cache_wback        = r4k_dma_cache_wback_inv;
1261         _dma_cache_inv          = r4k_dma_cache_inv;
1262 #endif
1263
1264         __flush_cache_all();
1265         coherency_setup();
1266
1267         build_clear_page();
1268         build_copy_page();
1269 }