arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/hardirq.h>
  11 #include <linux/init.h>
  12 #include <linux/highmem.h>
  13 #include <linux/kernel.h>
  14 #include <linux/linkage.h>
  15 #include <linux/preempt.h>
  16 #include <linux/sched.h>
  17 #include <linux/smp.h>
  18 #include <linux/mm.h>
  19 #include <linux/module.h>
  20 #include <linux/bitops.h>
  21
  22 #include <asm/bcache.h>
  23 #include <asm/bootinfo.h>
  24 #include <asm/cache.h>
  25 #include <asm/cacheops.h>
  26 #include <asm/cpu.h>
  27 #include <asm/cpu-features.h>
  28 #include <asm/cpu-type.h>
  29 #include <asm/io.h>
  30 #include <asm/page.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/r4kcache.h>
  33 #include <asm/sections.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/war.h>
  36 #include <asm/cacheflush.h> /* for run_uncached() */
  37 #include <asm/traps.h>
  38 #include <asm/dma-coherence.h>
  39
  40 /*
  41  * Special Variant of smp_call_function for use by cache functions:
  42  *
  43  *  o No return value
  44  *  o collapses to normal function call on UP kernels
  45  *  o collapses to normal function call on systems with a single shared
  46  *    primary cache.
  47  *  o doesn't disable interrupts on the local CPU
  48  */
  49 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
  50 {
  51         preempt_disable();
  52
  53 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
  54         smp_call_function(func, info, 1);
  55 #endif
  56         func(info);
  57         preempt_enable();
  58 }
  59
  60 #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS)
  61 #define cpu_has_safe_index_cacheops 0
  62 #else
  63 #define cpu_has_safe_index_cacheops 1
  64 #endif
  65
  66 /*
  67  * Must die.
  68  */
  69 static unsigned long icache_size __read_mostly;
  70 static unsigned long dcache_size __read_mostly;
  71 static unsigned long scache_size __read_mostly;
  72
  73 /*
  74  * Dummy cache handling routines for machines without boardcaches
  75  */
  76 static void cache_noop(void) {}
  77
  78 static struct bcache_ops no_sc_ops = {
  79         .bc_enable = (void *)cache_noop,
  80         .bc_disable = (void *)cache_noop,
  81         .bc_wback_inv = (void *)cache_noop,
  82         .bc_inv = (void *)cache_noop
  83 };
  84
  85 struct bcache_ops *bcops = &no_sc_ops;
  86
  87 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  88 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  89
  90 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  91 do {                                                                    \
  92         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  93                 *(volatile unsigned long *)CKSEG1;                      \
  94         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  95                 __asm__ __volatile__("nop;nop;nop;nop");                \
  96 } while (0)
  97
  98 static void (*r4k_blast_dcache_page)(unsigned long addr);
  99
 100 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 101 {
 102         R4600_HIT_CACHEOP_WAR_IMPL;
 103         blast_dcache32_page(addr);
 104 }
 105
 106 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 107 {
 108         R4600_HIT_CACHEOP_WAR_IMPL;
 109         blast_dcache64_page(addr);
 110 }
 111
 112 static void r4k_blast_dcache_page_setup(void)
 113 {
 114         unsigned long  dc_lsize = cpu_dcache_line_size();
 115
 116         if (dc_lsize == 0)
 117                 r4k_blast_dcache_page = (void *)cache_noop;
 118         else if (dc_lsize == 16)
 119                 r4k_blast_dcache_page = blast_dcache16_page;
 120         else if (dc_lsize == 32)
 121                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 122         else if (dc_lsize == 64)
 123                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 124 }
 125
 126 #ifndef CONFIG_EVA
 127 #define r4k_blast_dcache_user_page  r4k_blast_dcache_page
 128 #else
 129
 130 static void (*r4k_blast_dcache_user_page)(unsigned long addr);
 131
 132 static void r4k_blast_dcache_user_page_setup(void)
 133 {
 134         unsigned long  dc_lsize = cpu_dcache_line_size();
 135
 136         if (dc_lsize == 0)
 137                 r4k_blast_dcache_user_page = (void *)cache_noop;
 138         else if (dc_lsize == 16)
 139                 r4k_blast_dcache_user_page = blast_dcache16_user_page;
 140         else if (dc_lsize == 32)
 141                 r4k_blast_dcache_user_page = blast_dcache32_user_page;
 142         else if (dc_lsize == 64)
 143                 r4k_blast_dcache_user_page = blast_dcache64_user_page;
 144 }
 145
 146 #endif
 147
 148 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 149
 150 static void r4k_blast_dcache_page_indexed_setup(void)
 151 {
 152         unsigned long dc_lsize = cpu_dcache_line_size();
 153
 154         if (dc_lsize == 0)
 155                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 156         else if (dc_lsize == 16)
 157                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 158         else if (dc_lsize == 32)
 159                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 160         else if (dc_lsize == 64)
 161                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 162 }
 163
 164 void (* r4k_blast_dcache)(void);
 165 EXPORT_SYMBOL(r4k_blast_dcache);
 166
 167 static void r4k_blast_dcache_setup(void)
 168 {
 169         unsigned long dc_lsize = cpu_dcache_line_size();
 170
 171         if (dc_lsize == 0)
 172                 r4k_blast_dcache = (void *)cache_noop;
 173         else if (dc_lsize == 16)
 174                 r4k_blast_dcache = blast_dcache16;
 175         else if (dc_lsize == 32)
 176                 r4k_blast_dcache = blast_dcache32;
 177         else if (dc_lsize == 64)
 178                 r4k_blast_dcache = blast_dcache64;
 179 }
 180
 181 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 182 #define JUMP_TO_ALIGN(order) \
 183         __asm__ __volatile__( \
 184                 "b\t1f\n\t" \
 185                 ".align\t" #order "\n\t" \
 186                 "1:\n\t" \
 187                 )
 188 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 189 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 190
 191 static inline void blast_r4600_v1_icache32(void)
 192 {
 193         unsigned long flags;
 194
 195         local_irq_save(flags);
 196         blast_icache32();
 197         local_irq_restore(flags);
 198 }
 199
 200 static inline void tx49_blast_icache32(void)
 201 {
 202         unsigned long start = INDEX_BASE;
 203         unsigned long end = start + current_cpu_data.icache.waysize;
 204         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 205         unsigned long ws_end = current_cpu_data.icache.ways <<
 206                                current_cpu_data.icache.waybit;
 207         unsigned long ws, addr;
 208
 209         CACHE32_UNROLL32_ALIGN2;
 210         /* I'm in even chunk.  blast odd chunks */
 211         for (ws = 0; ws < ws_end; ws += ws_inc)
 212                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 213                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 214         CACHE32_UNROLL32_ALIGN;
 215         /* I'm in odd chunk.  blast even chunks */
 216         for (ws = 0; ws < ws_end; ws += ws_inc)
 217                 for (addr = start; addr < end; addr += 0x400 * 2)
 218                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 219 }
 220
 221 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 222 {
 223         unsigned long flags;
 224
 225         local_irq_save(flags);
 226         blast_icache32_page_indexed(page);
 227         local_irq_restore(flags);
 228 }
 229
 230 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 231 {
 232         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 233         unsigned long start = INDEX_BASE + (page & indexmask);
 234         unsigned long end = start + PAGE_SIZE;
 235         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 236         unsigned long ws_end = current_cpu_data.icache.ways <<
 237                                current_cpu_data.icache.waybit;
 238         unsigned long ws, addr;
 239
 240         CACHE32_UNROLL32_ALIGN2;
 241         /* I'm in even chunk.  blast odd chunks */
 242         for (ws = 0; ws < ws_end; ws += ws_inc)
 243                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 244                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 245         CACHE32_UNROLL32_ALIGN;
 246         /* I'm in odd chunk.  blast even chunks */
 247         for (ws = 0; ws < ws_end; ws += ws_inc)
 248                 for (addr = start; addr < end; addr += 0x400 * 2)
 249                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 250 }
 251
 252 static void (* r4k_blast_icache_page)(unsigned long addr);
 253
 254 static void r4k_blast_icache_page_setup(void)
 255 {
 256         unsigned long ic_lsize = cpu_icache_line_size();
 257
 258         if (ic_lsize == 0)
 259                 r4k_blast_icache_page = (void *)cache_noop;
 260         else if (ic_lsize == 16)
 261                 r4k_blast_icache_page = blast_icache16_page;
 262         else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
 263                 r4k_blast_icache_page = loongson2_blast_icache32_page;
 264         else if (ic_lsize == 32)
 265                 r4k_blast_icache_page = blast_icache32_page;
 266         else if (ic_lsize == 64)
 267                 r4k_blast_icache_page = blast_icache64_page;
 268 }
 269
 270 #ifndef CONFIG_EVA
 271 #define r4k_blast_icache_user_page  r4k_blast_icache_page
 272 #else
 273
 274 static void (*r4k_blast_icache_user_page)(unsigned long addr);
 275
 276 static void __cpuinit r4k_blast_icache_user_page_setup(void)
 277 {
 278         unsigned long ic_lsize = cpu_icache_line_size();
 279
 280         if (ic_lsize == 0)
 281                 r4k_blast_icache_user_page = (void *)cache_noop;
 282         else if (ic_lsize == 16)
 283                 r4k_blast_icache_user_page = blast_icache16_user_page;
 284         else if (ic_lsize == 32)
 285                 r4k_blast_icache_user_page = blast_icache32_user_page;
 286         else if (ic_lsize == 64)
 287                 r4k_blast_icache_user_page = blast_icache64_user_page;
 288 }
 289
 290 #endif
 291
 292 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 293
 294 static void r4k_blast_icache_page_indexed_setup(void)
 295 {
 296         unsigned long ic_lsize = cpu_icache_line_size();
 297
 298         if (ic_lsize == 0)
 299                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 300         else if (ic_lsize == 16)
 301                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 302         else if (ic_lsize == 32) {
 303                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 304                         r4k_blast_icache_page_indexed =
 305                                 blast_icache32_r4600_v1_page_indexed;
 306                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 307                         r4k_blast_icache_page_indexed =
 308                                 tx49_blast_icache32_page_indexed;
 309                 else if (current_cpu_type() == CPU_LOONGSON2)
 310                         r4k_blast_icache_page_indexed =
 311                                 loongson2_blast_icache32_page_indexed;
 312                 else
 313                         r4k_blast_icache_page_indexed =
 314                                 blast_icache32_page_indexed;
 315         } else if (ic_lsize == 64)
 316                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 317 }
 318
 319 void (* r4k_blast_icache)(void);
 320 EXPORT_SYMBOL(r4k_blast_icache);
 321
 322 static void r4k_blast_icache_setup(void)
 323 {
 324         unsigned long ic_lsize = cpu_icache_line_size();
 325
 326         if (ic_lsize == 0)
 327                 r4k_blast_icache = (void *)cache_noop;
 328         else if (ic_lsize == 16)
 329                 r4k_blast_icache = blast_icache16;
 330         else if (ic_lsize == 32) {
 331                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 332                         r4k_blast_icache = blast_r4600_v1_icache32;
 333                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 334                         r4k_blast_icache = tx49_blast_icache32;
 335                 else if (current_cpu_type() == CPU_LOONGSON2)
 336                         r4k_blast_icache = loongson2_blast_icache32;
 337                 else
 338                         r4k_blast_icache = blast_icache32;
 339         } else if (ic_lsize == 64)
 340                 r4k_blast_icache = blast_icache64;
 341 }
 342
 343 static void (* r4k_blast_scache_page)(unsigned long addr);
 344
 345 static void r4k_blast_scache_page_setup(void)
 346 {
 347         unsigned long sc_lsize = cpu_scache_line_size();
 348
 349         if (scache_size == 0)
 350                 r4k_blast_scache_page = (void *)cache_noop;
 351         else if (sc_lsize == 16)
 352                 r4k_blast_scache_page = blast_scache16_page;
 353         else if (sc_lsize == 32)
 354                 r4k_blast_scache_page = blast_scache32_page;
 355         else if (sc_lsize == 64)
 356                 r4k_blast_scache_page = blast_scache64_page;
 357         else if (sc_lsize == 128)
 358                 r4k_blast_scache_page = blast_scache128_page;
 359 }
 360
 361 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 362
 363 static void r4k_blast_scache_page_indexed_setup(void)
 364 {
 365         unsigned long sc_lsize = cpu_scache_line_size();
 366
 367         if (scache_size == 0)
 368                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 369         else if (sc_lsize == 16)
 370                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 371         else if (sc_lsize == 32)
 372                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 373         else if (sc_lsize == 64)
 374                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 375         else if (sc_lsize == 128)
 376                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 377 }
 378
 379 static void (* r4k_blast_scache)(void);
 380
 381 static void r4k_blast_scache_setup(void)
 382 {
 383         unsigned long sc_lsize = cpu_scache_line_size();
 384
 385         if (scache_size == 0)
 386                 r4k_blast_scache = (void *)cache_noop;
 387         else if (sc_lsize == 16)
 388                 r4k_blast_scache = blast_scache16;
 389         else if (sc_lsize == 32)
 390                 r4k_blast_scache = blast_scache32;
 391         else if (sc_lsize == 64)
 392                 r4k_blast_scache = blast_scache64;
 393         else if (sc_lsize == 128)
 394                 r4k_blast_scache = blast_scache128;
 395 }
 396
 397 static inline void local_r4k___flush_cache_all(void * args)
 398 {
 399         switch (current_cpu_type()) {
 400         case CPU_LOONGSON2:
 401         case CPU_R4000SC:
 402         case CPU_R4000MC:
 403         case CPU_R4400SC:
 404         case CPU_R4400MC:
 405         case CPU_R10000:
 406         case CPU_R12000:
 407         case CPU_R14000:
 408                 /*
 409                  * These caches are inclusive caches, that is, if something
 410                  * is not cached in the S-cache, we know it also won't be
 411                  * in one of the primary caches.
 412                  */
 413                 r4k_blast_scache();
 414                 break;
 415
 416         default:
 417                 r4k_blast_dcache();
 418                 r4k_blast_icache();
 419                 break;
 420         }
 421 }
 422
 423 static void r4k___flush_cache_all(void)
 424 {
 425         r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
 426 }
 427
 428 static inline int has_valid_asid(const struct mm_struct *mm)
 429 {
 430 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
 431         int i;
 432
 433         for_each_online_cpu(i)
 434                 if (cpu_context(i, mm))
 435                         return 1;
 436
 437         return 0;
 438 #else
 439         return cpu_context(smp_processor_id(), mm);
 440 #endif
 441 }
 442
 443 static void r4k__flush_cache_vmap(void)
 444 {
 445         r4k_blast_dcache();
 446 }
 447
 448 static void r4k__flush_cache_vunmap(void)
 449 {
 450         r4k_blast_dcache();
 451 }
 452
 453 static inline void local_r4k_flush_cache_range(void * args)
 454 {
 455         struct vm_area_struct *vma = args;
 456         int exec = vma->vm_flags & VM_EXEC;
 457
 458         if (!(has_valid_asid(vma->vm_mm)))
 459                 return;
 460
 461         r4k_blast_dcache();
 462         if (exec)
 463                 r4k_blast_icache();
 464 }
 465
 466 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 467         unsigned long start, unsigned long end)
 468 {
 469         int exec = vma->vm_flags & VM_EXEC;
 470
 471         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 472                 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
 473 }
 474
 475 static inline void local_r4k_flush_cache_mm(void * args)
 476 {
 477         struct mm_struct *mm = args;
 478
 479         if (!has_valid_asid(mm))
 480                 return;
 481
 482         /*
 483          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 484          * only flush the primary caches but R10000 and R12000 behave sane ...
 485          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 486          * caches, so we can bail out early.
 487          */
 488         if (current_cpu_type() == CPU_R4000SC ||
 489             current_cpu_type() == CPU_R4000MC ||
 490             current_cpu_type() == CPU_R4400SC ||
 491             current_cpu_type() == CPU_R4400MC) {
 492                 r4k_blast_scache();
 493                 return;
 494         }
 495
 496         r4k_blast_dcache();
 497 }
 498
 499 static void r4k_flush_cache_mm(struct mm_struct *mm)
 500 {
 501         if (!cpu_has_dc_aliases)
 502                 return;
 503
 504         r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
 505 }
 506
 507 struct flush_cache_page_args {
 508         struct vm_area_struct *vma;
 509         unsigned long addr;
 510         unsigned long pfn;
 511 };
 512
 513 static inline void local_r4k_flush_cache_page(void *args)
 514 {
 515         struct flush_cache_page_args *fcp_args = args;
 516         struct vm_area_struct *vma = fcp_args->vma;
 517         unsigned long addr = fcp_args->addr;
 518         struct page *page = pfn_to_page(fcp_args->pfn);
 519         int exec = vma->vm_flags & VM_EXEC;
 520         struct mm_struct *mm = vma->vm_mm;
 521         int map_coherent = 0;
 522         pgd_t *pgdp;
 523         pud_t *pudp;
 524         pmd_t *pmdp;
 525         pte_t *ptep;
 526         void *vaddr;
 527
 528         /*
 529          * If ownes no valid ASID yet, cannot possibly have gotten
 530          * this page into the cache.
 531          */
 532         if (!has_valid_asid(mm))
 533                 return;
 534
 535         addr &= PAGE_MASK;
 536         pgdp = pgd_offset(mm, addr);
 537         pudp = pud_offset(pgdp, addr);
 538         pmdp = pmd_offset(pudp, addr);
 539         ptep = pte_offset(pmdp, addr);
 540
 541         /*
 542          * If the page isn't marked valid, the page cannot possibly be
 543          * in the cache.
 544          */
 545         if (!(pte_present(*ptep)))
 546                 return;
 547
 548         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 549                 vaddr = NULL;
 550         else {
 551                 /*
 552                  * Use kmap_coherent or kmap_atomic to do flushes for
 553                  * another ASID than the current one.
 554                  */
 555                 map_coherent = (cpu_has_dc_aliases &&
 556                                 page_mapped(page) && !Page_dcache_dirty(page));
 557                 if (map_coherent)
 558                         vaddr = kmap_coherent(page, addr);
 559                 else
 560                         vaddr = kmap_atomic(page);
 561                 addr = (unsigned long)vaddr;
 562         }
 563
 564         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 565                 vaddr ? r4k_blast_dcache_page(addr) :
 566                         r4k_blast_dcache_user_page(addr);
 567                 if (exec && !cpu_icache_snoops_remote_store)
 568                         r4k_blast_scache_page(addr);
 569         }
 570         if (exec) {
 571                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 572                         int cpu = smp_processor_id();
 573
 574                         if (cpu_context(cpu, mm) != 0)
 575                                 drop_mmu_context(mm, cpu);
 576                 } else
 577                         vaddr ? r4k_blast_icache_page(addr) :
 578                                 r4k_blast_icache_user_page(addr);
 579         }
 580
 581         if (vaddr) {
 582                 if (map_coherent)
 583                         kunmap_coherent();
 584                 else
 585                         kunmap_atomic(vaddr);
 586         }
 587 }
 588
 589 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 590         unsigned long addr, unsigned long pfn)
 591 {
 592         struct flush_cache_page_args args;
 593
 594         args.vma = vma;
 595         args.addr = addr;
 596         args.pfn = pfn;
 597
 598         r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
 599 }
 600
 601 static inline void local_r4k_flush_data_cache_page(void * addr)
 602 {
 603         r4k_blast_dcache_page((unsigned long) addr);
 604 }
 605
 606 static void r4k_flush_data_cache_page(unsigned long addr)
 607 {
 608         if (in_atomic())
 609                 local_r4k_flush_data_cache_page((void *)addr);
 610         else
 611                 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
 612 }
 613
 614 struct flush_icache_range_args {
 615         unsigned long start;
 616         unsigned long end;
 617 };
 618
 619 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
 620 {
 621         if (!cpu_has_ic_fills_f_dc) {
 622                 if (end - start >= dcache_size) {
 623                         r4k_blast_dcache();
 624                 } else {
 625                         R4600_HIT_CACHEOP_WAR_IMPL;
 626                         protected_blast_dcache_range(start, end);
 627                 }
 628         }
 629
 630         if (end - start > icache_size)
 631                 r4k_blast_icache();
 632         else {
 633                 switch (boot_cpu_type()) {
 634                 case CPU_LOONGSON2:
 635                         protected_loongson2_blast_icache_range(start, end);
 636                         break;
 637
 638                 default:
 639                         protected_blast_icache_range(start, end);
 640                         break;
 641                 }
 642         }
 643 }
 644
 645 static inline void local_r4k_flush_icache_range_ipi(void *args)
 646 {
 647         struct flush_icache_range_args *fir_args = args;
 648         unsigned long start = fir_args->start;
 649         unsigned long end = fir_args->end;
 650
 651         local_r4k_flush_icache_range(start, end);
 652 }
 653
 654 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 655 {
 656         struct flush_icache_range_args args;
 657
 658         args.start = start;
 659         args.end = end;
 660
 661         r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
 662         instruction_hazard();
 663 }
 664
 665 #ifdef CONFIG_DMA_NONCOHERENT
 666
 667 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 668 {
 669         /* Catch bad driver code */
 670         BUG_ON(size == 0);
 671
 672         preempt_disable();
 673         if (cpu_has_inclusive_pcaches) {
 674                 if (size >= scache_size)
 675                         r4k_blast_scache();
 676                 else
 677                         blast_scache_range(addr, addr + size);
 678                 preempt_enable();
 679                 __sync();
 680                 return;
 681         }
 682
 683         /*
 684          * Either no secondary cache or the available caches don't have the
 685          * subset property so we have to flush the primary caches
 686          * explicitly
 687          */
 688         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 689                 r4k_blast_dcache();
 690         } else {
 691                 R4600_HIT_CACHEOP_WAR_IMPL;
 692                 blast_dcache_range(addr, addr + size);
 693         }
 694         preempt_enable();
 695
 696         bc_wback_inv(addr, size);
 697         __sync();
 698 }
 699
 700 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 701 {
 702         /* Catch bad driver code */
 703         BUG_ON(size == 0);
 704
 705         preempt_disable();
 706         if (cpu_has_inclusive_pcaches) {
 707                 if (size >= scache_size)
 708                         r4k_blast_scache();
 709                 else {
 710                         /*
 711                          * There is no clearly documented alignment requirement
 712                          * for the cache instruction on MIPS processors and
 713                          * some processors, among them the RM5200 and RM7000
 714                          * QED processors will throw an address error for cache
 715                          * hit ops with insufficient alignment.  Solved by
 716                          * aligning the address to cache line size.
 717                          */
 718                         blast_inv_scache_range(addr, addr + size);
 719                 }
 720                 preempt_enable();
 721                 __sync();
 722                 return;
 723         }
 724
 725         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 726                 r4k_blast_dcache();
 727         } else {
 728                 R4600_HIT_CACHEOP_WAR_IMPL;
 729                 blast_inv_dcache_range(addr, addr + size);
 730         }
 731         preempt_enable();
 732
 733         bc_inv(addr, size);
 734         __sync();
 735 }
 736 #endif /* CONFIG_DMA_NONCOHERENT */
 737
 738 /*
 739  * While we're protected against bad userland addresses we don't care
 740  * very much about what happens in that case.  Usually a segmentation
 741  * fault will dump the process later on anyway ...
 742  */
 743 static void local_r4k_flush_cache_sigtramp(void * arg)
 744 {
 745         unsigned long ic_lsize = cpu_icache_line_size();
 746         unsigned long dc_lsize = cpu_dcache_line_size();
 747         unsigned long sc_lsize = cpu_scache_line_size();
 748         unsigned long addr = (unsigned long) arg;
 749
 750         R4600_HIT_CACHEOP_WAR_IMPL;
 751         if (dc_lsize)
 752                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 753         if (!cpu_icache_snoops_remote_store && scache_size)
 754                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 755         if (ic_lsize)
 756                 protected_flush_icache_line(addr & ~(ic_lsize - 1));
 757         if (MIPS4K_ICACHE_REFILL_WAR) {
 758                 __asm__ __volatile__ (
 759                         ".set push\n\t"
 760                         ".set noat\n\t"
 761                         ".set mips3\n\t"
 762 #ifdef CONFIG_32BIT
 763                         "la     $at,1f\n\t"
 764 #endif
 765 #ifdef CONFIG_64BIT
 766                         "dla    $at,1f\n\t"
 767 #endif
 768                         "cache  %0,($at)\n\t"
 769                         "nop; nop; nop\n"
 770                         "1:\n\t"
 771                         ".set pop"
 772                         :
 773                         : "i" (Hit_Invalidate_I));
 774         }
 775         if (MIPS_CACHE_SYNC_WAR)
 776                 __asm__ __volatile__ ("sync");
 777 }
 778
 779 static void r4k_flush_cache_sigtramp(unsigned long addr)
 780 {
 781         r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
 782 }
 783
 784 static void r4k_flush_icache_all(void)
 785 {
 786         if (cpu_has_vtag_icache)
 787                 r4k_blast_icache();
 788 }
 789
 790 struct flush_kernel_vmap_range_args {
 791         unsigned long   vaddr;
 792         int             size;
 793 };
 794
 795 static inline void local_r4k_flush_kernel_vmap_range(void *args)
 796 {
 797         struct flush_kernel_vmap_range_args *vmra = args;
 798         unsigned long vaddr = vmra->vaddr;
 799         int size = vmra->size;
 800
 801         /*
 802          * Aliases only affect the primary caches so don't bother with
 803          * S-caches or T-caches.
 804          */
 805         if (cpu_has_safe_index_cacheops && size >= dcache_size)
 806                 r4k_blast_dcache();
 807         else {
 808                 R4600_HIT_CACHEOP_WAR_IMPL;
 809                 blast_dcache_range(vaddr, vaddr + size);
 810         }
 811 }
 812
 813 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
 814 {
 815         struct flush_kernel_vmap_range_args args;
 816
 817         args.vaddr = (unsigned long) vaddr;
 818         args.size = size;
 819
 820         r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
 821 }
 822
 823 static inline void rm7k_erratum31(void)
 824 {
 825         const unsigned long ic_lsize = 32;
 826         unsigned long addr;
 827
 828         /* RM7000 erratum #31. The icache is screwed at startup. */
 829         write_c0_taglo(0);
 830         write_c0_taghi(0);
 831
 832         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 833                 __asm__ __volatile__ (
 834                         ".set push\n\t"
 835                         ".set noreorder\n\t"
 836                         ".set mips3\n\t"
 837                         "cache\t%1, 0(%0)\n\t"
 838                         "cache\t%1, 0x1000(%0)\n\t"
 839                         "cache\t%1, 0x2000(%0)\n\t"
 840                         "cache\t%1, 0x3000(%0)\n\t"
 841                         "cache\t%2, 0(%0)\n\t"
 842                         "cache\t%2, 0x1000(%0)\n\t"
 843                         "cache\t%2, 0x2000(%0)\n\t"
 844                         "cache\t%2, 0x3000(%0)\n\t"
 845                         "cache\t%1, 0(%0)\n\t"
 846                         "cache\t%1, 0x1000(%0)\n\t"
 847                         "cache\t%1, 0x2000(%0)\n\t"
 848                         "cache\t%1, 0x3000(%0)\n\t"
 849                         ".set pop\n"
 850                         :
 851                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 852         }
 853 }
 854
 855 static inline void alias_74k_erratum(struct cpuinfo_mips *c)
 856 {
 857         unsigned int imp = c->processor_id & PRID_IMP_MASK;
 858         unsigned int rev = c->processor_id & PRID_REV_MASK;
 859
 860         /*
 861          * Early versions of the 74K do not update the cache tags on a
 862          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
 863          * aliases. In this case it is better to treat the cache as always
 864          * having aliases.
 865          */
 866         switch (imp) {
 867         case PRID_IMP_74K:
 868                 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
 869                         c->dcache.flags |= MIPS_CACHE_VTAG;
 870                 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
 871                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 872                 break;
 873         case PRID_IMP_1074K:
 874                 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
 875                         c->dcache.flags |= MIPS_CACHE_VTAG;
 876                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 877                 }
 878                 break;
 879         default:
 880                 BUG();
 881         }
 882 }
 883
 884 static char *way_string[] = { NULL, "direct mapped", "2-way",
 885         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 886 };
 887
 888 static void probe_pcache(void)
 889 {
 890         struct cpuinfo_mips *c = &current_cpu_data;
 891         unsigned int config = read_c0_config();
 892         unsigned int prid = read_c0_prid();
 893         unsigned long config1;
 894         unsigned int lsize;
 895
 896         switch (current_cpu_type()) {
 897         case CPU_R4600:                 /* QED style two way caches? */
 898         case CPU_R4700:
 899         case CPU_R5000:
 900         case CPU_NEVADA:
 901                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 902                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 903                 c->icache.ways = 2;
 904                 c->icache.waybit = __ffs(icache_size/2);
 905
 906                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 907                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 908                 c->dcache.ways = 2;
 909                 c->dcache.waybit= __ffs(dcache_size/2);
 910
 911                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 912                 break;
 913
 914         case CPU_R5432:
 915         case CPU_R5500:
 916                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 917                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 918                 c->icache.ways = 2;
 919                 c->icache.waybit= 0;
 920
 921                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 922                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 923                 c->dcache.ways = 2;
 924                 c->dcache.waybit = 0;
 925
 926                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
 927                 break;
 928
 929         case CPU_TX49XX:
 930                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 931                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 932                 c->icache.ways = 4;
 933                 c->icache.waybit= 0;
 934
 935                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 936                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 937                 c->dcache.ways = 4;
 938                 c->dcache.waybit = 0;
 939
 940                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 941                 c->options |= MIPS_CPU_PREFETCH;
 942                 break;
 943
 944         case CPU_R4000PC:
 945         case CPU_R4000SC:
 946         case CPU_R4000MC:
 947         case CPU_R4400PC:
 948         case CPU_R4400SC:
 949         case CPU_R4400MC:
 950         case CPU_R4300:
 951                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 952                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 953                 c->icache.ways = 1;
 954                 c->icache.waybit = 0;   /* doesn't matter */
 955
 956                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 957                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 958                 c->dcache.ways = 1;
 959                 c->dcache.waybit = 0;   /* does not matter */
 960
 961                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 962                 break;
 963
 964         case CPU_R10000:
 965         case CPU_R12000:
 966         case CPU_R14000:
 967                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 968                 c->icache.linesz = 64;
 969                 c->icache.ways = 2;
 970                 c->icache.waybit = 0;
 971
 972                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 973                 c->dcache.linesz = 32;
 974                 c->dcache.ways = 2;
 975                 c->dcache.waybit = 0;
 976
 977                 c->options |= MIPS_CPU_PREFETCH;
 978                 break;
 979
 980         case CPU_VR4133:
 981                 write_c0_config(config & ~VR41_CONF_P4K);
 982         case CPU_VR4131:
 983                 /* Workaround for cache instruction bug of VR4131 */
 984                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 985                     c->processor_id == 0x0c82U) {
 986                         config |= 0x00400000U;
 987                         if (c->processor_id == 0x0c80U)
 988                                 config |= VR41_CONF_BP;
 989                         write_c0_config(config);
 990                 } else
 991                         c->options |= MIPS_CPU_CACHE_CDEX_P;
 992
 993                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 994                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 995                 c->icache.ways = 2;
 996                 c->icache.waybit = __ffs(icache_size/2);
 997
 998                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 999                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1000                 c->dcache.ways = 2;
1001                 c->dcache.waybit = __ffs(dcache_size/2);
1002                 break;
1003
1004         case CPU_VR41XX:
1005         case CPU_VR4111:
1006         case CPU_VR4121:
1007         case CPU_VR4122:
1008         case CPU_VR4181:
1009         case CPU_VR4181A:
1010                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1011                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1012                 c->icache.ways = 1;
1013                 c->icache.waybit = 0;   /* doesn't matter */
1014
1015                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1016                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1017                 c->dcache.ways = 1;
1018                 c->dcache.waybit = 0;   /* does not matter */
1019
1020                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1021                 break;
1022
1023         case CPU_RM7000:
1024                 rm7k_erratum31();
1025
1026                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1027                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1028                 c->icache.ways = 4;
1029                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1030
1031                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1032                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1033                 c->dcache.ways = 4;
1034                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1035
1036                 c->options |= MIPS_CPU_CACHE_CDEX_P;
1037                 c->options |= MIPS_CPU_PREFETCH;
1038                 break;
1039
1040         case CPU_LOONGSON2:
1041                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1042                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1043                 if (prid & 0x3)
1044                         c->icache.ways = 4;
1045                 else
1046                         c->icache.ways = 2;
1047                 c->icache.waybit = 0;
1048
1049                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1050                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1051                 if (prid & 0x3)
1052                         c->dcache.ways = 4;
1053                 else
1054                         c->dcache.ways = 2;
1055                 c->dcache.waybit = 0;
1056                 break;
1057
1058         default:
1059                 if (!(config & MIPS_CONF_M))
1060                         panic("Don't know how to probe P-caches on this cpu.");
1061
1062                 /*
1063                  * So we seem to be a MIPS32 or MIPS64 CPU
1064                  * So let's probe the I-cache ...
1065                  */
1066                 config1 = read_c0_config1();
1067
1068                 lsize = (config1 >> 19) & 7;
1069
1070                 /* IL == 7 is reserved */
1071                 if (lsize == 7)
1072                         panic("Invalid icache line size");
1073
1074                 c->icache.linesz = lsize ? 2 << lsize : 0;
1075
1076                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1077                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1078
1079                 icache_size = c->icache.sets *
1080                               c->icache.ways *
1081                               c->icache.linesz;
1082                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1083
1084                 if (config & 0x8)               /* VI bit */
1085                         c->icache.flags |= MIPS_CACHE_VTAG;
1086
1087                 /*
1088                  * Now probe the MIPS32 / MIPS64 data cache.
1089                  */
1090                 c->dcache.flags = 0;
1091
1092                 lsize = (config1 >> 10) & 7;
1093
1094                 /* DL == 7 is reserved */
1095                 if (lsize == 7)
1096                         panic("Invalid dcache line size");
1097
1098                 c->dcache.linesz = lsize ? 2 << lsize : 0;
1099
1100                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1101                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1102
1103                 dcache_size = c->dcache.sets *
1104                               c->dcache.ways *
1105                               c->dcache.linesz;
1106                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1107
1108                 c->options |= MIPS_CPU_PREFETCH;
1109                 break;
1110         }
1111
1112         /*
1113          * Processor configuration sanity check for the R4000SC erratum
1114          * #5.  With page sizes larger than 32kB there is no possibility
1115          * to get a VCE exception anymore so we don't care about this
1116          * misconfiguration.  The case is rather theoretical anyway;
1117          * presumably no vendor is shipping his hardware in the "bad"
1118          * configuration.
1119          */
1120         if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1121             (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1122             !(config & CONF_SC) && c->icache.linesz != 16 &&
1123             PAGE_SIZE <= 0x8000)
1124                 panic("Improper R4000SC processor configuration detected");
1125
1126         /* compute a couple of other cache variables */
1127         c->icache.waysize = icache_size / c->icache.ways;
1128         c->dcache.waysize = dcache_size / c->dcache.ways;
1129
1130         c->icache.sets = c->icache.linesz ?
1131                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1132         c->dcache.sets = c->dcache.linesz ?
1133                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1134
1135         /*
1136          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
1137          * 2-way virtually indexed so normally would suffer from aliases.  So
1138          * normally they'd suffer from aliases but magic in the hardware deals
1139          * with that for us so we don't need to take care ourselves.
1140          */
1141         switch (current_cpu_type()) {
1142         case CPU_20KC:
1143         case CPU_25KF:
1144         case CPU_SB1:
1145         case CPU_SB1A:
1146         case CPU_XLR:
1147                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1148                 break;
1149
1150         case CPU_R10000:
1151         case CPU_R12000:
1152         case CPU_R14000:
1153                 break;
1154
1155         case CPU_M14KC:
1156         case CPU_M14KEC:
1157         case CPU_24K:
1158         case CPU_34K:
1159         case CPU_74K:
1160         case CPU_1004K:
1161         case CPU_1074K:
1162         case CPU_INTERAPTIV:
1163         case CPU_P5600:
1164         case CPU_PROAPTIV:
1165                 if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K))
1166                         alias_74k_erratum(c);
1167                 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1168                     (c->icache.waysize > PAGE_SIZE))
1169                         c->icache.flags |= MIPS_CACHE_ALIASES;
1170                 if (read_c0_config7() & MIPS_CONF7_AR) {
1171                         /*
1172                          * Effectively physically indexed dcache,
1173                          * thus no virtual aliases.
1174                         */
1175                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1176                         break;
1177                 }
1178         default:
1179                 if (c->dcache.waysize > PAGE_SIZE)
1180                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1181         }
1182
1183         switch (current_cpu_type()) {
1184         case CPU_20KC:
1185                 /*
1186                  * Some older 20Kc chips doesn't have the 'VI' bit in
1187                  * the config register.
1188                  */
1189                 c->icache.flags |= MIPS_CACHE_VTAG;
1190                 break;
1191
1192         case CPU_ALCHEMY:
1193                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1194                 break;
1195
1196         case CPU_LOONGSON2:
1197                 /*
1198                  * LOONGSON2 has 4 way icache, but when using indexed cache op,
1199                  * one op will act on all 4 ways
1200                  */
1201                 c->icache.ways = 1;
1202         }
1203
1204         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1205                icache_size >> 10,
1206                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1207                way_string[c->icache.ways], c->icache.linesz);
1208
1209         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1210                dcache_size >> 10, way_string[c->dcache.ways],
1211                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1212                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1213                         "cache aliases" : "no aliases",
1214                c->dcache.linesz);
1215 }
1216
1217 /*
1218  * If you even _breathe_ on this function, look at the gcc output and make sure
1219  * it does not pop things on and off the stack for the cache sizing loop that
1220  * executes in KSEG1 space or else you will crash and burn badly.  You have
1221  * been warned.
1222  */
1223 static int probe_scache(void)
1224 {
1225         unsigned long flags, addr, begin, end, pow2;
1226         unsigned int config = read_c0_config();
1227         struct cpuinfo_mips *c = &current_cpu_data;
1228
1229         if (config & CONF_SC)
1230                 return 0;
1231
1232         begin = (unsigned long) &_stext;
1233         begin &= ~((4 * 1024 * 1024) - 1);
1234         end = begin + (4 * 1024 * 1024);
1235
1236         /*
1237          * This is such a bitch, you'd think they would make it easy to do
1238          * this.  Away you daemons of stupidity!
1239          */
1240         local_irq_save(flags);
1241
1242         /* Fill each size-multiple cache line with a valid tag. */
1243         pow2 = (64 * 1024);
1244         for (addr = begin; addr < end; addr = (begin + pow2)) {
1245                 unsigned long *p = (unsigned long *) addr;
1246                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1247                 pow2 <<= 1;
1248         }
1249
1250         /* Load first line with zero (therefore invalid) tag. */
1251         write_c0_taglo(0);
1252         write_c0_taghi(0);
1253         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1254         cache_op(Index_Store_Tag_I, begin);
1255         cache_op(Index_Store_Tag_D, begin);
1256         cache_op(Index_Store_Tag_SD, begin);
1257
1258         /* Now search for the wrap around point. */
1259         pow2 = (128 * 1024);
1260         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1261                 cache_op(Index_Load_Tag_SD, addr);
1262                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1263                 if (!read_c0_taglo())
1264                         break;
1265                 pow2 <<= 1;
1266         }
1267         local_irq_restore(flags);
1268         addr -= begin;
1269
1270         scache_size = addr;
1271         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1272         c->scache.ways = 1;
1273         c->dcache.waybit = 0;           /* does not matter */
1274
1275         return 1;
1276 }
1277
1278 static void __init loongson2_sc_init(void)
1279 {
1280         struct cpuinfo_mips *c = &current_cpu_data;
1281
1282         scache_size = 512*1024;
1283         c->scache.linesz = 32;
1284         c->scache.ways = 4;
1285         c->scache.waybit = 0;
1286         c->scache.waysize = scache_size / (c->scache.ways);
1287         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1288         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1289                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1290
1291         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1292 }
1293
1294 extern int r5k_sc_init(void);
1295 extern int rm7k_sc_init(void);
1296 extern int mips_sc_init(void);
1297
1298 static void setup_scache(void)
1299 {
1300         struct cpuinfo_mips *c = &current_cpu_data;
1301         unsigned int config = read_c0_config();
1302         int sc_present = 0;
1303
1304         /*
1305          * Do the probing thing on R4000SC and R4400SC processors.  Other
1306          * processors don't have a S-cache that would be relevant to the
1307          * Linux memory management.
1308          */
1309         switch (current_cpu_type()) {
1310         case CPU_R4000SC:
1311         case CPU_R4000MC:
1312         case CPU_R4400SC:
1313         case CPU_R4400MC:
1314                 sc_present = run_uncached(probe_scache);
1315                 if (sc_present)
1316                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1317                 break;
1318
1319         case CPU_R10000:
1320         case CPU_R12000:
1321         case CPU_R14000:
1322                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1323                 c->scache.linesz = 64 << ((config >> 13) & 1);
1324                 c->scache.ways = 2;
1325                 c->scache.waybit= 0;
1326                 sc_present = 1;
1327                 break;
1328
1329         case CPU_R5000:
1330         case CPU_NEVADA:
1331 #ifdef CONFIG_R5000_CPU_SCACHE
1332                 r5k_sc_init();
1333 #endif
1334                 return;
1335
1336         case CPU_RM7000:
1337 #ifdef CONFIG_RM7000_CPU_SCACHE
1338                 rm7k_sc_init();
1339 #endif
1340                 return;
1341
1342         case CPU_LOONGSON2:
1343                 loongson2_sc_init();
1344                 return;
1345
1346         case CPU_XLP:
1347                 /* don't need to worry about L2, fully coherent */
1348                 return;
1349
1350         default:
1351                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1352                                     MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1353 #ifdef CONFIG_MIPS_CPU_SCACHE
1354                         if (mips_sc_init ()) {
1355                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1356                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1357                                        scache_size >> 10,
1358                                        way_string[c->scache.ways], c->scache.linesz);
1359                         }
1360 #else
1361                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1362                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1363 #endif
1364                         return;
1365                 }
1366                 sc_present = 0;
1367         }
1368
1369         if (!sc_present)
1370                 return;
1371
1372         /* compute a couple of other cache variables */
1373         c->scache.waysize = scache_size / c->scache.ways;
1374
1375         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1376
1377         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1378                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1379
1380         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1381 }
1382
1383 void au1x00_fixup_config_od(void)
1384 {
1385         /*
1386          * c0_config.od (bit 19) was write only (and read as 0)
1387          * on the early revisions of Alchemy SOCs.  It disables the bus
1388          * transaction overlapping and needs to be set to fix various errata.
1389          */
1390         switch (read_c0_prid()) {
1391         case 0x00030100: /* Au1000 DA */
1392         case 0x00030201: /* Au1000 HA */
1393         case 0x00030202: /* Au1000 HB */
1394         case 0x01030200: /* Au1500 AB */
1395         /*
1396          * Au1100 errata actually keeps silence about this bit, so we set it
1397          * just in case for those revisions that require it to be set according
1398          * to the (now gone) cpu table.
1399          */
1400         case 0x02030200: /* Au1100 AB */
1401         case 0x02030201: /* Au1100 BA */
1402         case 0x02030202: /* Au1100 BC */
1403                 set_c0_config(1 << 19);
1404                 break;
1405         }
1406 }
1407
1408 /* CP0 hazard avoidance. */
1409 #define NXP_BARRIER()                                                   \
1410          __asm__ __volatile__(                                          \
1411         ".set noreorder\n\t"                                            \
1412         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1413         ".set reorder\n\t")
1414
1415 static void nxp_pr4450_fixup_config(void)
1416 {
1417         unsigned long config0;
1418
1419         config0 = read_c0_config();
1420
1421         /* clear all three cache coherency fields */
1422         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1423         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1424                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1425                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1426         write_c0_config(config0);
1427         NXP_BARRIER();
1428 }
1429
1430 static int cca = -1;
1431
1432 static int __init cca_setup(char *str)
1433 {
1434         get_option(&str, &cca);
1435
1436         return 0;
1437 }
1438
1439 early_param("cca", cca_setup);
1440
1441 static void coherency_setup(void)
1442 {
1443         if (cca < 0 || cca > 7)
1444                 cca = read_c0_config() & CONF_CM_CMASK;
1445         _page_cachable_default = cca << _CACHE_SHIFT;
1446
1447         pr_debug("Using cache attribute %d\n", cca);
1448         change_c0_config(CONF_CM_CMASK, cca);
1449
1450         /*
1451          * c0_status.cu=0 specifies that updates by the sc instruction use
1452          * the coherency mode specified by the TLB; 1 means cachable
1453          * coherent update on write will be used.  Not all processors have
1454          * this bit and; some wire it to zero, others like Toshiba had the
1455          * silly idea of putting something else there ...
1456          */
1457         switch (current_cpu_type()) {
1458         case CPU_R4000PC:
1459         case CPU_R4000SC:
1460         case CPU_R4000MC:
1461         case CPU_R4400PC:
1462         case CPU_R4400SC:
1463         case CPU_R4400MC:
1464                 clear_c0_config(CONF_CU);
1465                 break;
1466         /*
1467          * We need to catch the early Alchemy SOCs with
1468          * the write-only co_config.od bit and set it back to one on:
1469          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1470          */
1471         case CPU_ALCHEMY:
1472                 au1x00_fixup_config_od();
1473                 break;
1474
1475         case PRID_IMP_PR4450:
1476                 nxp_pr4450_fixup_config();
1477                 break;
1478         }
1479 }
1480
1481 static void r4k_cache_error_setup(void)
1482 {
1483         extern char __weak except_vec2_generic;
1484         extern char __weak except_vec2_sb1;
1485
1486         switch (current_cpu_type()) {
1487         case CPU_SB1:
1488         case CPU_SB1A:
1489                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1490                 break;
1491
1492         default:
1493                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1494                 break;
1495         }
1496 }
1497
1498 void r4k_cache_init(void)
1499 {
1500         extern void build_clear_page(void);
1501         extern void build_copy_page(void);
1502         struct cpuinfo_mips *c = &current_cpu_data;
1503
1504         probe_pcache();
1505         setup_scache();
1506
1507         r4k_blast_dcache_page_setup();
1508         r4k_blast_dcache_page_indexed_setup();
1509         r4k_blast_dcache_setup();
1510         r4k_blast_icache_page_setup();
1511         r4k_blast_icache_page_indexed_setup();
1512         r4k_blast_icache_setup();
1513         r4k_blast_scache_page_setup();
1514         r4k_blast_scache_page_indexed_setup();
1515         r4k_blast_scache_setup();
1516 #ifdef CONFIG_EVA
1517         r4k_blast_dcache_user_page_setup();
1518         r4k_blast_icache_user_page_setup();
1519 #endif
1520
1521         /*
1522          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1523          * This code supports virtually indexed processors and will be
1524          * unnecessarily inefficient on physically indexed processors.
1525          */
1526         if (c->dcache.linesz)
1527                 shm_align_mask = max_t( unsigned long,
1528                                         c->dcache.sets * c->dcache.linesz - 1,
1529                                         PAGE_SIZE - 1);
1530         else
1531                 shm_align_mask = PAGE_SIZE-1;
1532
1533         __flush_cache_vmap      = r4k__flush_cache_vmap;
1534         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1535
1536         flush_cache_all         = cache_noop;
1537         __flush_cache_all       = r4k___flush_cache_all;
1538         flush_cache_mm          = r4k_flush_cache_mm;
1539         flush_cache_page        = r4k_flush_cache_page;
1540         flush_cache_range       = r4k_flush_cache_range;
1541
1542         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1543
1544         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1545         flush_icache_all        = r4k_flush_icache_all;
1546         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1547         flush_data_cache_page   = r4k_flush_data_cache_page;
1548         flush_icache_range      = r4k_flush_icache_range;
1549         local_flush_icache_range        = local_r4k_flush_icache_range;
1550
1551 #if defined(CONFIG_DMA_NONCOHERENT)
1552         if (coherentio) {
1553                 _dma_cache_wback_inv    = (void *)cache_noop;
1554                 _dma_cache_wback        = (void *)cache_noop;
1555                 _dma_cache_inv          = (void *)cache_noop;
1556         } else {
1557                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1558                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1559                 _dma_cache_inv          = r4k_dma_cache_inv;
1560         }
1561 #endif
1562
1563         build_clear_page();
1564         build_copy_page();
1565
1566         /*
1567          * We want to run CMP kernels on core with and without coherent
1568          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1569          * or not to flush caches.
1570          */
1571         local_r4k___flush_cache_all(NULL);
1572
1573         coherency_setup();
1574         board_cache_error_setup = r4k_cache_error_setup;
1575 }