2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
13 * ... and the days got worse and worse and now you see
14 * I've gone completly out of my mind.
16 * They're coming to take me a away haha
17 * they're coming to take me a away hoho hihi haha
18 * to the funny farm where code is beautiful all the time ...
20 * (Condolences to Napoleon XIV)
23 #include <linux/bug.h>
24 #include <linux/kernel.h>
25 #include <linux/types.h>
26 #include <linux/smp.h>
27 #include <linux/string.h>
28 #include <linux/init.h>
30 #include <asm/mmu_context.h>
35 * TLB load/store/modify handlers.
37 * Only the fastpath gets synthesized at runtime, the slowpath for
38 * do_page_fault remains normal asm.
40 extern void tlb_do_page_fault_0(void);
41 extern void tlb_do_page_fault_1(void);
44 static inline int r45k_bvahwbug(void)
46 /* XXX: We should probe for the presence of this bug, but we don't. */
50 static inline int r4k_250MHZhwbug(void)
52 /* XXX: We should probe for the presence of this bug, but we don't. */
56 static inline int __maybe_unused bcm1250_m3_war(void)
58 return BCM1250_M3_WAR;
61 static inline int __maybe_unused r10000_llsc_war(void)
63 return R10000_LLSC_WAR;
67 * Found by experiment: At least some revisions of the 4kc throw under
68 * some circumstances a machine check exception, triggered by invalid
69 * values in the index register. Delaying the tlbp instruction until
70 * after the next branch, plus adding an additional nop in front of
71 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
72 * why; it's not an issue caused by the core RTL.
75 static int __cpuinit m4kc_tlbp_war(void)
77 return (current_cpu_data.processor_id & 0xffff00) ==
78 (PRID_COMP_MIPS | PRID_IMP_4KC);
81 /* Handle labels (which must be positive integers). */
83 label_second_part = 1,
94 label_smp_pgtable_change,
95 label_r3000_write_probe_fail,
96 label_large_segbits_fault,
97 #ifdef CONFIG_HUGETLB_PAGE
98 label_tlb_huge_update,
102 UASM_L_LA(_second_part)
105 UASM_L_LA(_vmalloc_done)
106 UASM_L_LA(_tlbw_hazard)
108 UASM_L_LA(_tlbl_goaround1)
109 UASM_L_LA(_tlbl_goaround2)
110 UASM_L_LA(_nopage_tlbl)
111 UASM_L_LA(_nopage_tlbs)
112 UASM_L_LA(_nopage_tlbm)
113 UASM_L_LA(_smp_pgtable_change)
114 UASM_L_LA(_r3000_write_probe_fail)
115 UASM_L_LA(_large_segbits_fault)
116 #ifdef CONFIG_HUGETLB_PAGE
117 UASM_L_LA(_tlb_huge_update)
121 * For debug purposes.
123 static inline void dump_handler(const u32 *handler, int count)
127 pr_debug("\t.set push\n");
128 pr_debug("\t.set noreorder\n");
130 for (i = 0; i < count; i++)
131 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
133 pr_debug("\t.set pop\n");
136 /* The only general purpose registers allowed in TLB handlers. */
140 /* Some CP0 registers */
141 #define C0_INDEX 0, 0
142 #define C0_ENTRYLO0 2, 0
143 #define C0_TCBIND 2, 2
144 #define C0_ENTRYLO1 3, 0
145 #define C0_CONTEXT 4, 0
146 #define C0_PAGEMASK 5, 0
147 #define C0_BADVADDR 8, 0
148 #define C0_ENTRYHI 10, 0
150 #define C0_XCONTEXT 20, 0
153 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
155 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
158 /* The worst case length of the handler is around 18 instructions for
159 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
160 * Maximum space available is 32 instructions for R3000 and 64
161 * instructions for R4000.
163 * We deliberately chose a buffer size of 128, so we won't scribble
164 * over anything important on overflow before we panic.
166 static u32 tlb_handler[128] __cpuinitdata;
168 /* simply assume worst case size for labels and relocs */
169 static struct uasm_label labels[128] __cpuinitdata;
170 static struct uasm_reloc relocs[128] __cpuinitdata;
173 static int check_for_high_segbits __cpuinitdata;
176 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
178 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
179 * we cannot do r3000 under these circumstances.
183 * The R3000 TLB handler is simple.
185 static void __cpuinit build_r3000_tlb_refill_handler(void)
187 long pgdc = (long)pgd_current;
190 memset(tlb_handler, 0, sizeof(tlb_handler));
193 uasm_i_mfc0(&p, K0, C0_BADVADDR);
194 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
195 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
196 uasm_i_srl(&p, K0, K0, 22); /* load delay */
197 uasm_i_sll(&p, K0, K0, 2);
198 uasm_i_addu(&p, K1, K1, K0);
199 uasm_i_mfc0(&p, K0, C0_CONTEXT);
200 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
201 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
202 uasm_i_addu(&p, K1, K1, K0);
203 uasm_i_lw(&p, K0, 0, K1);
204 uasm_i_nop(&p); /* load delay */
205 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
206 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
207 uasm_i_tlbwr(&p); /* cp0 delay */
209 uasm_i_rfe(&p); /* branch delay */
211 if (p > tlb_handler + 32)
212 panic("TLB refill handler space exceeded");
214 pr_debug("Wrote TLB refill handler (%u instructions).\n",
215 (unsigned int)(p - tlb_handler));
217 memcpy((void *)ebase, tlb_handler, 0x80);
219 dump_handler((u32 *)ebase, 32);
221 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
224 * The R4000 TLB handler is much more complicated. We have two
225 * consecutive handler areas with 32 instructions space each.
226 * Since they aren't used at the same time, we can overflow in the
227 * other one.To keep things simple, we first assume linear space,
228 * then we relocate it to the final handler layout as needed.
230 static u32 final_handler[64] __cpuinitdata;
235 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
236 * 2. A timing hazard exists for the TLBP instruction.
238 * stalling_instruction
241 * The JTLB is being read for the TLBP throughout the stall generated by the
242 * previous instruction. This is not really correct as the stalling instruction
243 * can modify the address used to access the JTLB. The failure symptom is that
244 * the TLBP instruction will use an address created for the stalling instruction
245 * and not the address held in C0_ENHI and thus report the wrong results.
247 * The software work-around is to not allow the instruction preceding the TLBP
248 * to stall - make it an NOP or some other instruction guaranteed not to stall.
250 * Errata 2 will not be fixed. This errata is also on the R5000.
252 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
254 static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
256 switch (current_cpu_type()) {
257 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
274 * Write random or indexed TLB entry, and care about the hazards from
275 * the preceeding mtc0 and for the following eret.
277 enum tlb_write_entry { tlb_random, tlb_indexed };
279 static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
280 struct uasm_reloc **r,
281 enum tlb_write_entry wmode)
283 void(*tlbw)(u32 **) = NULL;
286 case tlb_random: tlbw = uasm_i_tlbwr; break;
287 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
290 if (cpu_has_mips_r2) {
291 if (cpu_has_mips_r2_exec_hazard)
297 switch (current_cpu_type()) {
305 * This branch uses up a mtc0 hazard nop slot and saves
306 * two nops after the tlbw instruction.
308 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
310 uasm_l_tlbw_hazard(l, *p);
355 uasm_i_nop(p); /* QED specifies 2 nops hazard */
357 * This branch uses up a mtc0 hazard nop slot and saves
358 * a nop after the tlbw instruction.
360 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
362 uasm_l_tlbw_hazard(l, *p);
375 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
376 * use of the JTLB for instructions should not occur for 4
377 * cpu cycles and use for data translations should not occur
417 panic("No TLB refill handler yet (CPU type: %d)",
418 current_cpu_data.cputype);
423 static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
426 if (kernel_uses_smartmips_rixi) {
427 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
428 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
430 #ifdef CONFIG_64BIT_PHYS_ADDR
431 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
433 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
438 #ifdef CONFIG_HUGETLB_PAGE
440 static __cpuinit void build_restore_pagemask(u32 **p,
441 struct uasm_reloc **r,
445 /* Reset default page size */
446 if (PM_DEFAULT_MASK >> 16) {
447 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
448 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
449 uasm_il_b(p, r, lid);
450 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
451 } else if (PM_DEFAULT_MASK) {
452 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
453 uasm_il_b(p, r, lid);
454 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
456 uasm_il_b(p, r, lid);
457 uasm_i_mtc0(p, 0, C0_PAGEMASK);
461 static __cpuinit void build_huge_tlb_write_entry(u32 **p,
462 struct uasm_label **l,
463 struct uasm_reloc **r,
465 enum tlb_write_entry wmode)
467 /* Set huge page tlb entry size */
468 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
469 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
470 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
472 build_tlb_write_entry(p, l, r, wmode);
474 build_restore_pagemask(p, r, tmp, label_leave);
478 * Check if Huge PTE is present, if so then jump to LABEL.
480 static void __cpuinit
481 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
482 unsigned int pmd, int lid)
484 UASM_i_LW(p, tmp, 0, pmd);
485 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
486 uasm_il_bnez(p, r, tmp, lid);
489 static __cpuinit void build_huge_update_entries(u32 **p,
496 * A huge PTE describes an area the size of the
497 * configured huge page size. This is twice the
498 * of the large TLB entry size we intend to use.
499 * A TLB entry half the size of the configured
500 * huge page size is configured into entrylo0
501 * and entrylo1 to cover the contiguous huge PTE
504 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
506 /* We can clobber tmp. It isn't used after this.*/
508 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
510 build_convert_pte_to_entrylo(p, pte);
511 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
512 /* convert to entrylo1 */
514 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
516 UASM_i_ADDU(p, pte, pte, tmp);
518 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
521 static __cpuinit void build_huge_handler_tail(u32 **p,
522 struct uasm_reloc **r,
523 struct uasm_label **l,
528 UASM_i_SC(p, pte, 0, ptr);
529 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
530 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
532 UASM_i_SW(p, pte, 0, ptr);
534 build_huge_update_entries(p, pte, ptr);
535 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed);
537 #endif /* CONFIG_HUGETLB_PAGE */
541 * TMP and PTR are scratch.
542 * TMP will be clobbered, PTR will hold the pmd entry.
544 static void __cpuinit
545 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
546 unsigned int tmp, unsigned int ptr)
548 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
549 long pgdc = (long)pgd_current;
552 * The vmalloc handling is not in the hotpath.
554 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
556 if (check_for_high_segbits) {
558 * The kernel currently implicitely assumes that the
559 * MIPS SEGBITS parameter for the processor is
560 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
561 * allocate virtual addresses outside the maximum
562 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
563 * that doesn't prevent user code from accessing the
564 * higher xuseg addresses. Here, we make sure that
565 * everything but the lower xuseg addresses goes down
566 * the module_alloc/vmalloc path.
568 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
569 uasm_il_bnez(p, r, ptr, label_vmalloc);
571 uasm_il_bltz(p, r, tmp, label_vmalloc);
573 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
575 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
577 * &pgd << 11 stored in CONTEXT [23..63].
579 UASM_i_MFC0(p, ptr, C0_CONTEXT);
580 uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
581 uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
582 uasm_i_drotr(p, ptr, ptr, 11);
583 #elif defined(CONFIG_SMP)
584 # ifdef CONFIG_MIPS_MT_SMTC
586 * SMTC uses TCBind value as "CPU" index
588 uasm_i_mfc0(p, ptr, C0_TCBIND);
589 uasm_i_dsrl_safe(p, ptr, ptr, 19);
592 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
595 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
596 uasm_i_dsrl_safe(p, ptr, ptr, 23);
598 UASM_i_LA_mostly(p, tmp, pgdc);
599 uasm_i_daddu(p, ptr, ptr, tmp);
600 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
601 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
603 UASM_i_LA_mostly(p, ptr, pgdc);
604 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
607 uasm_l_vmalloc_done(l, *p);
609 /* get pgd offset in bytes */
610 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
612 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
613 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
614 #ifndef __PAGETABLE_PMD_FOLDED
615 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
616 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
617 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
618 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
619 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
623 enum vmalloc64_mode {not_refill, refill};
625 * BVADDR is the faulting address, PTR is scratch.
626 * PTR will hold the pgd for vmalloc.
628 static void __cpuinit
629 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
630 unsigned int bvaddr, unsigned int ptr,
631 enum vmalloc64_mode mode)
633 long swpd = (long)swapper_pg_dir;
634 int single_insn_swpd;
635 int did_vmalloc_branch = 0;
637 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
639 uasm_l_vmalloc(l, *p);
641 if (mode == refill && check_for_high_segbits) {
642 if (single_insn_swpd) {
643 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
644 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
645 did_vmalloc_branch = 1;
648 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
651 if (!did_vmalloc_branch) {
652 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
653 uasm_il_b(p, r, label_vmalloc_done);
654 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
656 UASM_i_LA_mostly(p, ptr, swpd);
657 uasm_il_b(p, r, label_vmalloc_done);
658 if (uasm_in_compat_space_p(swpd))
659 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
661 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
664 if (mode == refill && check_for_high_segbits) {
665 uasm_l_large_segbits_fault(l, *p);
667 * We get here if we are an xsseg address, or if we are
668 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
670 * Ignoring xsseg (assume disabled so would generate
671 * (address errors?), the only remaining possibility
672 * is the upper xuseg addresses. On processors with
673 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
674 * addresses would have taken an address error. We try
675 * to mimic that here by taking a load/istream page
678 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
684 #else /* !CONFIG_64BIT */
687 * TMP and PTR are scratch.
688 * TMP will be clobbered, PTR will hold the pgd entry.
690 static void __cpuinit __maybe_unused
691 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
693 long pgdc = (long)pgd_current;
695 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
697 #ifdef CONFIG_MIPS_MT_SMTC
699 * SMTC uses TCBind value as "CPU" index
701 uasm_i_mfc0(p, ptr, C0_TCBIND);
702 UASM_i_LA_mostly(p, tmp, pgdc);
703 uasm_i_srl(p, ptr, ptr, 19);
706 * smp_processor_id() << 3 is stored in CONTEXT.
708 uasm_i_mfc0(p, ptr, C0_CONTEXT);
709 UASM_i_LA_mostly(p, tmp, pgdc);
710 uasm_i_srl(p, ptr, ptr, 23);
712 uasm_i_addu(p, ptr, tmp, ptr);
714 UASM_i_LA_mostly(p, ptr, pgdc);
716 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
717 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
718 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
719 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
720 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
723 #endif /* !CONFIG_64BIT */
725 static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
727 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
728 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
730 switch (current_cpu_type()) {
747 UASM_i_SRL(p, ctx, ctx, shift);
748 uasm_i_andi(p, ctx, ctx, mask);
751 static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
754 * Bug workaround for the Nevada. It seems as if under certain
755 * circumstances the move from cp0_context might produce a
756 * bogus result when the mfc0 instruction and its consumer are
757 * in a different cacheline or a load instruction, probably any
758 * memory reference, is between them.
760 switch (current_cpu_type()) {
762 UASM_i_LW(p, ptr, 0, ptr);
763 GET_CONTEXT(p, tmp); /* get context reg */
767 GET_CONTEXT(p, tmp); /* get context reg */
768 UASM_i_LW(p, ptr, 0, ptr);
772 build_adjust_context(p, tmp);
773 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
776 static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
780 * 64bit address support (36bit on a 32bit CPU) in a 32bit
781 * Kernel is a special case. Only a few CPUs use it.
783 #ifdef CONFIG_64BIT_PHYS_ADDR
784 if (cpu_has_64bits) {
785 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
786 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
787 if (kernel_uses_smartmips_rixi) {
788 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
789 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
790 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
791 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
792 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
794 uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
795 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
796 uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
798 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
800 int pte_off_even = sizeof(pte_t) / 2;
801 int pte_off_odd = pte_off_even + sizeof(pte_t);
803 /* The pte entries are pre-shifted */
804 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
805 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
806 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
807 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
810 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
811 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
813 build_tlb_probe_entry(p);
814 if (kernel_uses_smartmips_rixi) {
815 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
816 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
817 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
818 if (r4k_250MHZhwbug())
819 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
820 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
821 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
823 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
824 if (r4k_250MHZhwbug())
825 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
826 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
827 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
829 uasm_i_mfc0(p, tmp, C0_INDEX);
831 if (r4k_250MHZhwbug())
832 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
833 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
838 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
839 * because EXL == 0. If we wrap, we can also use the 32 instruction
840 * slots before the XTLB refill exception handler which belong to the
841 * unused TLB refill exception.
843 #define MIPS64_REFILL_INSNS 32
845 static void __cpuinit build_r4000_tlb_refill_handler(void)
847 u32 *p = tlb_handler;
848 struct uasm_label *l = labels;
849 struct uasm_reloc *r = relocs;
851 unsigned int final_len;
853 memset(tlb_handler, 0, sizeof(tlb_handler));
854 memset(labels, 0, sizeof(labels));
855 memset(relocs, 0, sizeof(relocs));
856 memset(final_handler, 0, sizeof(final_handler));
859 * create the plain linear handler
861 if (bcm1250_m3_war()) {
862 unsigned int segbits = 44;
864 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
865 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
866 uasm_i_xor(&p, K0, K0, K1);
867 uasm_i_dsrl_safe(&p, K1, K0, 62);
868 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
869 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
870 uasm_i_or(&p, K0, K0, K1);
871 uasm_il_bnez(&p, &r, K0, label_leave);
872 /* No need for uasm_i_nop */
876 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
878 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
881 #ifdef CONFIG_HUGETLB_PAGE
882 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
885 build_get_ptep(&p, K0, K1);
886 build_update_entries(&p, K0, K1);
887 build_tlb_write_entry(&p, &l, &r, tlb_random);
889 uasm_i_eret(&p); /* return from trap */
891 #ifdef CONFIG_HUGETLB_PAGE
892 uasm_l_tlb_huge_update(&l, p);
893 UASM_i_LW(&p, K0, 0, K1);
894 build_huge_update_entries(&p, K0, K1);
895 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random);
899 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, refill);
903 * Overflow check: For the 64bit handler, we need at least one
904 * free instruction slot for the wrap-around branch. In worst
905 * case, if the intended insertion point is a delay slot, we
906 * need three, with the second nop'ed and the third being
909 /* Loongson2 ebase is different than r4k, we have more space */
910 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
911 if ((p - tlb_handler) > 64)
912 panic("TLB refill handler space exceeded");
914 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
915 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
916 && uasm_insn_has_bdelay(relocs,
917 tlb_handler + MIPS64_REFILL_INSNS - 3)))
918 panic("TLB refill handler space exceeded");
922 * Now fold the handler in the TLB refill handler space.
924 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
926 /* Simplest case, just copy the handler. */
927 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
928 final_len = p - tlb_handler;
929 #else /* CONFIG_64BIT */
930 f = final_handler + MIPS64_REFILL_INSNS;
931 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
932 /* Just copy the handler. */
933 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
934 final_len = p - tlb_handler;
936 #if defined(CONFIG_HUGETLB_PAGE)
937 const enum label_id ls = label_tlb_huge_update;
939 const enum label_id ls = label_vmalloc;
945 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
947 BUG_ON(i == ARRAY_SIZE(labels));
948 split = labels[i].addr;
951 * See if we have overflown one way or the other.
953 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
954 split < p - MIPS64_REFILL_INSNS)
959 * Split two instructions before the end. One
960 * for the branch and one for the instruction
963 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
966 * If the branch would fall in a delay slot,
967 * we must back up an additional instruction
968 * so that it is no longer in a delay slot.
970 if (uasm_insn_has_bdelay(relocs, split - 1))
973 /* Copy first part of the handler. */
974 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
975 f += split - tlb_handler;
979 uasm_l_split(&l, final_handler);
980 uasm_il_b(&f, &r, label_split);
981 if (uasm_insn_has_bdelay(relocs, split))
984 uasm_copy_handler(relocs, labels,
985 split, split + 1, f);
986 uasm_move_labels(labels, f, f + 1, -1);
992 /* Copy the rest of the handler. */
993 uasm_copy_handler(relocs, labels, split, p, final_handler);
994 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
997 #endif /* CONFIG_64BIT */
999 uasm_resolve_relocs(relocs, labels);
1000 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1003 memcpy((void *)ebase, final_handler, 0x100);
1005 dump_handler((u32 *)ebase, 64);
1009 * 128 instructions for the fastpath handler is generous and should
1010 * never be exceeded.
1012 #define FASTPATH_SIZE 128
1014 u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
1015 u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
1016 u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
1018 static void __cpuinit
1019 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1022 # ifdef CONFIG_64BIT_PHYS_ADDR
1024 uasm_i_lld(p, pte, 0, ptr);
1027 UASM_i_LL(p, pte, 0, ptr);
1029 # ifdef CONFIG_64BIT_PHYS_ADDR
1031 uasm_i_ld(p, pte, 0, ptr);
1034 UASM_i_LW(p, pte, 0, ptr);
1038 static void __cpuinit
1039 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1042 #ifdef CONFIG_64BIT_PHYS_ADDR
1043 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1046 uasm_i_ori(p, pte, pte, mode);
1048 # ifdef CONFIG_64BIT_PHYS_ADDR
1050 uasm_i_scd(p, pte, 0, ptr);
1053 UASM_i_SC(p, pte, 0, ptr);
1055 if (r10000_llsc_war())
1056 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1058 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1060 # ifdef CONFIG_64BIT_PHYS_ADDR
1061 if (!cpu_has_64bits) {
1062 /* no uasm_i_nop needed */
1063 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1064 uasm_i_ori(p, pte, pte, hwmode);
1065 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1066 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1067 /* no uasm_i_nop needed */
1068 uasm_i_lw(p, pte, 0, ptr);
1075 # ifdef CONFIG_64BIT_PHYS_ADDR
1077 uasm_i_sd(p, pte, 0, ptr);
1080 UASM_i_SW(p, pte, 0, ptr);
1082 # ifdef CONFIG_64BIT_PHYS_ADDR
1083 if (!cpu_has_64bits) {
1084 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1085 uasm_i_ori(p, pte, pte, hwmode);
1086 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1087 uasm_i_lw(p, pte, 0, ptr);
1094 * Check if PTE is present, if not then jump to LABEL. PTR points to
1095 * the page table where this PTE is located, PTE will be re-loaded
1096 * with it's original value.
1098 static void __cpuinit
1099 build_pte_present(u32 **p, struct uasm_reloc **r,
1100 unsigned int pte, unsigned int ptr, enum label_id lid)
1102 if (kernel_uses_smartmips_rixi) {
1103 uasm_i_andi(p, pte, pte, _PAGE_PRESENT);
1104 uasm_il_beqz(p, r, pte, lid);
1106 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1107 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1108 uasm_il_bnez(p, r, pte, lid);
1110 iPTE_LW(p, pte, ptr);
1113 /* Make PTE valid, store result in PTR. */
1114 static void __cpuinit
1115 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1118 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1120 iPTE_SW(p, r, pte, ptr, mode);
1124 * Check if PTE can be written to, if not branch to LABEL. Regardless
1125 * restore PTE with value from PTR when done.
1127 static void __cpuinit
1128 build_pte_writable(u32 **p, struct uasm_reloc **r,
1129 unsigned int pte, unsigned int ptr, enum label_id lid)
1131 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1132 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1133 uasm_il_bnez(p, r, pte, lid);
1134 iPTE_LW(p, pte, ptr);
1137 /* Make PTE writable, update software status bits as well, then store
1140 static void __cpuinit
1141 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1144 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1147 iPTE_SW(p, r, pte, ptr, mode);
1151 * Check if PTE can be modified, if not branch to LABEL. Regardless
1152 * restore PTE with value from PTR when done.
1154 static void __cpuinit
1155 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1156 unsigned int pte, unsigned int ptr, enum label_id lid)
1158 uasm_i_andi(p, pte, pte, _PAGE_WRITE);
1159 uasm_il_beqz(p, r, pte, lid);
1160 iPTE_LW(p, pte, ptr);
1163 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1165 * R3000 style TLB load/store/modify handlers.
1169 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1172 static void __cpuinit
1173 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1175 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1176 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1179 uasm_i_rfe(p); /* branch delay */
1183 * This places the pte into ENTRYLO0 and writes it with tlbwi
1184 * or tlbwr as appropriate. This is because the index register
1185 * may have the probe fail bit set as a result of a trap on a
1186 * kseg2 access, i.e. without refill. Then it returns.
1188 static void __cpuinit
1189 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1190 struct uasm_reloc **r, unsigned int pte,
1193 uasm_i_mfc0(p, tmp, C0_INDEX);
1194 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1195 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1196 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1197 uasm_i_tlbwi(p); /* cp0 delay */
1199 uasm_i_rfe(p); /* branch delay */
1200 uasm_l_r3000_write_probe_fail(l, *p);
1201 uasm_i_tlbwr(p); /* cp0 delay */
1203 uasm_i_rfe(p); /* branch delay */
1206 static void __cpuinit
1207 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1210 long pgdc = (long)pgd_current;
1212 uasm_i_mfc0(p, pte, C0_BADVADDR);
1213 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1214 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1215 uasm_i_srl(p, pte, pte, 22); /* load delay */
1216 uasm_i_sll(p, pte, pte, 2);
1217 uasm_i_addu(p, ptr, ptr, pte);
1218 uasm_i_mfc0(p, pte, C0_CONTEXT);
1219 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1220 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1221 uasm_i_addu(p, ptr, ptr, pte);
1222 uasm_i_lw(p, pte, 0, ptr);
1223 uasm_i_tlbp(p); /* load delay */
1226 static void __cpuinit build_r3000_tlb_load_handler(void)
1228 u32 *p = handle_tlbl;
1229 struct uasm_label *l = labels;
1230 struct uasm_reloc *r = relocs;
1232 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1233 memset(labels, 0, sizeof(labels));
1234 memset(relocs, 0, sizeof(relocs));
1236 build_r3000_tlbchange_handler_head(&p, K0, K1);
1237 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1238 uasm_i_nop(&p); /* load delay */
1239 build_make_valid(&p, &r, K0, K1);
1240 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1242 uasm_l_nopage_tlbl(&l, p);
1243 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1246 if ((p - handle_tlbl) > FASTPATH_SIZE)
1247 panic("TLB load handler fastpath space exceeded");
1249 uasm_resolve_relocs(relocs, labels);
1250 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1251 (unsigned int)(p - handle_tlbl));
1253 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1256 static void __cpuinit build_r3000_tlb_store_handler(void)
1258 u32 *p = handle_tlbs;
1259 struct uasm_label *l = labels;
1260 struct uasm_reloc *r = relocs;
1262 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1263 memset(labels, 0, sizeof(labels));
1264 memset(relocs, 0, sizeof(relocs));
1266 build_r3000_tlbchange_handler_head(&p, K0, K1);
1267 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1268 uasm_i_nop(&p); /* load delay */
1269 build_make_write(&p, &r, K0, K1);
1270 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1272 uasm_l_nopage_tlbs(&l, p);
1273 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1276 if ((p - handle_tlbs) > FASTPATH_SIZE)
1277 panic("TLB store handler fastpath space exceeded");
1279 uasm_resolve_relocs(relocs, labels);
1280 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1281 (unsigned int)(p - handle_tlbs));
1283 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1286 static void __cpuinit build_r3000_tlb_modify_handler(void)
1288 u32 *p = handle_tlbm;
1289 struct uasm_label *l = labels;
1290 struct uasm_reloc *r = relocs;
1292 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1293 memset(labels, 0, sizeof(labels));
1294 memset(relocs, 0, sizeof(relocs));
1296 build_r3000_tlbchange_handler_head(&p, K0, K1);
1297 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1298 uasm_i_nop(&p); /* load delay */
1299 build_make_write(&p, &r, K0, K1);
1300 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1302 uasm_l_nopage_tlbm(&l, p);
1303 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1306 if ((p - handle_tlbm) > FASTPATH_SIZE)
1307 panic("TLB modify handler fastpath space exceeded");
1309 uasm_resolve_relocs(relocs, labels);
1310 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1311 (unsigned int)(p - handle_tlbm));
1313 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1315 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1318 * R4000 style TLB load/store/modify handlers.
1320 static void __cpuinit
1321 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1322 struct uasm_reloc **r, unsigned int pte,
1326 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1328 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1331 #ifdef CONFIG_HUGETLB_PAGE
1333 * For huge tlb entries, pmd doesn't contain an address but
1334 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1335 * see if we need to jump to huge tlb processing.
1337 build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update);
1340 UASM_i_MFC0(p, pte, C0_BADVADDR);
1341 UASM_i_LW(p, ptr, 0, ptr);
1342 UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1343 uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1344 UASM_i_ADDU(p, ptr, ptr, pte);
1347 uasm_l_smp_pgtable_change(l, *p);
1349 iPTE_LW(p, pte, ptr); /* get even pte */
1350 if (!m4kc_tlbp_war())
1351 build_tlb_probe_entry(p);
1354 static void __cpuinit
1355 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1356 struct uasm_reloc **r, unsigned int tmp,
1359 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1360 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1361 build_update_entries(p, tmp, ptr);
1362 build_tlb_write_entry(p, l, r, tlb_indexed);
1363 uasm_l_leave(l, *p);
1364 uasm_i_eret(p); /* return from trap */
1367 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1371 static void __cpuinit build_r4000_tlb_load_handler(void)
1373 u32 *p = handle_tlbl;
1374 struct uasm_label *l = labels;
1375 struct uasm_reloc *r = relocs;
1377 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1378 memset(labels, 0, sizeof(labels));
1379 memset(relocs, 0, sizeof(relocs));
1381 if (bcm1250_m3_war()) {
1382 unsigned int segbits = 44;
1384 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1385 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1386 uasm_i_xor(&p, K0, K0, K1);
1387 uasm_i_dsrl_safe(&p, K1, K0, 62);
1388 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1389 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1390 uasm_i_or(&p, K0, K0, K1);
1391 uasm_il_bnez(&p, &r, K0, label_leave);
1392 /* No need for uasm_i_nop */
1395 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1396 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1397 if (m4kc_tlbp_war())
1398 build_tlb_probe_entry(&p);
1400 if (kernel_uses_smartmips_rixi) {
1402 * If the page is not _PAGE_VALID, RI or XI could not
1403 * have triggered it. Skip the expensive test..
1405 uasm_i_andi(&p, K0, K0, _PAGE_VALID);
1406 uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1);
1410 /* Examine entrylo 0 or 1 based on ptr. */
1411 uasm_i_andi(&p, K0, K1, sizeof(pte_t));
1412 uasm_i_beqz(&p, K0, 8);
1414 UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/
1415 UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */
1417 * If the entryLo (now in K0) is valid (bit 1), RI or
1418 * XI must have triggered it.
1420 uasm_i_andi(&p, K0, K0, 2);
1421 uasm_il_bnez(&p, &r, K0, label_nopage_tlbl);
1423 uasm_l_tlbl_goaround1(&l, p);
1424 /* Reload the PTE value */
1425 iPTE_LW(&p, K0, K1);
1427 build_make_valid(&p, &r, K0, K1);
1428 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1430 #ifdef CONFIG_HUGETLB_PAGE
1432 * This is the entry point when build_r4000_tlbchange_handler_head
1433 * spots a huge page.
1435 uasm_l_tlb_huge_update(&l, p);
1436 iPTE_LW(&p, K0, K1);
1437 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1438 build_tlb_probe_entry(&p);
1440 if (kernel_uses_smartmips_rixi) {
1442 * If the page is not _PAGE_VALID, RI or XI could not
1443 * have triggered it. Skip the expensive test..
1445 uasm_i_andi(&p, K0, K0, _PAGE_VALID);
1446 uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2);
1450 /* Examine entrylo 0 or 1 based on ptr. */
1451 uasm_i_andi(&p, K0, K1, sizeof(pte_t));
1452 uasm_i_beqz(&p, K0, 8);
1454 UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/
1455 UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */
1457 * If the entryLo (now in K0) is valid (bit 1), RI or
1458 * XI must have triggered it.
1460 uasm_i_andi(&p, K0, K0, 2);
1461 uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2);
1462 /* Reload the PTE value */
1463 iPTE_LW(&p, K0, K1);
1466 * We clobbered C0_PAGEMASK, restore it. On the other branch
1467 * it is restored in build_huge_tlb_write_entry.
1469 build_restore_pagemask(&p, &r, K0, label_nopage_tlbl);
1471 uasm_l_tlbl_goaround2(&l, p);
1473 uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID));
1474 build_huge_handler_tail(&p, &r, &l, K0, K1);
1477 uasm_l_nopage_tlbl(&l, p);
1478 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1481 if ((p - handle_tlbl) > FASTPATH_SIZE)
1482 panic("TLB load handler fastpath space exceeded");
1484 uasm_resolve_relocs(relocs, labels);
1485 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1486 (unsigned int)(p - handle_tlbl));
1488 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1491 static void __cpuinit build_r4000_tlb_store_handler(void)
1493 u32 *p = handle_tlbs;
1494 struct uasm_label *l = labels;
1495 struct uasm_reloc *r = relocs;
1497 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1498 memset(labels, 0, sizeof(labels));
1499 memset(relocs, 0, sizeof(relocs));
1501 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1502 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1503 if (m4kc_tlbp_war())
1504 build_tlb_probe_entry(&p);
1505 build_make_write(&p, &r, K0, K1);
1506 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1508 #ifdef CONFIG_HUGETLB_PAGE
1510 * This is the entry point when
1511 * build_r4000_tlbchange_handler_head spots a huge page.
1513 uasm_l_tlb_huge_update(&l, p);
1514 iPTE_LW(&p, K0, K1);
1515 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1516 build_tlb_probe_entry(&p);
1517 uasm_i_ori(&p, K0, K0,
1518 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
1519 build_huge_handler_tail(&p, &r, &l, K0, K1);
1522 uasm_l_nopage_tlbs(&l, p);
1523 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1526 if ((p - handle_tlbs) > FASTPATH_SIZE)
1527 panic("TLB store handler fastpath space exceeded");
1529 uasm_resolve_relocs(relocs, labels);
1530 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1531 (unsigned int)(p - handle_tlbs));
1533 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1536 static void __cpuinit build_r4000_tlb_modify_handler(void)
1538 u32 *p = handle_tlbm;
1539 struct uasm_label *l = labels;
1540 struct uasm_reloc *r = relocs;
1542 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1543 memset(labels, 0, sizeof(labels));
1544 memset(relocs, 0, sizeof(relocs));
1546 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1547 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1548 if (m4kc_tlbp_war())
1549 build_tlb_probe_entry(&p);
1550 /* Present and writable bits set, set accessed and dirty bits. */
1551 build_make_write(&p, &r, K0, K1);
1552 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1554 #ifdef CONFIG_HUGETLB_PAGE
1556 * This is the entry point when
1557 * build_r4000_tlbchange_handler_head spots a huge page.
1559 uasm_l_tlb_huge_update(&l, p);
1560 iPTE_LW(&p, K0, K1);
1561 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1562 build_tlb_probe_entry(&p);
1563 uasm_i_ori(&p, K0, K0,
1564 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
1565 build_huge_handler_tail(&p, &r, &l, K0, K1);
1568 uasm_l_nopage_tlbm(&l, p);
1569 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1572 if ((p - handle_tlbm) > FASTPATH_SIZE)
1573 panic("TLB modify handler fastpath space exceeded");
1575 uasm_resolve_relocs(relocs, labels);
1576 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1577 (unsigned int)(p - handle_tlbm));
1579 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1582 void __cpuinit build_tlb_refill_handler(void)
1585 * The refill handler is generated per-CPU, multi-node systems
1586 * may have local storage for it. The other handlers are only
1589 static int run_once = 0;
1592 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1595 switch (current_cpu_type()) {
1603 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1604 build_r3000_tlb_refill_handler();
1606 build_r3000_tlb_load_handler();
1607 build_r3000_tlb_store_handler();
1608 build_r3000_tlb_modify_handler();
1612 panic("No R3000 TLB refill handler");
1618 panic("No R6000 TLB refill handler yet");
1622 panic("No R8000 TLB refill handler yet");
1626 build_r4000_tlb_refill_handler();
1628 build_r4000_tlb_load_handler();
1629 build_r4000_tlb_store_handler();
1630 build_r4000_tlb_modify_handler();
1636 void __cpuinit flush_tlb_handlers(void)
1638 local_flush_icache_range((unsigned long)handle_tlbl,
1639 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
1640 local_flush_icache_range((unsigned long)handle_tlbs,
1641 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
1642 local_flush_icache_range((unsigned long)handle_tlbm,
1643 (unsigned long)handle_tlbm + sizeof(handle_tlbm));