2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
16 #include <linux/kernel.h>
17 #include <linux/types.h>
22 #define UASM_ISA _UASM_ISA_MICROMIPS
29 #define SCIMM_MASK 0x3ff
32 /* This macro sets the non-variable bits of an instruction. */
33 #define M(a, b, c, d, e, f) \
41 /* Define these when we are not the ISA the kernel is being compiled with. */
42 #ifndef CONFIG_CPU_MICROMIPS
43 #define MM_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off)
44 #define MM_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off)
45 #define MM_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off)
46 #define MM_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off)
51 static struct insn insn_table_MM[] = {
52 { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD },
53 { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
54 { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD },
55 { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
56 { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
58 { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM },
60 { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM },
62 { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
63 { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
65 { insn_daddiu, 0, 0 },
69 { insn_dsll32, 0, 0 },
72 { insn_dsrl32, 0, 0 },
74 { insn_drotr32, 0, 0 },
76 { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 },
77 { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE },
78 { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE },
79 { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM },
80 { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM },
81 { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS },
83 { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM },
85 { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM },
86 { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
87 { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
88 { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
89 { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },
90 { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
91 { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM },
93 { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM },
96 { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },
97 { insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },
98 { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },
99 { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD },
100 { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD },
101 { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD },
102 { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
103 { insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS },
104 { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 },
105 { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },
106 { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },
107 { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 },
108 { insn_wait, M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM },
109 { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },
110 { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
112 { insn_dinsm, 0, 0 },
113 { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
114 { insn_bbit0, 0, 0 },
115 { insn_bbit1, 0, 0 },
118 { insn_invalid, 0, 0 }
123 static inline u32 build_bimm(s32 arg)
125 WARN(arg > 0xffff || arg < -0x10000,
126 KERN_WARNING "Micro-assembler field overflow\n");
128 WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
130 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff);
133 static inline u32 build_jimm(u32 arg)
136 WARN(arg & ~((JIMM_MASK << 2) | 1),
137 KERN_WARNING "Micro-assembler field overflow\n");
139 return (arg >> 1) & JIMM_MASK;
143 * The order of opcode arguments is implicitly left to right,
144 * starting with RS and ending with FUNC or IMM.
146 static void build_insn(u32 **buf, enum opcode opc, ...)
148 struct insn *ip = NULL;
153 for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++)
154 if (insn_table_MM[i].opcode == opc) {
155 ip = &insn_table_MM[i];
159 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
160 panic("Unsupported Micro-assembler instruction %d", opc);
164 if (ip->fields & RS) {
165 if (opc == insn_mfc0 || opc == insn_mtc0)
166 op |= build_rt(va_arg(ap, u32));
168 op |= build_rs(va_arg(ap, u32));
170 if (ip->fields & RT) {
171 if (opc == insn_mfc0 || opc == insn_mtc0)
172 op |= build_rs(va_arg(ap, u32));
174 op |= build_rt(va_arg(ap, u32));
177 op |= build_rd(va_arg(ap, u32));
179 op |= build_re(va_arg(ap, u32));
180 if (ip->fields & SIMM)
181 op |= build_simm(va_arg(ap, s32));
182 if (ip->fields & UIMM)
183 op |= build_uimm(va_arg(ap, u32));
184 if (ip->fields & BIMM)
185 op |= build_bimm(va_arg(ap, s32));
186 if (ip->fields & JIMM)
187 op |= build_jimm(va_arg(ap, u32));
188 if (ip->fields & FUNC)
189 op |= build_func(va_arg(ap, u32));
190 if (ip->fields & SET)
191 op |= build_set(va_arg(ap, u32));
192 if (ip->fields & SCIMM)
193 op |= build_scimm(va_arg(ap, u32));
196 #ifdef CONFIG_CPU_LITTLE_ENDIAN
197 **buf = ((op & 0xffff) << 16) | (op >> 16);
205 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
207 long laddr = (long)lab->addr;
208 long raddr = (long)rel->addr;
212 #ifdef CONFIG_CPU_LITTLE_ENDIAN
213 *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16);
215 *rel->addr |= build_bimm(laddr - (raddr + 4));
220 panic("Unsupported Micro-assembler relocation %d",