2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
36 #define IMM_MASK 0xffff
38 #define JIMM_MASK 0x3ffffff
40 #define FUNC_MASK 0x3f
47 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
48 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
49 insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
50 insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
51 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
52 insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
53 insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx,
54 insn_mfc0, insn_mfhi, insn_mtc0, insn_mul, insn_or, insn_ori, insn_pref,
55 insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv,
56 insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu,
57 insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi,
58 insn_tlbwr, insn_wait, insn_wsbh, insn_xor, insn_xori, insn_yield,
67 static inline u32 build_rs(u32 arg)
69 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
71 return (arg & RS_MASK) << RS_SH;
74 static inline u32 build_rt(u32 arg)
76 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
78 return (arg & RT_MASK) << RT_SH;
81 static inline u32 build_rd(u32 arg)
83 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
85 return (arg & RD_MASK) << RD_SH;
88 static inline u32 build_re(u32 arg)
90 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
92 return (arg & RE_MASK) << RE_SH;
95 static inline u32 build_simm(s32 arg)
97 WARN(arg > 0x7fff || arg < -0x8000,
98 KERN_WARNING "Micro-assembler field overflow\n");
103 static inline u32 build_uimm(u32 arg)
105 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
107 return arg & IMM_MASK;
110 static inline u32 build_scimm(u32 arg)
112 WARN(arg & ~SCIMM_MASK,
113 KERN_WARNING "Micro-assembler field overflow\n");
115 return (arg & SCIMM_MASK) << SCIMM_SH;
118 static inline u32 build_func(u32 arg)
120 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
122 return arg & FUNC_MASK;
125 static inline u32 build_set(u32 arg)
127 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
129 return arg & SET_MASK;
132 static void build_insn(u32 **buf, enum opcode opc, ...);
134 #define I_u1u2u3(op) \
137 build_insn(buf, insn##op, a, b, c); \
139 UASM_EXPORT_SYMBOL(uasm_i##op);
141 #define I_u2u1u3(op) \
144 build_insn(buf, insn##op, b, a, c); \
146 UASM_EXPORT_SYMBOL(uasm_i##op);
148 #define I_u3u2u1(op) \
151 build_insn(buf, insn##op, c, b, a); \
153 UASM_EXPORT_SYMBOL(uasm_i##op);
155 #define I_u3u1u2(op) \
158 build_insn(buf, insn##op, b, c, a); \
160 UASM_EXPORT_SYMBOL(uasm_i##op);
162 #define I_u1u2s3(op) \
165 build_insn(buf, insn##op, a, b, c); \
167 UASM_EXPORT_SYMBOL(uasm_i##op);
169 #define I_u2s3u1(op) \
172 build_insn(buf, insn##op, c, a, b); \
174 UASM_EXPORT_SYMBOL(uasm_i##op);
176 #define I_u2u1s3(op) \
179 build_insn(buf, insn##op, b, a, c); \
181 UASM_EXPORT_SYMBOL(uasm_i##op);
183 #define I_u2u1msbu3(op) \
186 build_insn(buf, insn##op, b, a, c+d-1, c); \
188 UASM_EXPORT_SYMBOL(uasm_i##op);
190 #define I_u2u1msb32u3(op) \
193 build_insn(buf, insn##op, b, a, c+d-33, c); \
195 UASM_EXPORT_SYMBOL(uasm_i##op);
197 #define I_u2u1msbdu3(op) \
200 build_insn(buf, insn##op, b, a, d-1, c); \
202 UASM_EXPORT_SYMBOL(uasm_i##op);
207 build_insn(buf, insn##op, a, b); \
209 UASM_EXPORT_SYMBOL(uasm_i##op);
214 build_insn(buf, insn##op, b, a); \
216 UASM_EXPORT_SYMBOL(uasm_i##op);
221 build_insn(buf, insn##op, a, b); \
223 UASM_EXPORT_SYMBOL(uasm_i##op);
228 build_insn(buf, insn##op, a); \
230 UASM_EXPORT_SYMBOL(uasm_i##op);
235 build_insn(buf, insn##op); \
237 UASM_EXPORT_SYMBOL(uasm_i##op);
308 I_u2u1msb32u3(_dinsm);
315 #ifdef CONFIG_CPU_CAVIUM_OCTEON
316 #include <asm/octeon/octeon.h>
317 void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
320 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
322 * As per erratum Core-14449, replace prefetches 0-4,
323 * 6-24 with 'pref 28'.
325 build_insn(buf, insn_pref, c, 28, b);
327 build_insn(buf, insn_pref, c, a, b);
329 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
335 void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
341 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
343 int ISAFUNC(uasm_in_compat_space_p)(long addr)
345 /* Is this address in 32bit compat space? */
347 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
352 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
354 static int uasm_rel_highest(long val)
357 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
363 static int uasm_rel_higher(long val)
366 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
372 int ISAFUNC(uasm_rel_hi)(long val)
374 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
376 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
378 int ISAFUNC(uasm_rel_lo)(long val)
380 return ((val & 0xffff) ^ 0x8000) - 0x8000;
382 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
384 void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
386 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
387 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
388 if (uasm_rel_higher(addr))
389 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
390 if (ISAFUNC(uasm_rel_hi(addr))) {
391 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
392 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
393 ISAFUNC(uasm_rel_hi)(addr));
394 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
396 ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
398 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
400 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
402 void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
404 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
405 if (ISAFUNC(uasm_rel_lo(addr))) {
406 if (!ISAFUNC(uasm_in_compat_space_p)(addr))
407 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
408 ISAFUNC(uasm_rel_lo(addr)));
410 ISAFUNC(uasm_i_addiu)(buf, rs, rs,
411 ISAFUNC(uasm_rel_lo(addr)));
414 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
416 /* Handle relocations. */
417 void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
420 (*rel)->type = R_MIPS_PC16;
424 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
426 static inline void __resolve_relocs(struct uasm_reloc *rel,
427 struct uasm_label *lab);
429 void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
430 struct uasm_label *lab)
432 struct uasm_label *l;
434 for (; rel->lab != UASM_LABEL_INVALID; rel++)
435 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
436 if (rel->lab == l->lab)
437 __resolve_relocs(rel, l);
439 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
441 void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
444 for (; rel->lab != UASM_LABEL_INVALID; rel++)
445 if (rel->addr >= first && rel->addr < end)
448 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
450 void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
453 for (; lab->lab != UASM_LABEL_INVALID; lab++)
454 if (lab->addr >= first && lab->addr < end)
457 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
459 void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
460 u32 *first, u32 *end, u32 *target)
462 long off = (long)(target - first);
464 memcpy(target, first, (end - first) * sizeof(u32));
466 ISAFUNC(uasm_move_relocs(rel, first, end, off));
467 ISAFUNC(uasm_move_labels(lab, first, end, off));
469 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
471 int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
473 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
474 if (rel->addr == addr
475 && (rel->type == R_MIPS_PC16
476 || rel->type == R_MIPS_26))
482 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
484 /* Convenience functions for labeled branches. */
485 void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
488 uasm_r_mips_pc16(r, *p, lid);
489 ISAFUNC(uasm_i_bltz)(p, reg, 0);
491 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
493 void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
495 uasm_r_mips_pc16(r, *p, lid);
496 ISAFUNC(uasm_i_b)(p, 0);
498 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
500 void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
501 unsigned int r2, int lid)
503 uasm_r_mips_pc16(r, *p, lid);
504 ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
506 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
508 void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
511 uasm_r_mips_pc16(r, *p, lid);
512 ISAFUNC(uasm_i_beqz)(p, reg, 0);
514 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
516 void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
519 uasm_r_mips_pc16(r, *p, lid);
520 ISAFUNC(uasm_i_beqzl)(p, reg, 0);
522 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
524 void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
525 unsigned int reg2, int lid)
527 uasm_r_mips_pc16(r, *p, lid);
528 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
530 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
532 void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
535 uasm_r_mips_pc16(r, *p, lid);
536 ISAFUNC(uasm_i_bnez)(p, reg, 0);
538 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
540 void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
543 uasm_r_mips_pc16(r, *p, lid);
544 ISAFUNC(uasm_i_bgezl)(p, reg, 0);
546 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
548 void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
551 uasm_r_mips_pc16(r, *p, lid);
552 ISAFUNC(uasm_i_bgez)(p, reg, 0);
554 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
556 void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
557 unsigned int bit, int lid)
559 uasm_r_mips_pc16(r, *p, lid);
560 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
562 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
564 void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
565 unsigned int bit, int lid)
567 uasm_r_mips_pc16(r, *p, lid);
568 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
570 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));