arch/mips/mm/uasm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * A small micro-assembler. It is intentionally kept simple, does only
   7  * support a subset of instructions, and does not try to hide pipeline
   8  * effects like branch delay slots.
   9  *
  10  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  11  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  12  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  13  * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
  14  */
  15
  16 enum fields {
  17         RS = 0x001,
  18         RT = 0x002,
  19         RD = 0x004,
  20         RE = 0x008,
  21         SIMM = 0x010,
  22         UIMM = 0x020,
  23         BIMM = 0x040,
  24         JIMM = 0x080,
  25         FUNC = 0x100,
  26         SET = 0x200,
  27         SCIMM = 0x400
  28 };
  29
  30 #define OP_MASK         0x3f
  31 #define OP_SH           26
  32 #define RD_MASK         0x1f
  33 #define RD_SH           11
  34 #define RE_MASK         0x1f
  35 #define RE_SH           6
  36 #define IMM_MASK        0xffff
  37 #define IMM_SH          0
  38 #define JIMM_MASK       0x3ffffff
  39 #define JIMM_SH         0
  40 #define FUNC_MASK       0x3f
  41 #define FUNC_SH         0
  42 #define SET_MASK        0x7
  43 #define SET_SH          0
  44
  45 enum opcode {
  46         insn_invalid,
  47         insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
  48         insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
  49         insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
  50         insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
  51         insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
  52         insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
  53         insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
  54         insn_mfhi, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe,
  55         insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_sltiu,
  56         insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,
  57         insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,
  58         insn_wsbh, insn_xor, insn_xori, insn_yield,
  59 };
  60
  61 struct insn {
  62         enum opcode opcode;
  63         u32 match;
  64         enum fields fields;
  65 };
  66
  67 static inline u32 build_rs(u32 arg)
  68 {
  69         WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  70
  71         return (arg & RS_MASK) << RS_SH;
  72 }
  73
  74 static inline u32 build_rt(u32 arg)
  75 {
  76         WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  77
  78         return (arg & RT_MASK) << RT_SH;
  79 }
  80
  81 static inline u32 build_rd(u32 arg)
  82 {
  83         WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  84
  85         return (arg & RD_MASK) << RD_SH;
  86 }
  87
  88 static inline u32 build_re(u32 arg)
  89 {
  90         WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  91
  92         return (arg & RE_MASK) << RE_SH;
  93 }
  94
  95 static inline u32 build_simm(s32 arg)
  96 {
  97         WARN(arg > 0x7fff || arg < -0x8000,
  98              KERN_WARNING "Micro-assembler field overflow\n");
  99
 100         return arg & 0xffff;
 101 }
 102
 103 static inline u32 build_uimm(u32 arg)
 104 {
 105         WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
 106
 107         return arg & IMM_MASK;
 108 }
 109
 110 static inline u32 build_scimm(u32 arg)
 111 {
 112         WARN(arg & ~SCIMM_MASK,
 113              KERN_WARNING "Micro-assembler field overflow\n");
 114
 115         return (arg & SCIMM_MASK) << SCIMM_SH;
 116 }
 117
 118 static inline u32 build_func(u32 arg)
 119 {
 120         WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
 121
 122         return arg & FUNC_MASK;
 123 }
 124
 125 static inline u32 build_set(u32 arg)
 126 {
 127         WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
 128
 129         return arg & SET_MASK;
 130 }
 131
 132 static void build_insn(u32 **buf, enum opcode opc, ...);
 133
 134 #define I_u1u2u3(op)                                    \
 135 Ip_u1u2u3(op)                                           \
 136 {                                                       \
 137         build_insn(buf, insn##op, a, b, c);             \
 138 }                                                       \
 139 UASM_EXPORT_SYMBOL(uasm_i##op);
 140
 141 #define I_u2u1u3(op)                                    \
 142 Ip_u2u1u3(op)                                           \
 143 {                                                       \
 144         build_insn(buf, insn##op, b, a, c);             \
 145 }                                                       \
 146 UASM_EXPORT_SYMBOL(uasm_i##op);
 147
 148 #define I_u3u2u1(op)                                    \
 149 Ip_u3u2u1(op)                                           \
 150 {                                                       \
 151         build_insn(buf, insn##op, c, b, a);             \
 152 }                                                       \
 153 UASM_EXPORT_SYMBOL(uasm_i##op);
 154
 155 #define I_u3u1u2(op)                                    \
 156 Ip_u3u1u2(op)                                           \
 157 {                                                       \
 158         build_insn(buf, insn##op, b, c, a);             \
 159 }                                                       \
 160 UASM_EXPORT_SYMBOL(uasm_i##op);
 161
 162 #define I_u1u2s3(op)                                    \
 163 Ip_u1u2s3(op)                                           \
 164 {                                                       \
 165         build_insn(buf, insn##op, a, b, c);             \
 166 }                                                       \
 167 UASM_EXPORT_SYMBOL(uasm_i##op);
 168
 169 #define I_u2s3u1(op)                                    \
 170 Ip_u2s3u1(op)                                           \
 171 {                                                       \
 172         build_insn(buf, insn##op, c, a, b);             \
 173 }                                                       \
 174 UASM_EXPORT_SYMBOL(uasm_i##op);
 175
 176 #define I_u2u1s3(op)                                    \
 177 Ip_u2u1s3(op)                                           \
 178 {                                                       \
 179         build_insn(buf, insn##op, b, a, c);             \
 180 }                                                       \
 181 UASM_EXPORT_SYMBOL(uasm_i##op);
 182
 183 #define I_u2u1msbu3(op)                                 \
 184 Ip_u2u1msbu3(op)                                        \
 185 {                                                       \
 186         build_insn(buf, insn##op, b, a, c+d-1, c);      \
 187 }                                                       \
 188 UASM_EXPORT_SYMBOL(uasm_i##op);
 189
 190 #define I_u2u1msb32u3(op)                               \
 191 Ip_u2u1msbu3(op)                                        \
 192 {                                                       \
 193         build_insn(buf, insn##op, b, a, c+d-33, c);     \
 194 }                                                       \
 195 UASM_EXPORT_SYMBOL(uasm_i##op);
 196
 197 #define I_u2u1msbdu3(op)                                \
 198 Ip_u2u1msbu3(op)                                        \
 199 {                                                       \
 200         build_insn(buf, insn##op, b, a, d-1, c);        \
 201 }                                                       \
 202 UASM_EXPORT_SYMBOL(uasm_i##op);
 203
 204 #define I_u1u2(op)                                      \
 205 Ip_u1u2(op)                                             \
 206 {                                                       \
 207         build_insn(buf, insn##op, a, b);                \
 208 }                                                       \
 209 UASM_EXPORT_SYMBOL(uasm_i##op);
 210
 211 #define I_u2u1(op)                                      \
 212 Ip_u1u2(op)                                             \
 213 {                                                       \
 214         build_insn(buf, insn##op, b, a);                \
 215 }                                                       \
 216 UASM_EXPORT_SYMBOL(uasm_i##op);
 217
 218 #define I_u1s2(op)                                      \
 219 Ip_u1s2(op)                                             \
 220 {                                                       \
 221         build_insn(buf, insn##op, a, b);                \
 222 }                                                       \
 223 UASM_EXPORT_SYMBOL(uasm_i##op);
 224
 225 #define I_u1(op)                                        \
 226 Ip_u1(op)                                               \
 227 {                                                       \
 228         build_insn(buf, insn##op, a);                   \
 229 }                                                       \
 230 UASM_EXPORT_SYMBOL(uasm_i##op);
 231
 232 #define I_0(op)                                         \
 233 Ip_0(op)                                                \
 234 {                                                       \
 235         build_insn(buf, insn##op);                      \
 236 }                                                       \
 237 UASM_EXPORT_SYMBOL(uasm_i##op);
 238
 239 I_u2u1s3(_addiu)
 240 I_u3u1u2(_addu)
 241 I_u2u1u3(_andi)
 242 I_u3u1u2(_and)
 243 I_u1u2s3(_beq)
 244 I_u1u2s3(_beql)
 245 I_u1s2(_bgez)
 246 I_u1s2(_bgezl)
 247 I_u1s2(_bltz)
 248 I_u1s2(_bltzl)
 249 I_u1u2s3(_bne)
 250 I_u2s3u1(_cache)
 251 I_u1u2u3(_dmfc0)
 252 I_u1u2u3(_dmtc0)
 253 I_u2u1s3(_daddiu)
 254 I_u3u1u2(_daddu)
 255 I_u1u2(_divu)
 256 I_u2u1u3(_dsll)
 257 I_u2u1u3(_dsll32)
 258 I_u2u1u3(_dsra)
 259 I_u2u1u3(_dsrl)
 260 I_u2u1u3(_dsrl32)
 261 I_u2u1u3(_drotr)
 262 I_u2u1u3(_drotr32)
 263 I_u3u1u2(_dsubu)
 264 I_0(_eret)
 265 I_u2u1msbdu3(_ext)
 266 I_u2u1msbu3(_ins)
 267 I_u1(_j)
 268 I_u1(_jal)
 269 I_u2u1(_jalr)
 270 I_u1(_jr)
 271 I_u2s3u1(_ld)
 272 I_u2s3u1(_ll)
 273 I_u2s3u1(_lld)
 274 I_u1s2(_lui)
 275 I_u2s3u1(_lw)
 276 I_u1u2u3(_mfc0)
 277 I_u1(_mfhi)
 278 I_u1u2u3(_mtc0)
 279 I_u2u1u3(_ori)
 280 I_u3u1u2(_or)
 281 I_0(_rfe)
 282 I_u2s3u1(_sc)
 283 I_u2s3u1(_scd)
 284 I_u2s3u1(_sd)
 285 I_u2u1u3(_sll)
 286 I_u3u2u1(_sllv)
 287 I_u2u1s3(_sltiu)
 288 I_u3u1u2(_sltu)
 289 I_u2u1u3(_sra)
 290 I_u2u1u3(_srl)
 291 I_u3u2u1(_srlv)
 292 I_u2u1u3(_rotr)
 293 I_u3u1u2(_subu)
 294 I_u2s3u1(_sw)
 295 I_u1(_sync)
 296 I_0(_tlbp)
 297 I_0(_tlbr)
 298 I_0(_tlbwi)
 299 I_0(_tlbwr)
 300 I_u1(_wait);
 301 I_u2u1(_wsbh)
 302 I_u3u1u2(_xor)
 303 I_u2u1u3(_xori)
 304 I_u2u1(_yield)
 305 I_u2u1msbu3(_dins);
 306 I_u2u1msb32u3(_dinsm);
 307 I_u1(_syscall);
 308 I_u1u2s3(_bbit0);
 309 I_u1u2s3(_bbit1);
 310 I_u3u1u2(_lwx)
 311 I_u3u1u2(_ldx)
 312
 313 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 314 #include <asm/octeon/octeon.h>
 315 void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
 316                             unsigned int c)
 317 {
 318         if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
 319                 /*
 320                  * As per erratum Core-14449, replace prefetches 0-4,
 321                  * 6-24 with 'pref 28'.
 322                  */
 323                 build_insn(buf, insn_pref, c, 28, b);
 324         else
 325                 build_insn(buf, insn_pref, c, a, b);
 326 }
 327 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
 328 #else
 329 I_u2s3u1(_pref)
 330 #endif
 331
 332 /* Handle labels. */
 333 void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
 334 {
 335         (*lab)->addr = addr;
 336         (*lab)->lab = lid;
 337         (*lab)++;
 338 }
 339 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
 340
 341 int ISAFUNC(uasm_in_compat_space_p)(long addr)
 342 {
 343         /* Is this address in 32bit compat space? */
 344 #ifdef CONFIG_64BIT
 345         return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
 346 #else
 347         return 1;
 348 #endif
 349 }
 350 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
 351
 352 static int uasm_rel_highest(long val)
 353 {
 354 #ifdef CONFIG_64BIT
 355         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
 356 #else
 357         return 0;
 358 #endif
 359 }
 360
 361 static int uasm_rel_higher(long val)
 362 {
 363 #ifdef CONFIG_64BIT
 364         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
 365 #else
 366         return 0;
 367 #endif
 368 }
 369
 370 int ISAFUNC(uasm_rel_hi)(long val)
 371 {
 372         return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
 373 }
 374 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
 375
 376 int ISAFUNC(uasm_rel_lo)(long val)
 377 {
 378         return ((val & 0xffff) ^ 0x8000) - 0x8000;
 379 }
 380 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
 381
 382 void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
 383 {
 384         if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
 385                 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
 386                 if (uasm_rel_higher(addr))
 387                         ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
 388                 if (ISAFUNC(uasm_rel_hi(addr))) {
 389                         ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
 390                         ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
 391                                         ISAFUNC(uasm_rel_hi)(addr));
 392                         ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
 393                 } else
 394                         ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
 395         } else
 396                 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
 397 }
 398 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
 399
 400 void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
 401 {
 402         ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
 403         if (ISAFUNC(uasm_rel_lo(addr))) {
 404                 if (!ISAFUNC(uasm_in_compat_space_p)(addr))
 405                         ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
 406                                         ISAFUNC(uasm_rel_lo(addr)));
 407                 else
 408                         ISAFUNC(uasm_i_addiu)(buf, rs, rs,
 409                                         ISAFUNC(uasm_rel_lo(addr)));
 410         }
 411 }
 412 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
 413
 414 /* Handle relocations. */
 415 void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
 416 {
 417         (*rel)->addr = addr;
 418         (*rel)->type = R_MIPS_PC16;
 419         (*rel)->lab = lid;
 420         (*rel)++;
 421 }
 422 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
 423
 424 static inline void __resolve_relocs(struct uasm_reloc *rel,
 425                                     struct uasm_label *lab);
 426
 427 void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
 428                                   struct uasm_label *lab)
 429 {
 430         struct uasm_label *l;
 431
 432         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 433                 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
 434                         if (rel->lab == l->lab)
 435                                 __resolve_relocs(rel, l);
 436 }
 437 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
 438
 439 void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
 440                                long off)
 441 {
 442         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 443                 if (rel->addr >= first && rel->addr < end)
 444                         rel->addr += off;
 445 }
 446 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
 447
 448 void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
 449                                long off)
 450 {
 451         for (; lab->lab != UASM_LABEL_INVALID; lab++)
 452                 if (lab->addr >= first && lab->addr < end)
 453                         lab->addr += off;
 454 }
 455 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
 456
 457 void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
 458                                 u32 *first, u32 *end, u32 *target)
 459 {
 460         long off = (long)(target - first);
 461
 462         memcpy(target, first, (end - first) * sizeof(u32));
 463
 464         ISAFUNC(uasm_move_relocs(rel, first, end, off));
 465         ISAFUNC(uasm_move_labels(lab, first, end, off));
 466 }
 467 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
 468
 469 int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
 470 {
 471         for (; rel->lab != UASM_LABEL_INVALID; rel++) {
 472                 if (rel->addr == addr
 473                     && (rel->type == R_MIPS_PC16
 474                         || rel->type == R_MIPS_26))
 475                         return 1;
 476         }
 477
 478         return 0;
 479 }
 480 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
 481
 482 /* Convenience functions for labeled branches. */
 483 void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 484                            int lid)
 485 {
 486         uasm_r_mips_pc16(r, *p, lid);
 487         ISAFUNC(uasm_i_bltz)(p, reg, 0);
 488 }
 489 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
 490
 491 void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
 492 {
 493         uasm_r_mips_pc16(r, *p, lid);
 494         ISAFUNC(uasm_i_b)(p, 0);
 495 }
 496 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
 497
 498 void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
 499                           unsigned int r2, int lid)
 500 {
 501         uasm_r_mips_pc16(r, *p, lid);
 502         ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
 503 }
 504 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
 505
 506 void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 507                            int lid)
 508 {
 509         uasm_r_mips_pc16(r, *p, lid);
 510         ISAFUNC(uasm_i_beqz)(p, reg, 0);
 511 }
 512 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
 513
 514 void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 515                             int lid)
 516 {
 517         uasm_r_mips_pc16(r, *p, lid);
 518         ISAFUNC(uasm_i_beqzl)(p, reg, 0);
 519 }
 520 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
 521
 522 void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
 523                           unsigned int reg2, int lid)
 524 {
 525         uasm_r_mips_pc16(r, *p, lid);
 526         ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
 527 }
 528 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
 529
 530 void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 531                            int lid)
 532 {
 533         uasm_r_mips_pc16(r, *p, lid);
 534         ISAFUNC(uasm_i_bnez)(p, reg, 0);
 535 }
 536 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
 537
 538 void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 539                             int lid)
 540 {
 541         uasm_r_mips_pc16(r, *p, lid);
 542         ISAFUNC(uasm_i_bgezl)(p, reg, 0);
 543 }
 544 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
 545
 546 void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 547                            int lid)
 548 {
 549         uasm_r_mips_pc16(r, *p, lid);
 550         ISAFUNC(uasm_i_bgez)(p, reg, 0);
 551 }
 552 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
 553
 554 void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 555                             unsigned int bit, int lid)
 556 {
 557         uasm_r_mips_pc16(r, *p, lid);
 558         ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
 559 }
 560 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
 561
 562 void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 563                             unsigned int bit, int lid)
 564 {
 565         uasm_r_mips_pc16(r, *p, lid);
 566         ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
 567 }
 568 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));