arch/mips/mti-malta/malta-time.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * Setting up the clock on the MIPS boards.
  19  */
  20 #include <linux/types.h>
  21 #include <linux/i8253.h>
  22 #include <linux/init.h>
  23 #include <linux/kernel_stat.h>
  24 #include <linux/sched.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/timex.h>
  28 #include <linux/mc146818rtc.h>
  29
  30 #include <asm/mipsregs.h>
  31 #include <asm/mipsmtregs.h>
  32 #include <asm/hardirq.h>
  33 #include <asm/irq.h>
  34 #include <asm/div64.h>
  35 #include <asm/setup.h>
  36 #include <asm/time.h>
  37 #include <asm/mc146818-time.h>
  38 #include <asm/msc01_ic.h>
  39 #include <asm/gic.h>
  40
  41 #include <asm/mips-boards/generic.h>
  42 #include <asm/mips-boards/maltaint.h>
  43
  44 unsigned long cpu_khz;
  45
  46 static int mips_cpu_timer_irq;
  47 static int mips_cpu_perf_irq;
  48 extern int cp0_perfcount_irq;
  49
  50 static void mips_timer_dispatch(void)
  51 {
  52         do_IRQ(mips_cpu_timer_irq);
  53 }
  54
  55 static void mips_perf_dispatch(void)
  56 {
  57         do_IRQ(mips_cpu_perf_irq);
  58 }
  59
  60 static unsigned int freqround(unsigned int freq, unsigned int amount)
  61 {
  62         freq += amount;
  63         freq -= freq % (amount*2);
  64         return freq;
  65 }
  66
  67 /*
  68  * Estimate CPU and GIC frequencies.
  69  */
  70 static void __init estimate_frequencies(void)
  71 {
  72         unsigned long flags;
  73         unsigned int count, start;
  74         unsigned int giccount = 0, gicstart = 0;
  75
  76         local_irq_save(flags);
  77
  78         /* Start counter exactly on falling edge of update flag. */
  79         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  80         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  81
  82         /* Initialize counters. */
  83         start = read_c0_count();
  84         if (gic_present)
  85                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
  86
  87         /* Read counter exactly on falling edge of update flag. */
  88         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
  89         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
  90
  91         count = read_c0_count();
  92         if (gic_present)
  93                 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
  94
  95         local_irq_restore(flags);
  96
  97         count -= start;
  98         if (gic_present)
  99                 giccount -= gicstart;
 100
 101         mips_hpt_frequency = count;
 102         if (gic_present)
 103                 gic_frequency = giccount;
 104 }
 105
 106 void read_persistent_clock(struct timespec *ts)
 107 {
 108         ts->tv_sec = mc146818_get_cmos_time();
 109         ts->tv_nsec = 0;
 110 }
 111
 112 static void __init plat_perf_setup(void)
 113 {
 114 #ifdef MSC01E_INT_BASE
 115         if (cpu_has_veic) {
 116                 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
 117                 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
 118         } else
 119 #endif
 120         if (cp0_perfcount_irq >= 0) {
 121                 if (cpu_has_vint)
 122                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
 123                 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 124 #ifdef CONFIG_SMP
 125                 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
 126 #endif
 127         }
 128 }
 129
 130 unsigned int __cpuinit get_c0_compare_int(void)
 131 {
 132 #ifdef MSC01E_INT_BASE
 133         if (cpu_has_veic) {
 134                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
 135                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
 136         } else
 137 #endif
 138         {
 139                 if (cpu_has_vint)
 140                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
 141                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 142         }
 143
 144         return mips_cpu_timer_irq;
 145 }
 146
 147 void __init plat_time_init(void)
 148 {
 149         unsigned int prid = read_c0_prid() & 0xffff00;
 150         unsigned int freq;
 151
 152         estimate_frequencies();
 153
 154         freq = mips_hpt_frequency;
 155         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
 156             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
 157                 freq *= 2;
 158         freq = freqround(freq, 5000);
 159         pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
 160                (freq%1000000)*100/1000000);
 161         cpu_khz = freq / 1000;
 162
 163         if (gic_present) {
 164                 freq = freqround(gic_frequency, 5000);
 165                 pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
 166                        (freq%1000000)*100/1000000);
 167                 gic_clocksource_init(gic_frequency);
 168         } else
 169                 init_r4k_clocksource();
 170
 171 #ifdef CONFIG_I8253
 172         /* Only Malta has a PIT. */
 173         setup_pit_timer();
 174 #endif
 175
 176         mips_scroll_message();
 177
 178         plat_perf_setup();
 179 }