2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
11 * Define the pci_ops for the Toshiba rbtx4927
13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com>
16 * Copyright 2004 MontaVista Software Inc.
17 * Author: Manish Lachwani (mlachwani@mvista.com)
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * You should have received a copy of the GNU General Public License along
36 * with this program; if not, write to the Free Software Foundation, Inc.,
37 * 675 Mass Ave, Cambridge, MA 02139, USA.
39 #include <linux/types.h>
40 #include <linux/pci.h>
41 #include <linux/kernel.h>
42 #include <linux/init.h>
43 #include <asm/txx9/tx4927.h>
45 /* initialize in setup */
46 struct resource pci_io_resource = {
47 .name = "TX4927 PCI IO SPACE",
49 .end = (0x1000 + (TX4927_PCIIO_SIZE)) - 1,
50 .flags = IORESOURCE_IO
53 /* initialize in setup */
54 struct resource pci_mem_resource = {
55 .name = "TX4927 PCI MEM SPACE",
56 .start = TX4927_PCIMEM,
57 .end = TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1,
58 .flags = IORESOURCE_MEM
61 static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
64 /* Type 1 configuration */
65 tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
66 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
68 if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
71 /* Type 0 configuration */
72 tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
73 ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
75 /* clear M_ABORT and Disable M_ABORT Int. */
76 tx4927_pcicptr->pcistatus =
77 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
78 (PCI_STATUS_REC_MASTER_ABORT << 16);
79 tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
83 static int check_abort(int flags)
85 int code = PCIBIOS_SUCCESSFUL;
87 pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
88 tx4927_pcicptr->pcistatus =
90 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
92 tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
93 code = PCIBIOS_DEVICE_NOT_FOUND;
98 static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where,
101 int flags, retval, dev, busno, func;
104 dev = PCI_SLOT(devfn);
105 func = PCI_FUNC(devfn);
107 /* check if the bus is top-level */
108 if (bus->parent != NULL) {
114 if (mkaddr(busno, devfn, where, &flags))
119 *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr->
121 #ifdef __LITTLE_ENDIAN
124 ((where & 0x3) ^ 0x3));
128 *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr->
130 #ifdef __LITTLE_ENDIAN
133 ((where & 0x3) ^ 0x2));
137 *val = tx4927_pcicptr->g2pcfgdata;
141 retval = check_abort(flags);
142 if (retval == PCIBIOS_DEVICE_NOT_FOUND)
148 static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
151 int flags, dev, busno, func;
153 dev = PCI_SLOT(devfn);
154 func = PCI_FUNC(devfn);
156 /* check if the bus is top-level */
157 if (bus->parent != NULL) {
163 if (mkaddr(busno, devfn, where, &flags))
168 *(volatile u8 *) ((unsigned long) & tx4927_pcicptr->
170 #ifdef __LITTLE_ENDIAN
173 ((where & 0x3) ^ 0x3)) = val;
178 *(volatile u16 *) ((unsigned long) & tx4927_pcicptr->
180 #ifdef __LITTLE_ENDIAN
183 ((where & 0x3) ^ 0x2)) = val;
187 tx4927_pcicptr->g2pcfgdata = val;
191 return check_abort(flags);
194 struct pci_ops tx4927_pci_ops = {
195 tx4927_pcibios_read_config,
196 tx4927_pcibios_write_config
200 * h/w only supports devices 0x00 to 0x14
202 struct pci_controller tx4927_controller = {
203 .pci_ops = &tx4927_pci_ops,
204 .io_resource = &pci_io_resource,
205 .mem_resource = &pci_mem_resource,