2 * PCI Tower specific code
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/pci.h>
15 #include <linux/serial_8250.h>
19 #include <asm/irq_cpu.h>
22 #define PORT(_base,_irq) \
27 .iotype = UPIO_PORT, \
28 .flags = UPF_BOOT_AUTOCONF, \
31 static struct plat_serial8250_port pcit_data[] = {
37 static struct platform_device pcit_serial8250_device = {
39 .id = PLAT8250_DEV_PLATFORM,
41 .platform_data = pcit_data,
45 static struct plat_serial8250_port pcit_cplus_data[] = {
53 static struct platform_device pcit_cplus_serial8250_device = {
55 .id = PLAT8250_DEV_PLATFORM,
57 .platform_data = pcit_cplus_data,
61 static struct resource pcit_cmos_rsrc[] = {
65 .flags = IORESOURCE_IO
70 .flags = IORESOURCE_IRQ
74 static struct platform_device pcit_cmos_device = {
76 .num_resources = ARRAY_SIZE(pcit_cmos_rsrc),
77 .resource = pcit_cmos_rsrc
80 static struct platform_device pcit_pcspeaker_pdev = {
85 static struct resource sni_io_resource = {
86 .start = 0x00000000UL,
89 .flags = IORESOURCE_IO,
92 static struct resource pcit_io_resources[] = {
97 .flags = IORESOURCE_BUSY
102 .flags = IORESOURCE_BUSY
107 .flags = IORESOURCE_BUSY
111 .name = "dma page reg",
112 .flags = IORESOURCE_BUSY
117 .flags = IORESOURCE_BUSY
121 .name = "PCI config addr",
122 .flags = IORESOURCE_BUSY
126 .name = "PCI config data",
127 .flags = IORESOURCE_BUSY
131 static struct resource sni_mem_resource = {
132 .start = 0x18000000UL,
134 .name = "PCIT PCI MEM",
135 .flags = IORESOURCE_MEM
138 static void __init sni_pcit_resource_init(void)
142 /* request I/O space for devices used on all i[345]86 PCs */
143 for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
144 request_resource(&sni_io_resource, pcit_io_resources + i);
148 extern struct pci_ops sni_pcit_ops;
150 static struct pci_controller sni_pcit_controller = {
151 .pci_ops = &sni_pcit_ops,
152 .mem_resource = &sni_mem_resource,
153 .mem_offset = 0x00000000UL,
154 .io_resource = &sni_io_resource,
155 .io_offset = 0x00000000UL,
156 .io_map_base = SNI_PORT_BASE
159 static void enable_pcit_irq(struct irq_data *d)
161 u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
163 *(volatile u32 *)SNI_PCIT_INT_REG |= mask;
166 void disable_pcit_irq(struct irq_data *d)
168 u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
170 *(volatile u32 *)SNI_PCIT_INT_REG &= ~mask;
173 static struct irq_chip pcit_irq_type = {
175 .irq_mask = disable_pcit_irq,
176 .irq_unmask = enable_pcit_irq,
179 static void pcit_hwint1(void)
181 u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
184 clear_c0_status(IE_IRQ1);
185 irq = ffs((pending >> 16) & 0x7f);
188 do_IRQ(irq + SNI_PCIT_INT_START - 1);
189 set_c0_status(IE_IRQ1);
192 static void pcit_hwint0(void)
194 u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
197 clear_c0_status(IE_IRQ0);
198 irq = ffs((pending >> 16) & 0x3f);
201 do_IRQ(irq + SNI_PCIT_INT_START - 1);
202 set_c0_status(IE_IRQ0);
205 static void sni_pcit_hwint(void)
207 u32 pending = read_c0_cause() & read_c0_status();
209 if (pending & C_IRQ1)
211 else if (pending & C_IRQ2)
212 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
213 else if (pending & C_IRQ3)
214 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
215 else if (pending & C_IRQ5)
216 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
219 static void sni_pcit_hwint_cplus(void)
221 u32 pending = read_c0_cause() & read_c0_status();
223 if (pending & C_IRQ0)
225 else if (pending & C_IRQ1)
226 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
227 else if (pending & C_IRQ2)
228 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
229 else if (pending & C_IRQ3)
230 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
231 else if (pending & C_IRQ5)
232 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
235 void __init sni_pcit_irq_init(void)
240 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
241 irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
242 *(volatile u32 *)SNI_PCIT_INT_REG = 0;
243 sni_hwint = sni_pcit_hwint;
244 change_c0_status(ST0_IM, IE_IRQ1);
245 setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq);
248 void __init sni_pcit_cplus_irq_init(void)
253 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
254 irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
255 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
256 sni_hwint = sni_pcit_hwint_cplus;
257 change_c0_status(ST0_IM, IE_IRQ0);
258 setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
261 void __init sni_pcit_init(void)
263 ioport_resource.end = sni_io_resource.end;
265 PCIBIOS_MIN_IO = 0x9000;
266 register_pci_controller(&sni_pcit_controller);
268 sni_pcit_resource_init();
271 static int __init snirm_pcit_setup_devinit(void)
273 switch (sni_brd_type) {
274 case SNI_BRD_PCI_TOWER:
275 platform_device_register(&pcit_serial8250_device);
276 platform_device_register(&pcit_cmos_device);
277 platform_device_register(&pcit_pcspeaker_pdev);
280 case SNI_BRD_PCI_TOWER_CPLUS:
281 platform_device_register(&pcit_cplus_serial8250_device);
282 platform_device_register(&pcit_cmos_device);
283 platform_device_register(&pcit_pcspeaker_pdev);
289 device_initcall(snirm_pcit_setup_devinit);