1 #include <linux/types.h>
2 #include <linux/interrupt.h>
3 #include <linux/time.h>
7 #include <asm-generic/rtc.h>
9 #define SNI_CLOCK_TICK_RATE 3686400
10 #define SNI_COUNTER2_DIV 64
11 #define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
13 static void sni_a20r_timer_ack(void)
15 *(volatile u8 *)A20R_PT_TIM0_ACK = 0x0; wmb();
19 * a20r platform uses 2 counters to divide the input frequency.
20 * Counter 2 output is connected to Counter 0 & 1 input.
22 static void __init sni_a20r_timer_setup(struct irqaction *irq)
24 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34; wmb();
25 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = (SNI_COUNTER0_DIV) & 0xff; wmb();
26 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = (SNI_COUNTER0_DIV >> 8) & 0xff; wmb();
28 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4; wmb();
29 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = (SNI_COUNTER2_DIV) & 0xff; wmb();
30 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = (SNI_COUNTER2_DIV >> 8) & 0xff; wmb();
32 setup_irq(SNI_A20R_IRQ_TIMER, irq);
33 mips_timer_ack = sni_a20r_timer_ack;
36 #define SNI_8254_TICK_RATE 1193182UL
38 #define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255)
40 static __init unsigned long dosample(void)
45 /* Start the counter. */
47 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
48 outb (SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
50 /* Get initial counter invariant */
51 ct0 = read_c0_count();
53 /* Latch and spin until top byte of counter0 is zero */
58 ct1 = read_c0_count();
61 /* Stop the counter. */
64 * Return the difference, this is how far the r4k counter increments
65 * for every 1/HZ seconds. We round off the nearest 1 MHz of master
66 * clock (= 1000000 / HZ / 2).
68 /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
69 return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
73 * Here we need to calibrate the cycle counter to at least be close.
75 void __init plat_time_init(void)
77 unsigned long r4k_ticks[3];
78 unsigned long r4k_tick;
81 * Figure out the r4k offset, the algorithm is very simple and works in
82 * _all_ cases as long as the 8254 counter register itself works ok (as
83 * an interrupt driving timer it does not because of bug, this is why
84 * we are using the onchip r4k counter/compare register to serve this
85 * purpose, but for r4k_offset calculation it will work ok for us).
86 * There are other very complicated ways of performing this calculation
87 * but this one works just fine so I am not going to futz around. ;-)
89 printk(KERN_INFO "Calibrating system timer... ");
90 dosample(); /* Prime cache. */
91 dosample(); /* Prime cache. */
92 /* Zero is NOT an option. */
94 r4k_ticks[0] = dosample();
95 } while (!r4k_ticks[0]);
97 r4k_ticks[1] = dosample();
98 } while (!r4k_ticks[1]);
100 if (r4k_ticks[0] != r4k_ticks[1]) {
101 printk("warning: timer counts differ, retrying... ");
102 r4k_ticks[2] = dosample();
103 if (r4k_ticks[2] == r4k_ticks[0]
104 || r4k_ticks[2] == r4k_ticks[1])
105 r4k_tick = r4k_ticks[2];
107 printk("disagreement, using average... ");
108 r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
112 r4k_tick = r4k_ticks[0];
114 printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
115 (int) (r4k_tick / (500000 / HZ)),
116 (int) (r4k_tick % (500000 / HZ)));
118 mips_hpt_frequency = r4k_tick * HZ;
122 * R4k counter based timer interrupt. Works on RM200-225 and possibly
123 * others but not on RM400
125 static void __init sni_cpu_timer_setup(struct irqaction *irq)
127 setup_irq(SNI_MIPS_IRQ_CPU_TIMER, irq);
130 void __init plat_timer_setup(struct irqaction *irq)
132 switch (sni_brd_type) {
135 case SNI_BRD_TOWER_OASIC:
136 case SNI_BRD_MINITOWER:
137 sni_a20r_timer_setup (irq);
140 case SNI_BRD_PCI_TOWER:
142 case SNI_BRD_PCI_MTOWER:
143 case SNI_BRD_PCI_DESKTOP:
144 case SNI_BRD_PCI_TOWER_CPLUS:
145 case SNI_BRD_PCI_MTOWER_CPLUS:
146 sni_cpu_timer_setup (irq);
151 unsigned long read_persistent_clock(void)