2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/ioport.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/console.h>
20 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/clk.h>
25 #include <asm/wbflush.h>
26 #include <asm/reboot.h>
29 #include <asm/uaccess.h>
31 #include <asm/bootinfo.h>
32 #include <asm/tx4938/rbtx4938.h>
33 #ifdef CONFIG_SERIAL_TXX9
34 #include <linux/tty.h>
35 #include <linux/serial.h>
36 #include <linux/serial_core.h>
38 #include <linux/spi/spi.h>
39 #include <asm/tx4938/spi.h>
42 extern void rbtx4938_time_init(void) __init;
43 extern char * __init prom_getcmdline(void);
44 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
46 /* These functions are used for rebooting or halting the machine*/
47 extern void rbtx4938_machine_restart(char *command);
48 extern void rbtx4938_machine_halt(void);
49 extern void rbtx4938_machine_power_off(void);
52 unsigned int txx9_master_clock;
53 unsigned int txx9_cpu_clock;
54 unsigned int txx9_gbus_clock;
56 unsigned long rbtx4938_ce_base[8];
57 unsigned long rbtx4938_ce_size[8];
58 int txboard_pci66_mode;
59 static int tx4938_pcic_trdyto; /* default: disabled */
60 static int tx4938_pcic_retryto; /* default: disabled */
61 static int tx4938_ccfg_toeon = 1;
63 struct tx4938_pcic_reg *pcicptrs[4] = {
64 tx4938_pcicptr /* default setting for TX4938 */
70 } phys_regions[16] __initdata;
71 static int num_phys_regions __initdata;
73 #define PHYS_REGION_MINSIZE 0x10000
75 void rbtx4938_machine_halt(void)
77 printk(KERN_NOTICE "System Halted\n");
81 __asm__(".set\tmips3\n\t"
86 void rbtx4938_machine_power_off(void)
88 rbtx4938_machine_halt();
92 void rbtx4938_machine_restart(char *command)
96 printk("Rebooting...");
97 *rbtx4938_softresetlock_ptr = 1;
98 *rbtx4938_sfvol_ptr = 1;
99 *rbtx4938_softreset_ptr = 1;
106 txboard_add_phys_region(unsigned long base, unsigned long size)
108 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
109 printk("phys_region overflow\n");
112 phys_regions[num_phys_regions].base = base;
113 phys_regions[num_phys_regions].size = size;
117 txboard_find_free_phys_region(unsigned long begin, unsigned long end,
123 for (base = begin / size * size; base < end; base += size) {
124 for (i = 0; i < num_phys_regions; i++) {
125 if (phys_regions[i].size &&
126 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
127 base + (size - 1) >= phys_regions[i].base)
130 if (i == num_phys_regions)
136 txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
139 unsigned long sz, base;
140 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
141 base = txboard_find_free_phys_region(begin, end, sz);
150 txboard_request_phys_region_range(unsigned long begin, unsigned long end,
154 base = txboard_find_free_phys_region(begin, end, size);
156 txboard_add_phys_region(base, size);
160 txboard_request_phys_region(unsigned long size)
163 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
164 base = txboard_find_free_phys_region(begin, end, size);
166 txboard_add_phys_region(base, size);
170 txboard_request_phys_region_shrink(unsigned long *size)
173 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
174 base = txboard_find_free_phys_region_shrink(begin, end, size);
176 txboard_add_phys_region(base, *size);
182 tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
183 struct pci_controller *channel,
184 unsigned long pci_io_base,
189 /* Disable All Initiator Space */
190 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
191 TX4938_PCIC_PCICCFG_G2PMEN(1)|
192 TX4938_PCIC_PCICCFG_G2PMEN(2)|
193 TX4938_PCIC_PCICCFG_G2PIOEN);
195 /* GB->PCI mappings */
196 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
197 pcicptr->g2piogbase = pci_io_base |
199 TX4938_PCIC_G2PIOGBASE_ECHG
201 TX4938_PCIC_G2PIOGBASE_BSDIS
204 pcicptr->g2piopbase = 0;
205 for (i = 0; i < 3; i++) {
206 pcicptr->g2pmmask[i] = 0;
207 pcicptr->g2pmgbase[i] = 0;
208 pcicptr->g2pmpbase[i] = 0;
210 if (channel->mem_resource->end) {
211 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
212 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
214 TX4938_PCIC_G2PMnGBASE_ECHG
216 TX4938_PCIC_G2PMnGBASE_BSDIS
219 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
221 /* PCI->GB mappings (I/O 256B) */
222 pcicptr->p2giopbase = 0; /* 256B */
223 pcicptr->p2giogbase = 0;
224 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
225 pcicptr->p2gm0plbase = 0;
226 pcicptr->p2gm0pubase = 0;
227 pcicptr->p2gmgbase[0] = 0 |
228 TX4938_PCIC_P2GMnGBASE_TMEMEN |
230 TX4938_PCIC_P2GMnGBASE_TECHG
232 TX4938_PCIC_P2GMnGBASE_TBSDIS
235 /* PCI->GB mappings (MEM 16MB) */
236 pcicptr->p2gm1plbase = 0xffffffff;
237 pcicptr->p2gm1pubase = 0xffffffff;
238 pcicptr->p2gmgbase[1] = 0;
239 /* PCI->GB mappings (MEM 1MB) */
240 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
241 pcicptr->p2gmgbase[2] = 0;
243 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
244 /* Enable Initiator Memory Space */
245 if (channel->mem_resource->end)
246 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
247 /* Enable Initiator I/O Space */
248 if (channel->io_resource->end)
249 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
250 /* Enable Initiator Config */
252 TX4938_PCIC_PCICCFG_ICAEN |
253 TX4938_PCIC_PCICCFG_TCAR;
255 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
256 pcicptr->pcicfg1 = 0;
258 pcicptr->g2ptocnt &= ~0xffff;
260 if (tx4938_pcic_trdyto >= 0) {
261 pcicptr->g2ptocnt &= ~0xff;
262 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
265 if (tx4938_pcic_retryto >= 0) {
266 pcicptr->g2ptocnt &= ~0xff00;
267 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
270 /* Clear All Local Bus Status */
271 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
272 /* Enable All Local Bus Interrupts */
273 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
274 /* Clear All Initiator Status */
275 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
276 /* Enable All Initiator Interrupts */
277 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
278 /* Clear All PCI Status Error */
280 (pcicptr->pcistatus & 0x0000ffff) |
281 (TX4938_PCIC_PCISTATUS_ALL << 16);
282 /* Enable All PCI Status Error Interrupts */
283 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
286 /* Reset Bus Arbiter */
287 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
289 /* Enable Bus Arbiter */
290 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
293 /* PCIC Int => IRC IRQ16 */
295 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
297 pcicptr->pcistatus = PCI_COMMAND_MASTER |
299 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
303 tx4938_report_pciclk(void)
305 unsigned long pcode = TX4938_REV_PCODE();
307 printk("TX%lx PCIC --%s PCICLK:",
309 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
310 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
312 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
313 case TX4938_CCFG_PCIDIVMODE_4:
314 pciclk = txx9_cpu_clock / 4; break;
315 case TX4938_CCFG_PCIDIVMODE_4_5:
316 pciclk = txx9_cpu_clock * 2 / 9; break;
317 case TX4938_CCFG_PCIDIVMODE_5:
318 pciclk = txx9_cpu_clock / 5; break;
319 case TX4938_CCFG_PCIDIVMODE_5_5:
320 pciclk = txx9_cpu_clock * 2 / 11; break;
321 case TX4938_CCFG_PCIDIVMODE_8:
322 pciclk = txx9_cpu_clock / 8; break;
323 case TX4938_CCFG_PCIDIVMODE_9:
324 pciclk = txx9_cpu_clock / 9; break;
325 case TX4938_CCFG_PCIDIVMODE_10:
326 pciclk = txx9_cpu_clock / 10; break;
327 case TX4938_CCFG_PCIDIVMODE_11:
328 pciclk = txx9_cpu_clock / 11; break;
330 printk("Internal(%dMHz)", pciclk / 1000000);
339 void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
341 pcicptrs[ch] = pcicptr;
344 struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
349 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
350 int top_bus, int busnr, int devfn)
352 static struct pci_dev dev;
353 static struct pci_bus bus;
355 dev.sysdata = (void *)hose;
358 bus.ops = hose->pci_ops;
365 #define EARLY_PCI_OP(rw, size, type) \
366 static int early_##rw##_config_##size(struct pci_controller *hose, \
367 int top_bus, int bus, int devfn, int offset, type value) \
369 return pci_##rw##_config_##size( \
370 fake_pci_dev(hose, top_bus, bus, devfn), \
374 EARLY_PCI_OP(read, word, u16 *)
376 int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
381 int devfn_stop = 0xff;
385 printk("PCI: Checking 66MHz capabilities...\n");
387 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
388 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
389 PCI_VENDOR_ID, &vid);
391 if (vid == 0xffff) continue;
393 /* check 66MHz capability */
397 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
399 if (!(stat & PCI_STATUS_66MHZ)) {
400 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
401 current_bus, pci_devfn);
411 tx4938_pciclk66_setup(void)
416 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
417 /* Double PCICLK (if possible) */
418 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
419 unsigned int pcidivmode =
420 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
421 switch (pcidivmode) {
422 case TX4938_CCFG_PCIDIVMODE_8:
423 case TX4938_CCFG_PCIDIVMODE_4:
424 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
425 pciclk = txx9_cpu_clock / 4;
427 case TX4938_CCFG_PCIDIVMODE_9:
428 case TX4938_CCFG_PCIDIVMODE_4_5:
429 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
430 pciclk = txx9_cpu_clock * 2 / 9;
432 case TX4938_CCFG_PCIDIVMODE_10:
433 case TX4938_CCFG_PCIDIVMODE_5:
434 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
435 pciclk = txx9_cpu_clock / 5;
437 case TX4938_CCFG_PCIDIVMODE_11:
438 case TX4938_CCFG_PCIDIVMODE_5_5:
440 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
441 pciclk = txx9_cpu_clock * 2 / 11;
444 tx4938_ccfgptr->ccfg =
445 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
447 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
448 (unsigned long)tx4938_ccfgptr->ccfg);
455 extern struct pci_controller tx4938_pci_controller[];
456 static int __init tx4938_pcibios_init(void)
458 unsigned long mem_base[2];
459 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
460 unsigned long io_base[2];
461 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
462 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
463 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
465 PCIBIOS_MIN_IO = 0x00001000UL;
466 PCIBIOS_MIN_MEM = 0x01000000UL;
468 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
469 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
471 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
472 (unsigned short)(tx4938_pcicptr->pciid >> 16),
473 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
474 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
475 extarb ? "External" : "Internal");
478 tx4938_pci_controller[0].io_resource->start = io_base[0];
479 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
480 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
481 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
483 set_tx4938_pcicptr(0, tx4938_pcicptr);
485 register_pci_controller(&tx4938_pci_controller[0]);
487 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
488 printk("TX4938_CCFG_PCI66 already configured\n");
489 txboard_pci66_mode = -1; /* already configured */
493 *rbtx4938_pcireset_ptr = 0;
495 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
496 if (txboard_pci66_mode > 0)
497 tx4938_pciclk66_setup();
499 /* clear PCIC reset */
500 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
501 *rbtx4938_pcireset_ptr = 1;
503 tx4938_report_pcic_status1(tx4938_pcicptr);
505 tx4938_report_pciclk();
506 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
507 if (txboard_pci66_mode == 0 &&
508 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
510 *rbtx4938_pcireset_ptr = 0;
512 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
513 tx4938_pciclk66_setup();
515 /* clear PCIC reset */
516 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
517 *rbtx4938_pcireset_ptr = 1;
519 /* Reinitialize PCIC */
520 tx4938_report_pciclk();
521 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
524 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
525 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
527 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
528 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
529 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
530 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
532 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
534 /* clear PCIC1 reset */
535 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
536 tx4938_report_pcic_status1(tx4938_pcic1ptr);
538 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
539 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
540 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
541 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
542 printk("%s PCICLK:%dMHz\n",
543 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
545 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
548 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
549 tx4938_pci_controller[1].io_resource->start =
550 io_base[1] - io_base[0];
551 tx4938_pci_controller[1].io_resource->end =
552 io_base[1] - io_base[0] + io_size[1] - 1;
553 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
554 tx4938_pci_controller[1].mem_resource->end =
555 mem_base[1] + mem_size[1] - 1;
556 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
558 register_pci_controller(&tx4938_pci_controller[1]);
560 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
562 /* map ioport 0 to PCI I/O space address 0 */
563 set_io_port_base(KSEG1 + io_base[0]);
568 arch_initcall(tx4938_pcibios_init);
570 #endif /* CONFIG_PCI */
574 /* chip select for SPI devices */
575 #define SEEPROM1_CS 7 /* PIO7 */
576 #define SEEPROM2_CS 0 /* IOC */
577 #define SEEPROM3_CS 1 /* IOC */
578 #define SRTC_CS 2 /* IOC */
581 static unsigned char rbtx4938_ethaddr[17];
582 static int __init rbtx4938_ethaddr_init(void)
587 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
588 if (spi_eeprom_read(SEEPROM1_CS, 0,
589 rbtx4938_ethaddr, sizeof(rbtx4938_ethaddr)))
590 printk(KERN_ERR "seeprom: read error.\n");
592 unsigned char *dat = rbtx4938_ethaddr;
593 if (strcmp(dat, "MAC") != 0)
594 printk(KERN_WARNING "seeprom: bad signature.\n");
595 for (i = 0, sum = 0; i < sizeof(dat); i++)
598 printk(KERN_WARNING "seeprom: bad checksum.\n");
602 device_initcall(rbtx4938_ethaddr_init);
604 int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
606 struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata;
609 if (channel != &tx4938_pci_controller[1])
612 switch (PCI_SLOT(dev->devfn)) {
613 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
616 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
622 memcpy(addr, &rbtx4938_ethaddr[4 + 6 * ch], 6);
625 #endif /* CONFIG_PCI */
627 static void __init rbtx4938_spi_setup(void)
630 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
631 /* chip selects for SPI devices */
632 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
633 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
636 static struct resource rbtx4938_fpga_resource;
638 static char pcode_str[8];
639 static struct resource tx4938_reg_resource = {
640 .start = TX4938_REG_BASE,
641 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
643 .flags = IORESOURCE_MEM
646 void __init tx4938_board_setup(void)
649 unsigned long divmode;
651 unsigned long pcode = TX4938_REV_PCODE();
653 ioport_resource.start = 0x1000;
654 ioport_resource.end = 0xffffffff;
655 iomem_resource.start = 0x1000;
656 iomem_resource.end = 0xffffffff; /* expand to 4GB */
658 sprintf(pcode_str, "TX%lx", pcode);
659 /* SDRAMC,EBUSC are configured by PROM */
660 for (i = 0; i < 8; i++) {
661 if (!(tx4938_ebuscptr->cr[i] & 0x8))
662 continue; /* disabled */
663 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
664 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
668 if (txx9_master_clock) {
669 /* calculate gbus_clock and cpu_clock from master_clock */
670 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
672 case TX4938_CCFG_DIVMODE_8:
673 case TX4938_CCFG_DIVMODE_10:
674 case TX4938_CCFG_DIVMODE_12:
675 case TX4938_CCFG_DIVMODE_16:
676 case TX4938_CCFG_DIVMODE_18:
677 txx9_gbus_clock = txx9_master_clock * 4; break;
679 txx9_gbus_clock = txx9_master_clock;
682 case TX4938_CCFG_DIVMODE_2:
683 case TX4938_CCFG_DIVMODE_8:
684 cpuclk = txx9_gbus_clock * 2; break;
685 case TX4938_CCFG_DIVMODE_2_5:
686 case TX4938_CCFG_DIVMODE_10:
687 cpuclk = txx9_gbus_clock * 5 / 2; break;
688 case TX4938_CCFG_DIVMODE_3:
689 case TX4938_CCFG_DIVMODE_12:
690 cpuclk = txx9_gbus_clock * 3; break;
691 case TX4938_CCFG_DIVMODE_4:
692 case TX4938_CCFG_DIVMODE_16:
693 cpuclk = txx9_gbus_clock * 4; break;
694 case TX4938_CCFG_DIVMODE_4_5:
695 case TX4938_CCFG_DIVMODE_18:
696 cpuclk = txx9_gbus_clock * 9 / 2; break;
698 txx9_cpu_clock = cpuclk;
700 if (txx9_cpu_clock == 0) {
701 txx9_cpu_clock = 300000000; /* 300MHz */
703 /* calculate gbus_clock and master_clock from cpu_clock */
704 cpuclk = txx9_cpu_clock;
705 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
707 case TX4938_CCFG_DIVMODE_2:
708 case TX4938_CCFG_DIVMODE_8:
709 txx9_gbus_clock = cpuclk / 2; break;
710 case TX4938_CCFG_DIVMODE_2_5:
711 case TX4938_CCFG_DIVMODE_10:
712 txx9_gbus_clock = cpuclk * 2 / 5; break;
713 case TX4938_CCFG_DIVMODE_3:
714 case TX4938_CCFG_DIVMODE_12:
715 txx9_gbus_clock = cpuclk / 3; break;
716 case TX4938_CCFG_DIVMODE_4:
717 case TX4938_CCFG_DIVMODE_16:
718 txx9_gbus_clock = cpuclk / 4; break;
719 case TX4938_CCFG_DIVMODE_4_5:
720 case TX4938_CCFG_DIVMODE_18:
721 txx9_gbus_clock = cpuclk * 2 / 9; break;
724 case TX4938_CCFG_DIVMODE_8:
725 case TX4938_CCFG_DIVMODE_10:
726 case TX4938_CCFG_DIVMODE_12:
727 case TX4938_CCFG_DIVMODE_16:
728 case TX4938_CCFG_DIVMODE_18:
729 txx9_master_clock = txx9_gbus_clock / 4; break;
731 txx9_master_clock = txx9_gbus_clock;
734 /* change default value to udelay/mdelay take reasonable time */
735 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
738 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
739 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
740 /* clear PCIC1 reset */
741 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
742 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
744 /* enable Timeout BusError */
745 if (tx4938_ccfg_toeon)
746 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
749 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
751 /* Use external clock for external arbiter */
752 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
753 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
755 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
757 cpuclk / 1000000, txx9_master_clock / 1000000,
758 (unsigned long)tx4938_ccfgptr->crir,
759 tx4938_ccfgptr->ccfg,
760 tx4938_ccfgptr->pcfg);
762 printk("%s SDRAMC --", pcode_str);
763 for (i = 0; i < 4; i++) {
764 unsigned long long cr = tx4938_sdramcptr->cr[i];
765 unsigned long ram_base, ram_size;
766 if (!((unsigned long)cr & 0x00000400))
767 continue; /* disabled */
768 ram_base = (unsigned long)(cr >> 49) << 21;
769 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
770 if (ram_base >= 0x20000000)
771 continue; /* high memory (ignore) */
772 printk(" CR%d:%016Lx", i, cr);
773 txboard_add_phys_region(ram_base, ram_size);
775 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
778 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
779 unsigned int size = 0x800;
781 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
782 txboard_add_phys_region(base, size);
786 /* disable interrupt control */
787 tx4938_ircptr->cer = 0;
790 /* disable all timers */
791 for (i = 0; i < TX4938_NR_TMR; i++) {
792 tx4938_tmrptr(i)->tcr = 0x00000020;
793 tx4938_tmrptr(i)->tisr = 0;
794 tx4938_tmrptr(i)->cpra = 0xffffffff;
795 tx4938_tmrptr(i)->itmr = 0;
796 tx4938_tmrptr(i)->ccdr = 0;
797 tx4938_tmrptr(i)->pgmr = 0;
801 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
802 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
805 tx4938_pioptr->maskcpu = 0;
806 tx4938_pioptr->maskext = 0;
808 /* TX4938 internal registers */
809 if (request_resource(&iomem_resource, &tx4938_reg_resource))
810 printk("request resource for internal registers failed\n");
814 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
816 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
817 unsigned long g2pstatus = pcicptr->g2pstatus;
818 unsigned long pcicstatus = pcicptr->pcicstatus;
823 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
824 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
825 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
826 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
827 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
828 { PCI_STATUS_PARITY, "MasterParityError" },
830 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
831 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
832 }, pcicstat_tbl[] = {
833 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
834 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
835 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
836 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
837 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
838 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
839 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
840 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
844 printk("pcistat:%04x(", pcistatus);
845 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
846 if (pcistatus & pcistat_tbl[i].flag)
847 printk("%s ", pcistat_tbl[i].str);
848 printk("), g2pstatus:%08lx(", g2pstatus);
849 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
850 if (g2pstatus & g2pstat_tbl[i].flag)
851 printk("%s ", g2pstat_tbl[i].str);
852 printk("), pcicstatus:%08lx(", pcicstatus);
853 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
854 if (pcicstatus & pcicstat_tbl[i].flag)
855 printk("%s ", pcicstat_tbl[i].str);
859 void tx4938_report_pcic_status(void)
862 struct tx4938_pcic_reg *pcicptr;
863 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
864 tx4938_report_pcic_status1(pcicptr);
867 #endif /* CONFIG_PCI */
869 /* We use onchip r4k counter or TMR timer as our system wide timer
870 * interrupt running at 100HZ. */
872 void __init rbtx4938_time_init(void)
874 mips_hpt_frequency = txx9_cpu_clock / 2;
877 void __init toshiba_rbtx4938_setup(void)
879 unsigned long long pcfg;
882 iomem_resource.end = 0xffffffff; /* 4GB */
884 if (txx9_master_clock == 0)
885 txx9_master_clock = 25000000; /* 25MHz */
886 tx4938_board_setup();
887 /* setup irq stuff */
888 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */
889 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */
890 /* setup serial stuff */
891 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
892 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
895 set_io_port_base(RBTX4938_ETHER_BASE);
898 #ifdef CONFIG_SERIAL_TXX9
900 extern int early_serial_txx9_setup(struct uart_port *port);
902 struct uart_port req;
903 for(i = 0; i < 2; i++) {
904 memset(&req, 0, sizeof(req));
906 req.iotype = UPIO_MEM;
907 req.membase = (char *)(0xff1ff300 + i * 0x100);
908 req.mapbase = 0xff1ff300 + i * 0x100;
910 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
911 req.uartclk = 50000000;
912 early_serial_txx9_setup(&req);
915 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
916 argptr = prom_getcmdline();
917 if (strstr(argptr, "console=") == NULL) {
918 strcat(argptr, " console=ttyS0,38400");
923 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
924 printk("PIOSEL: disabling both ata and nand selection\n");
926 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
929 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
930 printk("PIOSEL: enabling nand selection\n");
931 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
932 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
935 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
936 printk("PIOSEL: enabling ata selection\n");
937 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
938 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
942 argptr = prom_getcmdline();
943 if (strstr(argptr, "ip=") == NULL) {
944 strcat(argptr, " ip=any");
951 conswitchp = &dummy_con;
955 rbtx4938_spi_setup();
956 pcfg = tx4938_ccfgptr->pcfg; /* updated */
958 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
959 TX4938_PCFG_ATA_SEL) {
960 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
962 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
963 TX4938_PCFG_NDF_SEL) {
964 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
967 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
970 rbtx4938_fpga_resource.name = "FPGA Registers";
971 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
972 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
973 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
974 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
975 printk("request resource for fpga failed\n");
977 /* disable all OnBoard I/O interrupts */
978 *rbtx4938_imask_ptr = 0;
980 _machine_restart = rbtx4938_machine_restart;
981 _machine_halt = rbtx4938_machine_halt;
982 pm_power_off = rbtx4938_machine_power_off;
984 *rbtx4938_led_ptr = 0xff;
985 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
986 printk(" DIPSW:%02x,%02x\n",
987 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
990 static int __init rbtx4938_ne_init(void)
992 struct resource res[] = {
994 .start = RBTX4938_RTL_8019_BASE,
995 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
996 .flags = IORESOURCE_IO,
998 .start = RBTX4938_RTL_8019_IRQ,
999 .flags = IORESOURCE_IRQ,
1002 struct platform_device *dev =
1003 platform_device_register_simple("ne", -1,
1004 res, ARRAY_SIZE(res));
1005 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1007 device_initcall(rbtx4938_ne_init);
1011 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
1013 static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
1016 unsigned long flags;
1018 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
1019 val = *rbtx4938_spics_ptr;
1023 val &= ~(1 << gpio);
1024 *rbtx4938_spics_ptr = val;
1026 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
1029 static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
1031 rbtx4938_spi_gpio_set(gpio, value);
1035 static DEFINE_SPINLOCK(tx4938_gpio_lock);
1037 static int tx4938_gpio_get(unsigned gpio)
1039 return tx4938_pioptr->din & (1 << gpio);
1042 static void tx4938_gpio_set_raw(unsigned gpio, int value)
1045 val = tx4938_pioptr->dout;
1049 val &= ~(1 << gpio);
1050 tx4938_pioptr->dout = val;
1053 static void tx4938_gpio_set(unsigned gpio, int value)
1055 unsigned long flags;
1056 spin_lock_irqsave(&tx4938_gpio_lock, flags);
1057 tx4938_gpio_set_raw(gpio, value);
1059 spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
1062 static int tx4938_gpio_dir_in(unsigned gpio)
1064 spin_lock_irq(&tx4938_gpio_lock);
1065 tx4938_pioptr->dir &= ~(1 << gpio);
1067 spin_unlock_irq(&tx4938_gpio_lock);
1071 static int tx4938_gpio_dir_out(unsigned int gpio, int value)
1073 spin_lock_irq(&tx4938_gpio_lock);
1074 tx4938_gpio_set_raw(gpio, value);
1075 tx4938_pioptr->dir |= 1 << gpio;
1077 spin_unlock_irq(&tx4938_gpio_lock);
1081 int gpio_direction_input(unsigned gpio)
1084 return tx4938_gpio_dir_in(gpio);
1088 int gpio_direction_output(unsigned gpio, int value)
1091 return tx4938_gpio_dir_out(gpio, value);
1093 return rbtx4938_spi_gpio_dir_out(gpio, value);
1097 int gpio_get_value(unsigned gpio)
1100 return tx4938_gpio_get(gpio);
1104 void gpio_set_value(unsigned gpio, int value)
1107 tx4938_gpio_set(gpio, value);
1109 rbtx4938_spi_gpio_set(gpio, value);
1114 static void __init txx9_spi_init(unsigned long base, int irq)
1116 struct resource res[] = {
1119 .end = base + 0x20 - 1,
1120 .flags = IORESOURCE_MEM,
1121 .parent = &tx4938_reg_resource,
1124 .flags = IORESOURCE_IRQ,
1127 platform_device_register_simple("txx9spi", 0,
1128 res, ARRAY_SIZE(res));
1131 static int __init rbtx4938_spi_init(void)
1133 struct spi_board_info srtc_info = {
1134 .modalias = "rs5c348",
1135 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
1137 .chip_select = 16 + SRTC_CS,
1138 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
1139 .mode = SPI_MODE_1 | SPI_CS_HIGH,
1141 spi_register_board_info(&srtc_info, 1);
1142 spi_eeprom_register(SEEPROM1_CS);
1143 spi_eeprom_register(16 + SEEPROM2_CS);
1144 spi_eeprom_register(16 + SEEPROM3_CS);
1145 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
1148 arch_initcall(rbtx4938_spi_init);
1150 /* Minimum CLK support */
1152 struct clk *clk_get(struct device *dev, const char *id)
1154 if (!strcmp(id, "spi-baseclk"))
1155 return (struct clk *)(txx9_gbus_clock / 2 / 4);
1156 return ERR_PTR(-ENOENT);
1158 EXPORT_SYMBOL(clk_get);
1160 int clk_enable(struct clk *clk)
1164 EXPORT_SYMBOL(clk_enable);
1166 void clk_disable(struct clk *clk)
1169 EXPORT_SYMBOL(clk_disable);
1171 unsigned long clk_get_rate(struct clk *clk)
1173 return (unsigned long)clk;
1175 EXPORT_SYMBOL(clk_get_rate);
1177 void clk_put(struct clk *clk)
1180 EXPORT_SYMBOL(clk_put);