2 * Toshiba rbtx4927 specific setup
4 * Author: MontaVista Software, Inc.
7 * Copyright 2001-2002 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
20 * Copyright (C) 2000-2001 Toshiba Corporation
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/ioport.h>
49 #include <linux/interrupt.h>
51 #include <linux/platform_device.h>
52 #include <linux/delay.h>
54 #include <asm/bootinfo.h>
56 #include <asm/processor.h>
57 #include <asm/reboot.h>
59 #include <asm/txx9tmr.h>
60 #include <asm/txx9/generic.h>
61 #include <asm/txx9/pci.h>
62 #include <asm/txx9/rbtx4927.h>
63 #include <asm/txx9/tx4938.h> /* for TX4937 */
64 #ifdef CONFIG_SERIAL_TXX9
65 #include <linux/serial_core.h>
68 /* These functions are used for rebooting or halting the machine*/
69 extern void toshiba_rbtx4927_restart(char *command);
70 extern void toshiba_rbtx4927_halt(void);
71 extern void toshiba_rbtx4927_power_off(void);
72 extern void toshiba_rbtx4927_irq_setup(void);
74 char *prom_getcmdline(void);
76 static int tx4927_ccfg_toeon = 1;
79 static void __init tx4927_pci_setup(void)
81 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
82 struct pci_controller *c = &txx9_primary_pcic;
84 register_pci_controller(c);
86 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
88 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
89 TXX9_PCI_OPT_CLK_66; /* already configured */
92 writeb(1, rbtx4927_pcireset_addr);
94 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
95 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
97 tx4927_pciclk66_setup();
99 /* clear PCIC reset */
100 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
101 writeb(0, rbtx4927_pcireset_addr);
104 tx4927_report_pciclk();
105 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
106 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
107 TXX9_PCI_OPT_CLK_AUTO &&
108 txx9_pci66_check(c, 0, 0)) {
110 writeb(1, rbtx4927_pcireset_addr);
112 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
113 tx4927_pciclk66_setup();
115 /* clear PCIC reset */
116 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
117 writeb(0, rbtx4927_pcireset_addr);
119 /* Reinitialize PCIC */
120 tx4927_report_pciclk();
121 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
125 static void __init tx4937_pci_setup(void)
127 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
128 struct pci_controller *c = &txx9_primary_pcic;
130 register_pci_controller(c);
132 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
134 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
135 TXX9_PCI_OPT_CLK_66; /* already configured */
138 writeb(1, rbtx4927_pcireset_addr);
140 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
141 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
143 tx4938_pciclk66_setup();
145 /* clear PCIC reset */
146 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
147 writeb(0, rbtx4927_pcireset_addr);
150 tx4938_report_pciclk();
151 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
152 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
153 TXX9_PCI_OPT_CLK_AUTO &&
154 txx9_pci66_check(c, 0, 0)) {
156 writeb(1, rbtx4927_pcireset_addr);
158 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
159 tx4938_pciclk66_setup();
161 /* clear PCIC reset */
162 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
163 writeb(0, rbtx4927_pcireset_addr);
165 /* Reinitialize PCIC */
166 tx4938_report_pciclk();
167 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
171 static void __init rbtx4927_arch_init(void)
173 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
179 #define rbtx4927_arch_init NULL
180 #endif /* CONFIG_PCI */
182 static void __noreturn wait_forever(void)
189 void toshiba_rbtx4927_restart(char *command)
191 printk(KERN_NOTICE "System Rebooting...\n");
193 /* enable the s/w reset register */
194 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
196 /* wait for enable to be seen */
197 while ((readb(RBTX4927_SW_RESET_ENABLE) &
198 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
201 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
203 /* do something passive while waiting for reset */
209 void toshiba_rbtx4927_halt(void)
211 printk(KERN_NOTICE "System Halted\n");
217 void toshiba_rbtx4927_power_off(void)
219 toshiba_rbtx4927_halt();
223 static void __init rbtx4927_mem_setup(void)
229 /* f/w leaves this on at startup */
230 clear_c0_status(ST0_ERL);
232 /* enable caches -- HCP5 does this, pmon does not */
233 cp0_config = read_c0_config();
234 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
235 write_c0_config(cp0_config);
237 ioport_resource.end = 0xffffffff;
238 iomem_resource.end = 0xffffffff;
240 _machine_restart = toshiba_rbtx4927_restart;
241 _machine_halt = toshiba_rbtx4927_halt;
242 pm_power_off = toshiba_rbtx4927_power_off;
244 for (i = 0; i < TX4927_NR_TMR; i++)
245 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
248 txx9_alloc_pci_controller(&txx9_primary_pcic,
249 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
250 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
252 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
256 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
259 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
260 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
261 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
262 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
263 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
264 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
267 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
268 * PCIDIVMODE[10] is 0.
269 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
270 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
271 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
272 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
273 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
274 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
277 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
278 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
279 TX4938_CCFG_PCIDIVMODE_MASK) {
280 case TX4938_CCFG_PCIDIVMODE_8:
281 case TX4938_CCFG_PCIDIVMODE_4:
282 txx9_cpu_clock = 266666666; /* 266MHz */
284 case TX4938_CCFG_PCIDIVMODE_9:
285 case TX4938_CCFG_PCIDIVMODE_4_5:
286 txx9_cpu_clock = 300000000; /* 300MHz */
289 txx9_cpu_clock = 333333333; /* 333MHz */
292 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
293 TX4927_CCFG_PCIDIVMODE_MASK) {
294 case TX4927_CCFG_PCIDIVMODE_2_5:
295 case TX4927_CCFG_PCIDIVMODE_5:
296 txx9_cpu_clock = 166666666; /* 166MHz */
299 txx9_cpu_clock = 200000000; /* 200MHz */
301 /* change default value to udelay/mdelay take reasonable time */
302 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
305 /* do reset on watchdog */
306 tx4927_ccfg_set(TX4927_CCFG_WR);
307 /* enable Timeout BusError */
308 if (tx4927_ccfg_toeon)
309 tx4927_ccfg_set(TX4927_CCFG_TOE);
311 #ifdef CONFIG_SERIAL_TXX9
313 extern int early_serial_txx9_setup(struct uart_port *port);
314 struct uart_port req;
315 for(i = 0; i < 2; i++) {
316 memset(&req, 0, sizeof(req));
318 req.iotype = UPIO_MEM;
319 req.membase = (char *)(0xff1ff300 + i * 0x100);
320 req.mapbase = 0xff1ff300 + i * 0x100;
321 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
322 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
323 req.uartclk = 50000000;
324 early_serial_txx9_setup(&req);
327 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
328 argptr = prom_getcmdline();
329 if (strstr(argptr, "console=") == NULL) {
330 strcat(argptr, " console=ttyS0,38400");
335 #ifdef CONFIG_ROOT_NFS
336 argptr = prom_getcmdline();
337 if (strstr(argptr, "root=") == NULL) {
338 strcat(argptr, " root=/dev/nfs rw");
343 argptr = prom_getcmdline();
344 if (strstr(argptr, "ip=") == NULL) {
345 strcat(argptr, " ip=any");
350 static void __init rbtx4927_time_init(void)
352 mips_hpt_frequency = txx9_cpu_clock / 2;
353 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
354 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
359 static int __init toshiba_rbtx4927_rtc_init(void)
361 static struct resource __initdata res = {
363 .end = 0x1c010000 + 0x800 - 1,
364 .flags = IORESOURCE_MEM,
366 struct platform_device *dev =
367 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
368 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
371 static int __init rbtx4927_ne_init(void)
373 static struct resource __initdata res[] = {
375 .start = RBTX4927_RTL_8019_BASE,
376 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
377 .flags = IORESOURCE_IO,
379 .start = RBTX4927_RTL_8019_IRQ,
380 .flags = IORESOURCE_IRQ,
383 struct platform_device *dev =
384 platform_device_register_simple("ne", -1,
385 res, ARRAY_SIZE(res));
386 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
389 /* Watchdog support */
391 static int __init txx9_wdt_init(unsigned long base)
393 struct resource res = {
395 .end = base + 0x100 - 1,
396 .flags = IORESOURCE_MEM,
398 struct platform_device *dev =
399 platform_device_register_simple("txx9wdt", -1, &res, 1);
400 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
403 static int __init rbtx4927_wdt_init(void)
405 return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
408 static void __init rbtx4927_device_init(void)
410 toshiba_rbtx4927_rtc_init();
415 struct txx9_board_vec rbtx4927_vec __initdata = {
416 .type = MACH_TOSHIBA_RBTX4927,
417 .system = "Toshiba RBTX4927",
418 .prom_init = rbtx4927_prom_init,
419 .mem_setup = rbtx4927_mem_setup,
420 .irq_setup = rbtx4927_irq_setup,
421 .time_init = rbtx4927_time_init,
422 .device_init = rbtx4927_device_init,
423 .arch_init = rbtx4927_arch_init,
425 .pci_map_irq = rbtx4927_pci_map_irq,
428 struct txx9_board_vec rbtx4937_vec __initdata = {
429 .type = MACH_TOSHIBA_RBTX4937,
430 .system = "Toshiba RBTX4937",
431 .prom_init = rbtx4927_prom_init,
432 .mem_setup = rbtx4927_mem_setup,
433 .irq_setup = rbtx4927_irq_setup,
434 .time_init = rbtx4927_time_init,
435 .device_init = rbtx4927_device_init,
436 .arch_init = rbtx4927_arch_init,
438 .pci_map_irq = rbtx4927_pci_map_irq,