1 /* MN10300 System definitions
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
14 #include <asm/cpu-regs.h>
19 #include <linux/kernel.h>
20 #include <linux/irqflags.h>
26 struct task_struct *__switch_to(struct thread_struct *prev,
27 struct thread_struct *next,
28 struct task_struct *prev_task);
30 /* context switching is now performed out-of-line in switch_to.S */
31 #define switch_to(prev, next, last) \
33 current->thread.wchan = (u_long) __builtin_return_address(0); \
34 (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
36 current->thread.wchan = 0; \
39 #define arch_align_stack(x) (x)
41 #define nop() asm volatile ("nop")
43 #endif /* !__ASSEMBLY__ */
46 * Force strict CPU ordering.
47 * And yes, this is required on UP too when we're talking
50 * For now, "wmb()" doesn't actually do anything, as all
51 * Intel CPU's follow what Intel calls a *Processor Order*,
52 * in which all writes are seen in the program order even
55 * I expect future Intel CPU's to have a weaker ordering,
56 * but I'd also expect them to finally get their act together
57 * and add some real memory barriers if so.
59 * Some non intel clones support out of order store. wmb() ceases to be a
63 #define mb() asm volatile ("": : :"memory")
65 #define wmb() asm volatile ("": : :"memory")
69 #define smp_rmb() rmb()
70 #define smp_wmb() wmb()
72 #define smp_mb() barrier()
73 #define smp_rmb() barrier()
74 #define smp_wmb() barrier()
77 #define set_mb(var, value) do { var = value; mb(); } while (0)
78 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
80 #define read_barrier_depends() do {} while (0)
81 #define smp_read_barrier_depends() do {} while (0)
83 /*****************************************************************************/
85 * MN10300 doesn't actually have an exchange instruction
89 struct __xchg_dummy { unsigned long a[100]; };
90 #define __xg(x) ((struct __xchg_dummy *)(x))
93 unsigned long __xchg(volatile unsigned long *m, unsigned long val)
98 local_irq_save(flags);
101 local_irq_restore(flags);
105 #define xchg(ptr, v) \
106 ((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \
109 static inline unsigned long __cmpxchg(volatile unsigned long *m,
110 unsigned long old, unsigned long new)
112 unsigned long retval;
115 local_irq_save(flags);
119 local_irq_restore(flags);
123 #define cmpxchg(ptr, o, n) \
124 ((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \
125 (unsigned long)(o), \
128 #endif /* !__ASSEMBLY__ */
130 #endif /* __KERNEL__ */
131 #endif /* _ASM_SYSTEM_H */