2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
7 * Copyright (C) 1999 SuSE GmbH Nuernberg
8 * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
10 * Cache and TLB management
14 #include <linux/init.h>
15 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/seq_file.h>
19 #include <linux/pagemap.h>
20 #include <linux/sched.h>
22 #include <asm/cache.h>
23 #include <asm/cacheflush.h>
24 #include <asm/tlbflush.h>
26 #include <asm/pgalloc.h>
27 #include <asm/processor.h>
28 #include <asm/sections.h>
29 #include <asm/shmparam.h>
31 int split_tlb __read_mostly;
32 int dcache_stride __read_mostly;
33 int icache_stride __read_mostly;
34 EXPORT_SYMBOL(dcache_stride);
36 void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
37 EXPORT_SYMBOL(flush_dcache_page_asm);
38 void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
41 /* On some machines (e.g. ones with the Merced bus), there can be
42 * only a single PxTLB broadcast at a time; this must be guaranteed
43 * by software. We put a spinlock around all TLB flushes to
46 DEFINE_SPINLOCK(pa_tlb_lock);
48 struct pdc_cache_info cache_info __read_mostly;
50 static struct pdc_btlb_info btlb_info __read_mostly;
55 flush_data_cache(void)
57 on_each_cpu(flush_data_cache_local, NULL, 1);
60 flush_instruction_cache(void)
62 on_each_cpu(flush_instruction_cache_local, NULL, 1);
67 flush_cache_all_local(void)
69 flush_instruction_cache_local(NULL);
70 flush_data_cache_local(NULL);
72 EXPORT_SYMBOL(flush_cache_all_local);
74 /* Virtual address of pfn. */
75 #define pfn_va(pfn) __va(PFN_PHYS(pfn))
78 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
80 unsigned long pfn = pte_pfn(*ptep);
83 /* We don't have pte special. As a result, we can be called with
84 an invalid pfn and we don't need to flush the kernel dcache page.
85 This occurs with FireGL card in C8000. */
89 page = pfn_to_page(pfn);
90 if (page_mapping(page) && test_bit(PG_dcache_dirty, &page->flags)) {
91 flush_kernel_dcache_page_addr(pfn_va(pfn));
92 clear_bit(PG_dcache_dirty, &page->flags);
93 } else if (parisc_requires_coherency())
94 flush_kernel_dcache_page_addr(pfn_va(pfn));
98 show_cache_info(struct seq_file *m)
102 seq_printf(m, "I-cache\t\t: %ld KB\n",
103 cache_info.ic_size/1024 );
104 if (cache_info.dc_loop != 1)
105 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
106 seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
107 cache_info.dc_size/1024,
108 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
109 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
110 ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
111 seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
114 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
118 /* BTLB - Block TLB */
119 if (btlb_info.max_size==0) {
120 seq_printf(m, "BTLB\t\t: not supported\n" );
123 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
124 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
125 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
126 btlb_info.max_size, (int)4096,
127 btlb_info.max_size>>8,
128 btlb_info.fixed_range_info.num_i,
129 btlb_info.fixed_range_info.num_d,
130 btlb_info.fixed_range_info.num_comb,
131 btlb_info.variable_range_info.num_i,
132 btlb_info.variable_range_info.num_d,
133 btlb_info.variable_range_info.num_comb
140 parisc_cache_init(void)
142 if (pdc_cache_info(&cache_info) < 0)
143 panic("parisc_cache_init: pdc_cache_info failed");
146 printk("ic_size %lx dc_size %lx it_size %lx\n",
151 printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
153 cache_info.dc_stride,
157 printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
158 *(unsigned long *) (&cache_info.dc_conf),
159 cache_info.dc_conf.cc_alias,
160 cache_info.dc_conf.cc_block,
161 cache_info.dc_conf.cc_line,
162 cache_info.dc_conf.cc_shift);
163 printk(" wt %d sh %d cst %d hv %d\n",
164 cache_info.dc_conf.cc_wt,
165 cache_info.dc_conf.cc_sh,
166 cache_info.dc_conf.cc_cst,
167 cache_info.dc_conf.cc_hv);
169 printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
171 cache_info.ic_stride,
175 printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
176 *(unsigned long *) (&cache_info.ic_conf),
177 cache_info.ic_conf.cc_alias,
178 cache_info.ic_conf.cc_block,
179 cache_info.ic_conf.cc_line,
180 cache_info.ic_conf.cc_shift);
181 printk(" wt %d sh %d cst %d hv %d\n",
182 cache_info.ic_conf.cc_wt,
183 cache_info.ic_conf.cc_sh,
184 cache_info.ic_conf.cc_cst,
185 cache_info.ic_conf.cc_hv);
187 printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
188 cache_info.dt_conf.tc_sh,
189 cache_info.dt_conf.tc_page,
190 cache_info.dt_conf.tc_cst,
191 cache_info.dt_conf.tc_aid,
192 cache_info.dt_conf.tc_pad1);
194 printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
195 cache_info.it_conf.tc_sh,
196 cache_info.it_conf.tc_page,
197 cache_info.it_conf.tc_cst,
198 cache_info.it_conf.tc_aid,
199 cache_info.it_conf.tc_pad1);
203 if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
204 if (cache_info.dt_conf.tc_sh == 2)
205 printk(KERN_WARNING "Unexpected TLB configuration. "
206 "Will flush I/D separately (could be optimized).\n");
211 /* "New and Improved" version from Jim Hull
212 * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
213 * The following CAFL_STRIDE is an optimized version, see
214 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
215 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
217 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
218 dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
219 icache_stride = CAFL_STRIDE(cache_info.ic_conf);
223 if (pdc_btlb_info(&btlb_info) < 0) {
224 memset(&btlb_info, 0, sizeof btlb_info);
228 if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
229 PDC_MODEL_NVA_UNSUPPORTED) {
230 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
232 panic("SMP kernel required to avoid non-equivalent aliasing");
237 void disable_sr_hashing(void)
239 int srhash_type, retval;
240 unsigned long space_bits;
242 switch (boot_cpu_data.cpu_type) {
243 case pcx: /* We shouldn't get this far. setup.c should prevent it. */
250 srhash_type = SRHASH_PCXST;
254 srhash_type = SRHASH_PCXL;
257 case pcxl2: /* pcxl2 doesn't support space register hashing */
260 default: /* Currently all PA2.0 machines use the same ins. sequence */
261 srhash_type = SRHASH_PA20;
265 disable_sr_hashing_asm(srhash_type);
267 retval = pdc_spaceid_bits(&space_bits);
268 /* If this procedure isn't implemented, don't panic. */
269 if (retval < 0 && retval != PDC_BAD_OPTION)
270 panic("pdc_spaceid_bits call failed.\n");
272 panic("SpaceID hashing is still on!\n");
276 __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
277 unsigned long physaddr)
280 flush_dcache_page_asm(physaddr, vmaddr);
281 if (vma->vm_flags & VM_EXEC)
282 flush_icache_page_asm(physaddr, vmaddr);
286 void flush_dcache_page(struct page *page)
288 struct address_space *mapping = page_mapping(page);
289 struct vm_area_struct *mpnt;
290 unsigned long offset;
291 unsigned long addr, old_addr = 0;
294 if (mapping && !mapping_mapped(mapping)) {
295 set_bit(PG_dcache_dirty, &page->flags);
299 flush_kernel_dcache_page(page);
304 pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
306 /* We have carefully arranged in arch_get_unmapped_area() that
307 * *any* mappings of a file are always congruently mapped (whether
308 * declared as MAP_PRIVATE or MAP_SHARED), so we only need
309 * to flush one address here for them all to become coherent */
311 flush_dcache_mmap_lock(mapping);
312 vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
313 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
314 addr = mpnt->vm_start + offset;
316 /* The TLB is the engine of coherence on parisc: The
317 * CPU is entitled to speculate any page with a TLB
318 * mapping, so here we kill the mapping then flush the
319 * page along a special flush only alias mapping.
320 * This guarantees that the page is no-longer in the
321 * cache for any process and nor may it be
322 * speculatively read in (until the user or kernel
323 * specifically accesses it, of course) */
325 flush_tlb_page(mpnt, addr);
326 if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
327 != (addr & (SHM_COLOUR - 1))) {
328 __flush_cache_page(mpnt, addr, page_to_phys(page));
330 printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
334 flush_dcache_mmap_unlock(mapping);
336 EXPORT_SYMBOL(flush_dcache_page);
338 /* Defined in arch/parisc/kernel/pacache.S */
339 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
340 EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
341 EXPORT_SYMBOL(flush_data_cache_local);
342 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
344 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
345 static unsigned long parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
347 #define FLUSH_TLB_THRESHOLD (2*1024*1024) /* 2MB initial TLB threshold */
348 static unsigned long parisc_tlb_flush_threshold __read_mostly = FLUSH_TLB_THRESHOLD;
350 void __init parisc_setup_cache_timing(void)
352 unsigned long rangetime, alltime;
353 unsigned long size, start;
354 unsigned long threshold;
358 alltime = mfctl(16) - alltime;
360 size = (unsigned long)(_end - _text);
361 rangetime = mfctl(16);
362 flush_kernel_dcache_range((unsigned long)_text, size);
363 rangetime = mfctl(16) - rangetime;
365 printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
366 alltime, size, rangetime);
368 threshold = L1_CACHE_ALIGN(size * alltime / rangetime);
369 if (threshold > cache_info.dc_size)
370 threshold = cache_info.dc_size;
372 parisc_cache_flush_threshold = threshold;
373 printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",
374 parisc_cache_flush_threshold/1024);
376 /* calculate TLB flush threshold */
380 alltime = mfctl(16) - alltime;
383 start = (unsigned long) _text;
384 rangetime = mfctl(16);
385 while (start < (unsigned long) _end) {
386 flush_tlb_kernel_range(start, start + PAGE_SIZE);
390 rangetime = mfctl(16) - rangetime;
392 printk(KERN_DEBUG "Whole TLB flush %lu cycles, flushing %lu bytes %lu cycles\n",
393 alltime, size, rangetime);
395 threshold = PAGE_ALIGN(num_online_cpus() * size * alltime / rangetime);
397 parisc_tlb_flush_threshold = threshold;
398 printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",
399 parisc_tlb_flush_threshold/1024);
402 extern void purge_kernel_dcache_page_asm(unsigned long);
403 extern void clear_user_page_asm(void *, unsigned long);
404 extern void copy_user_page_asm(void *, void *, unsigned long);
406 void flush_kernel_dcache_page_addr(void *addr)
410 flush_kernel_dcache_page_asm(addr);
411 purge_tlb_start(flags);
413 purge_tlb_end(flags);
415 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
417 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
420 /* Copy using kernel mapping. No coherency is needed (all in
421 kunmap) for the `to' page. However, the `from' page needs to
422 be flushed through a mapping equivalent to the user mapping
423 before it can be accessed through the kernel mapping. */
425 flush_dcache_page_asm(__pa(vfrom), vaddr);
427 copy_page_asm(vto, vfrom);
429 EXPORT_SYMBOL(copy_user_page);
431 /* __flush_tlb_range()
433 * returns 1 if all TLBs were flushed.
435 int __flush_tlb_range(unsigned long sid, unsigned long start,
438 unsigned long flags, size;
440 size = (end - start);
441 if (size >= parisc_tlb_flush_threshold) {
446 /* Purge TLB entries for small ranges using the pdtlb and
447 pitlb instructions. These instructions execute locally
448 but cause a purge request to be broadcast to other TLBs. */
449 if (likely(!split_tlb)) {
450 while (start < end) {
451 purge_tlb_start(flags);
454 purge_tlb_end(flags);
461 while (start < end) {
462 purge_tlb_start(flags);
466 purge_tlb_end(flags);
472 static void cacheflush_h_tmp_function(void *dummy)
474 flush_cache_all_local();
477 void flush_cache_all(void)
479 on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
482 static inline unsigned long mm_total_size(struct mm_struct *mm)
484 struct vm_area_struct *vma;
485 unsigned long usize = 0;
487 for (vma = mm->mmap; vma; vma = vma->vm_next)
488 usize += vma->vm_end - vma->vm_start;
492 static inline pte_t *get_ptep(pgd_t *pgd, unsigned long addr)
496 if (!pgd_none(*pgd)) {
497 pud_t *pud = pud_offset(pgd, addr);
498 if (!pud_none(*pud)) {
499 pmd_t *pmd = pmd_offset(pud, addr);
501 ptep = pte_offset_map(pmd, addr);
507 void flush_cache_mm(struct mm_struct *mm)
509 struct vm_area_struct *vma;
512 /* Flushing the whole cache on each cpu takes forever on
513 rp3440, etc. So, avoid it if the mm isn't too big. */
514 if (mm_total_size(mm) >= parisc_cache_flush_threshold) {
519 if (mm->context == mfsp(3)) {
520 for (vma = mm->mmap; vma; vma = vma->vm_next) {
521 flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
522 if ((vma->vm_flags & VM_EXEC) == 0)
524 flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
530 for (vma = mm->mmap; vma; vma = vma->vm_next) {
533 for (addr = vma->vm_start; addr < vma->vm_end;
536 pte_t *ptep = get_ptep(pgd, addr);
539 pfn = pte_pfn(*ptep);
542 __flush_cache_page(vma, addr, PFN_PHYS(pfn));
548 flush_user_dcache_range(unsigned long start, unsigned long end)
550 if ((end - start) < parisc_cache_flush_threshold)
551 flush_user_dcache_range_asm(start,end);
557 flush_user_icache_range(unsigned long start, unsigned long end)
559 if ((end - start) < parisc_cache_flush_threshold)
560 flush_user_icache_range_asm(start,end);
562 flush_instruction_cache();
565 void flush_cache_range(struct vm_area_struct *vma,
566 unsigned long start, unsigned long end)
571 BUG_ON(!vma->vm_mm->context);
573 if ((end - start) >= parisc_cache_flush_threshold) {
578 if (vma->vm_mm->context == mfsp(3)) {
579 flush_user_dcache_range_asm(start, end);
580 if (vma->vm_flags & VM_EXEC)
581 flush_user_icache_range_asm(start, end);
585 pgd = vma->vm_mm->pgd;
586 for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
588 pte_t *ptep = get_ptep(pgd, addr);
591 pfn = pte_pfn(*ptep);
593 __flush_cache_page(vma, addr, PFN_PHYS(pfn));
598 flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
600 BUG_ON(!vma->vm_mm->context);
602 if (pfn_valid(pfn)) {
603 flush_tlb_page(vma, vmaddr);
604 __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));