2 * PARISC TLB and cache flushing support
3 * Copyright (C) 2000-2001 Hewlett-Packard (John Marvin)
4 * Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org)
5 * Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * NOTE: fdc,fic, and pdc instructions that use base register modification
24 * should only use index and base registers that are not shadowed,
25 * so that the fast path emulation in the non access miss handler
36 #include <asm/assembly.h>
37 #include <asm/pgtable.h>
38 #include <asm/cache.h>
39 #include <linux/linkage.h>
44 ENTRY(flush_tlb_all_local)
50 * The pitlbe and pdtlbe instructions should only be used to
51 * flush the entire tlb. Also, there needs to be no intervening
52 * tlb operations, e.g. tlb misses, so the operation needs
53 * to happen in real mode with all interruptions disabled.
56 /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
57 rsm PSW_SM_I, %r19 /* save I-bit state */
65 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
66 mtctl %r0, %cr17 /* Clear IIASQ tail */
67 mtctl %r0, %cr17 /* Clear IIASQ head */
68 mtctl %r1, %cr18 /* IIAOQ head */
70 mtctl %r1, %cr18 /* IIAOQ tail */
71 load32 REAL_MODE_PSW, %r1
76 1: load32 PA(cache_info), %r1
78 /* Flush Instruction Tlb */
80 LDREG ITLB_SID_BASE(%r1), %r20
81 LDREG ITLB_SID_STRIDE(%r1), %r21
82 LDREG ITLB_SID_COUNT(%r1), %r22
83 LDREG ITLB_OFF_BASE(%r1), %arg0
84 LDREG ITLB_OFF_STRIDE(%r1), %arg1
85 LDREG ITLB_OFF_COUNT(%r1), %arg2
86 LDREG ITLB_LOOP(%r1), %arg3
88 addib,COND(=) -1, %arg3, fitoneloop /* Preadjust and test */
89 movb,<,n %arg3, %r31, fitdone /* If loop < 0, skip */
90 copy %arg0, %r28 /* Init base addr */
92 fitmanyloop: /* Loop if LOOP >= 2 */
94 add %r21, %r20, %r20 /* increment space */
95 copy %arg2, %r29 /* Init middle loop count */
97 fitmanymiddle: /* Loop if LOOP >= 2 */
98 addib,COND(>) -1, %r31, fitmanymiddle /* Adjusted inner loop decr */
99 pitlbe %r0(%sr1, %r28)
100 pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */
101 addib,COND(>) -1, %r29, fitmanymiddle /* Middle loop decr */
102 copy %arg3, %r31 /* Re-init inner loop count */
104 movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */
105 addib,COND(<=),n -1, %r22, fitdone /* Outer loop count decr */
107 fitoneloop: /* Loop if LOOP = 1 */
109 copy %arg0, %r28 /* init base addr */
110 copy %arg2, %r29 /* init middle loop count */
112 fitonemiddle: /* Loop if LOOP = 1 */
113 addib,COND(>) -1, %r29, fitonemiddle /* Middle loop count decr */
114 pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */
116 addib,COND(>) -1, %r22, fitoneloop /* Outer loop count decr */
117 add %r21, %r20, %r20 /* increment space */
123 LDREG DTLB_SID_BASE(%r1), %r20
124 LDREG DTLB_SID_STRIDE(%r1), %r21
125 LDREG DTLB_SID_COUNT(%r1), %r22
126 LDREG DTLB_OFF_BASE(%r1), %arg0
127 LDREG DTLB_OFF_STRIDE(%r1), %arg1
128 LDREG DTLB_OFF_COUNT(%r1), %arg2
129 LDREG DTLB_LOOP(%r1), %arg3
131 addib,COND(=) -1, %arg3, fdtoneloop /* Preadjust and test */
132 movb,<,n %arg3, %r31, fdtdone /* If loop < 0, skip */
133 copy %arg0, %r28 /* Init base addr */
135 fdtmanyloop: /* Loop if LOOP >= 2 */
137 add %r21, %r20, %r20 /* increment space */
138 copy %arg2, %r29 /* Init middle loop count */
140 fdtmanymiddle: /* Loop if LOOP >= 2 */
141 addib,COND(>) -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */
142 pdtlbe %r0(%sr1, %r28)
143 pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */
144 addib,COND(>) -1, %r29, fdtmanymiddle /* Middle loop decr */
145 copy %arg3, %r31 /* Re-init inner loop count */
147 movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */
148 addib,COND(<=),n -1, %r22,fdtdone /* Outer loop count decr */
150 fdtoneloop: /* Loop if LOOP = 1 */
152 copy %arg0, %r28 /* init base addr */
153 copy %arg2, %r29 /* init middle loop count */
155 fdtonemiddle: /* Loop if LOOP = 1 */
156 addib,COND(>) -1, %r29, fdtonemiddle /* Middle loop count decr */
157 pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */
159 addib,COND(>) -1, %r22, fdtoneloop /* Outer loop count decr */
160 add %r21, %r20, %r20 /* increment space */
165 * Switch back to virtual mode
176 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
177 mtctl %r0, %cr17 /* Clear IIASQ tail */
178 mtctl %r0, %cr17 /* Clear IIASQ head */
179 mtctl %r1, %cr18 /* IIAOQ head */
181 mtctl %r1, %cr18 /* IIAOQ tail */
182 load32 KERNEL_PSW, %r1
183 or %r1, %r19, %r1 /* I-bit to state on entry */
184 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
193 ENDPROC(flush_tlb_all_local)
195 .import cache_info,data
197 ENTRY(flush_instruction_cache_local)
202 load32 cache_info, %r1
204 /* Flush Instruction Cache */
206 LDREG ICACHE_BASE(%r1), %arg0
207 LDREG ICACHE_STRIDE(%r1), %arg1
208 LDREG ICACHE_COUNT(%r1), %arg2
209 LDREG ICACHE_LOOP(%r1), %arg3
210 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
212 addib,COND(=) -1, %arg3, fioneloop /* Preadjust and test */
213 movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */
215 fimanyloop: /* Loop if LOOP >= 2 */
216 addib,COND(>) -1, %r31, fimanyloop /* Adjusted inner loop decr */
217 fice %r0(%sr1, %arg0)
218 fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */
219 movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */
220 addib,COND(<=),n -1, %arg2, fisync /* Outer loop decr */
222 fioneloop: /* Loop if LOOP = 1 */
223 /* Some implementations may flush with a single fice instruction */
224 cmpib,COND(>>=),n 15, %arg2, fioneloop2
227 fice,m %arg1(%sr1, %arg0)
228 fice,m %arg1(%sr1, %arg0)
229 fice,m %arg1(%sr1, %arg0)
230 fice,m %arg1(%sr1, %arg0)
231 fice,m %arg1(%sr1, %arg0)
232 fice,m %arg1(%sr1, %arg0)
233 fice,m %arg1(%sr1, %arg0)
234 fice,m %arg1(%sr1, %arg0)
235 fice,m %arg1(%sr1, %arg0)
236 fice,m %arg1(%sr1, %arg0)
237 fice,m %arg1(%sr1, %arg0)
238 fice,m %arg1(%sr1, %arg0)
239 fice,m %arg1(%sr1, %arg0)
240 fice,m %arg1(%sr1, %arg0)
241 fice,m %arg1(%sr1, %arg0)
242 addib,COND(>) -16, %arg2, fioneloop1
243 fice,m %arg1(%sr1, %arg0)
246 cmpb,COND(=),n %arg2, %r0, fisync /* Predict branch taken */
249 addib,COND(>) -1, %arg2, fioneloop2 /* Outer loop count decr */
250 fice,m %arg1(%sr1, %arg0) /* Fice for one loop */
254 mtsm %r22 /* restore I-bit */
260 ENDPROC(flush_instruction_cache_local)
263 .import cache_info, data
264 ENTRY(flush_data_cache_local)
269 load32 cache_info, %r1
271 /* Flush Data Cache */
273 LDREG DCACHE_BASE(%r1), %arg0
274 LDREG DCACHE_STRIDE(%r1), %arg1
275 LDREG DCACHE_COUNT(%r1), %arg2
276 LDREG DCACHE_LOOP(%r1), %arg3
277 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
279 addib,COND(=) -1, %arg3, fdoneloop /* Preadjust and test */
280 movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */
282 fdmanyloop: /* Loop if LOOP >= 2 */
283 addib,COND(>) -1, %r31, fdmanyloop /* Adjusted inner loop decr */
284 fdce %r0(%sr1, %arg0)
285 fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */
286 movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */
287 addib,COND(<=),n -1, %arg2, fdsync /* Outer loop decr */
289 fdoneloop: /* Loop if LOOP = 1 */
290 /* Some implementations may flush with a single fdce instruction */
291 cmpib,COND(>>=),n 15, %arg2, fdoneloop2
294 fdce,m %arg1(%sr1, %arg0)
295 fdce,m %arg1(%sr1, %arg0)
296 fdce,m %arg1(%sr1, %arg0)
297 fdce,m %arg1(%sr1, %arg0)
298 fdce,m %arg1(%sr1, %arg0)
299 fdce,m %arg1(%sr1, %arg0)
300 fdce,m %arg1(%sr1, %arg0)
301 fdce,m %arg1(%sr1, %arg0)
302 fdce,m %arg1(%sr1, %arg0)
303 fdce,m %arg1(%sr1, %arg0)
304 fdce,m %arg1(%sr1, %arg0)
305 fdce,m %arg1(%sr1, %arg0)
306 fdce,m %arg1(%sr1, %arg0)
307 fdce,m %arg1(%sr1, %arg0)
308 fdce,m %arg1(%sr1, %arg0)
309 addib,COND(>) -16, %arg2, fdoneloop1
310 fdce,m %arg1(%sr1, %arg0)
313 cmpb,COND(=),n %arg2, %r0, fdsync /* Predict branch taken */
316 addib,COND(>) -1, %arg2, fdoneloop2 /* Outer loop count decr */
317 fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */
322 mtsm %r22 /* restore I-bit */
328 ENDPROC(flush_data_cache_local)
332 /* Macros to serialize TLB purge operations on SMP. */
334 .macro tlb_lock la,flags,tmp
336 ldil L%pa_tlb_lock,%r1
337 ldo R%pa_tlb_lock(%r1),\la
349 .macro tlb_unlock la,flags,tmp
357 /* Clear page using kernel mapping. */
359 ENTRY(clear_page_asm)
366 /* Unroll the loop. */
367 ldi (PAGE_SIZE / 128), %r1
387 /* Note reverse branch hint for addib is taken. */
388 addib,COND(>),n -1, %r1, 1b
394 * Note that until (if) we start saving the full 64-bit register
395 * values on interrupt, we can't use std on a 32 bit kernel.
397 ldi (PAGE_SIZE / 64), %r1
417 addib,COND(>),n -1, %r1, 1b
425 ENDPROC(clear_page_asm)
427 /* Copy page using kernel mapping. */
435 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
436 * Unroll the loop by hand and arrange insn appropriately.
437 * Prefetch doesn't improve performance on rp3440.
438 * GCC probably can do this just as well...
441 ldi (PAGE_SIZE / 128), %r1
485 /* Note reverse branch hint for addib is taken. */
486 addib,COND(>),n -1, %r1, 1b
492 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
493 * bundles (very restricted rules for bundling).
494 * Note that until (if) we start saving
495 * the full 64 bit register values on interrupt, we can't
496 * use ldd/std on a 32 bit kernel.
499 ldi (PAGE_SIZE / 64), %r1
535 addib,COND(>),n -1, %r1, 1b
543 ENDPROC(copy_page_asm)
546 * NOTE: Code in clear_user_page has a hard coded dependency on the
547 * maximum alias boundary being 4 Mb. We've been assured by the
548 * parisc chip designers that there will not ever be a parisc
549 * chip with a larger alias boundary (Never say never :-) ).
551 * Subtle: the dtlb miss handlers support the temp alias region by
552 * "knowing" that if a dtlb miss happens within the temp alias
553 * region it must have occurred while in clear_user_page. Since
554 * this routine makes use of processor local translations, we
555 * don't want to insert them into the kernel page table. Instead,
556 * we load up some general registers (they need to be registers
557 * which aren't shadowed) with the physical page numbers (preshifted
558 * for tlb insertion) needed to insert the translations. When we
559 * miss on the translation, the dtlb miss handler inserts the
560 * translation into the tlb using these values:
562 * %r26 physical page (shifted for tlb insert) of "to" translation
563 * %r23 physical page (shifted for tlb insert) of "from" translation
566 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
567 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
568 .macro convert_phys_for_tlb_insert20 phys
569 extrd,u \phys, 56-PAGE_ADD_SHIFT, 32-PAGE_ADD_SHIFT, \phys
570 #if _PAGE_SIZE_ENCODING_DEFAULT
571 depdi _PAGE_SIZE_ENCODING_DEFAULT, 63, (63-58), \phys
576 * We can't do this since copy_user_page is used to bring in
577 * file data that might have instructions. Since the data would
578 * then need to be flushed out so the i-fetch can see it, it
579 * makes more sense to just copy through the kernel translation
582 * I'm still keeping this around because it may be possible to
583 * use it if more information is passed into copy_user_page().
584 * Have to do some measurements to see if it is worthwhile to
585 * lobby for such a change.
589 ENTRY(copy_user_page_asm)
594 /* Convert virtual `to' and `from' addresses to physical addresses.
595 Move `from' physical address to non shadowed register. */
596 ldil L%(__PAGE_OFFSET), %r1
600 ldil L%(TMPALIAS_MAP_START), %r28
602 #if (TMPALIAS_MAP_START >= 0x80000000)
603 depdi 0, 31,32, %r28 /* clear any sign extension */
605 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
606 convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */
607 depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
608 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
610 depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */
612 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
613 extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */
614 depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */
615 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
617 depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */
620 /* Purge any old translations */
626 tlb_lock %r20,%r21,%r22
629 tlb_unlock %r20,%r21,%r22
633 /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
634 * Unroll the loop by hand and arrange insn appropriately.
635 * GCC probably can do this just as well.
639 ldi (PAGE_SIZE / 128), %r1
683 /* conditional branches nullify on forward taken branch, and on
684 * non-taken backward branch. Note that .+4 is a backwards branch.
685 * The ldd should only get executed if the branch is taken.
687 addib,COND(>),n -1, %r1, 1b /* bundle 10 */
688 ldd 0(%r29), %r19 /* start next loads */
691 ldi (PAGE_SIZE / 64), %r1
694 * This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
695 * bundles (very restricted rules for bundling). It probably
696 * does OK on PCXU and better, but we could do better with
697 * ldd/std instructions. Note that until (if) we start saving
698 * the full 64 bit register values on interrupt, we can't
699 * use ldd/std on a 32 bit kernel.
736 addib,COND(>) -1, %r1,1b
745 ENDPROC(copy_user_page_asm)
747 ENTRY(clear_user_page_asm)
754 ldil L%(TMPALIAS_MAP_START), %r28
756 #if (TMPALIAS_MAP_START >= 0x80000000)
757 depdi 0, 31,32, %r28 /* clear any sign extension */
759 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
760 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
761 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
763 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
764 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
765 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
768 /* Purge any old translation */
773 tlb_lock %r20,%r21,%r22
775 tlb_unlock %r20,%r21,%r22
779 ldi (PAGE_SIZE / 128), %r1
781 /* PREFETCH (Write) has not (yet) been proven to help here */
782 /* #define PREFETCHW_OP ldd 256(%0), %r0 */
800 addib,COND(>) -1, %r1, 1b
803 #else /* ! CONFIG_64BIT */
804 ldi (PAGE_SIZE / 64), %r1
822 addib,COND(>) -1, %r1, 1b
824 #endif /* CONFIG_64BIT */
831 ENDPROC(clear_user_page_asm)
833 ENTRY(flush_dcache_page_asm)
838 ldil L%(TMPALIAS_MAP_START), %r28
840 #if (TMPALIAS_MAP_START >= 0x80000000)
841 depdi 0, 31,32, %r28 /* clear any sign extension */
843 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
844 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
845 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
847 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
848 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
849 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
852 /* Purge any old translation */
857 tlb_lock %r20,%r21,%r22
859 tlb_unlock %r20,%r21,%r22
862 ldil L%dcache_stride, %r1
863 ldw R%dcache_stride(%r1), r31
866 depdi,z 1, 63-PAGE_SHIFT,1, %r25
868 depwi,z 1, 31-PAGE_SHIFT,1, %r25
889 cmpb,COND(<<) %r28, %r25,1b
897 tlb_lock %r20,%r21,%r22
899 tlb_unlock %r20,%r21,%r22
907 ENDPROC(flush_dcache_page_asm)
909 ENTRY(flush_icache_page_asm)
914 ldil L%(TMPALIAS_MAP_START), %r28
916 #if (TMPALIAS_MAP_START >= 0x80000000)
917 depdi 0, 31,32, %r28 /* clear any sign extension */
919 convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
920 depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
921 depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
923 extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
924 depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
925 depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
928 /* Purge any old translation. Note that the FIC instruction
929 * may use either the instruction or data TLB. Given that we
930 * have a flat address space, it's not clear which TLB will be
931 * used. So, we purge both entries. */
935 pitlb,l %r0(%sr4,%r28)
937 tlb_lock %r20,%r21,%r22
940 tlb_unlock %r20,%r21,%r22
943 ldil L%icache_stride, %r1
944 ldw R%icache_stride(%r1), %r31
947 depdi,z 1, 63-PAGE_SHIFT,1, %r25
949 depwi,z 1, 31-PAGE_SHIFT,1, %r25
955 /* fic only has the type 26 form on PA1.1, requiring an
956 * explicit space specification, so use %sr4 */
957 1: fic,m %r31(%sr4,%r28)
958 fic,m %r31(%sr4,%r28)
959 fic,m %r31(%sr4,%r28)
960 fic,m %r31(%sr4,%r28)
961 fic,m %r31(%sr4,%r28)
962 fic,m %r31(%sr4,%r28)
963 fic,m %r31(%sr4,%r28)
964 fic,m %r31(%sr4,%r28)
965 fic,m %r31(%sr4,%r28)
966 fic,m %r31(%sr4,%r28)
967 fic,m %r31(%sr4,%r28)
968 fic,m %r31(%sr4,%r28)
969 fic,m %r31(%sr4,%r28)
970 fic,m %r31(%sr4,%r28)
971 fic,m %r31(%sr4,%r28)
972 cmpb,COND(<<) %r28, %r25,1b
973 fic,m %r31(%sr4,%r28)
979 pitlb,l %r0(%sr4,%r25)
981 tlb_lock %r20,%r21,%r22
984 tlb_unlock %r20,%r21,%r22
992 ENDPROC(flush_icache_page_asm)
994 ENTRY(flush_kernel_dcache_page_asm)
999 ldil L%dcache_stride, %r1
1000 ldw R%dcache_stride(%r1), %r23
1003 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1005 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1007 add %r26, %r25, %r25
1008 sub %r25, %r23, %r25
1026 cmpb,COND(<<) %r26, %r25,1b
1035 ENDPROC(flush_kernel_dcache_page_asm)
1037 ENTRY(purge_kernel_dcache_page_asm)
1042 ldil L%dcache_stride, %r1
1043 ldw R%dcache_stride(%r1), %r23
1046 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1048 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1050 add %r26, %r25, %r25
1051 sub %r25, %r23, %r25
1068 cmpb,COND(<<) %r26, %r25, 1b
1077 ENDPROC(purge_kernel_dcache_page_asm)
1079 ENTRY(flush_user_dcache_range_asm)
1084 ldil L%dcache_stride, %r1
1085 ldw R%dcache_stride(%r1), %r23
1087 ANDCM %r26, %r21, %r26
1089 1: cmpb,COND(<<),n %r26, %r25, 1b
1090 fdc,m %r23(%sr3, %r26)
1098 ENDPROC(flush_user_dcache_range_asm)
1100 ENTRY(flush_kernel_dcache_range_asm)
1105 ldil L%dcache_stride, %r1
1106 ldw R%dcache_stride(%r1), %r23
1108 ANDCM %r26, %r21, %r26
1110 1: cmpb,COND(<<),n %r26, %r25,1b
1120 ENDPROC(flush_kernel_dcache_range_asm)
1122 ENTRY(flush_user_icache_range_asm)
1127 ldil L%icache_stride, %r1
1128 ldw R%icache_stride(%r1), %r23
1130 ANDCM %r26, %r21, %r26
1132 1: cmpb,COND(<<),n %r26, %r25,1b
1133 fic,m %r23(%sr3, %r26)
1141 ENDPROC(flush_user_icache_range_asm)
1143 ENTRY(flush_kernel_icache_page)
1148 ldil L%icache_stride, %r1
1149 ldw R%icache_stride(%r1), %r23
1152 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1154 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1156 add %r26, %r25, %r25
1157 sub %r25, %r23, %r25
1160 1: fic,m %r23(%sr4, %r26)
1161 fic,m %r23(%sr4, %r26)
1162 fic,m %r23(%sr4, %r26)
1163 fic,m %r23(%sr4, %r26)
1164 fic,m %r23(%sr4, %r26)
1165 fic,m %r23(%sr4, %r26)
1166 fic,m %r23(%sr4, %r26)
1167 fic,m %r23(%sr4, %r26)
1168 fic,m %r23(%sr4, %r26)
1169 fic,m %r23(%sr4, %r26)
1170 fic,m %r23(%sr4, %r26)
1171 fic,m %r23(%sr4, %r26)
1172 fic,m %r23(%sr4, %r26)
1173 fic,m %r23(%sr4, %r26)
1174 fic,m %r23(%sr4, %r26)
1175 cmpb,COND(<<) %r26, %r25, 1b
1176 fic,m %r23(%sr4, %r26)
1184 ENDPROC(flush_kernel_icache_page)
1186 ENTRY(flush_kernel_icache_range_asm)
1191 ldil L%icache_stride, %r1
1192 ldw R%icache_stride(%r1), %r23
1194 ANDCM %r26, %r21, %r26
1196 1: cmpb,COND(<<),n %r26, %r25, 1b
1197 fic,m %r23(%sr4, %r26)
1204 ENDPROC(flush_kernel_icache_range_asm)
1206 /* align should cover use of rfi in disable_sr_hashing_asm and
1210 ENTRY(disable_sr_hashing_asm)
1216 * Switch to real mode
1227 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1228 mtctl %r0, %cr17 /* Clear IIASQ tail */
1229 mtctl %r0, %cr17 /* Clear IIASQ head */
1230 mtctl %r1, %cr18 /* IIAOQ head */
1232 mtctl %r1, %cr18 /* IIAOQ tail */
1233 load32 REAL_MODE_PSW, %r1
1238 1: cmpib,=,n SRHASH_PCXST, %r26,srdis_pcxs
1239 cmpib,=,n SRHASH_PCXL, %r26,srdis_pcxl
1240 cmpib,=,n SRHASH_PA20, %r26,srdis_pa20
1245 /* Disable Space Register Hashing for PCXS,PCXT,PCXT' */
1247 .word 0x141c1a00 /* mfdiag %dr0, %r28 */
1248 .word 0x141c1a00 /* must issue twice */
1249 depwi 0,18,1, %r28 /* Clear DHE (dcache hash enable) */
1250 depwi 0,20,1, %r28 /* Clear IHE (icache hash enable) */
1251 .word 0x141c1600 /* mtdiag %r28, %dr0 */
1252 .word 0x141c1600 /* must issue twice */
1257 /* Disable Space Register Hashing for PCXL */
1259 .word 0x141c0600 /* mfdiag %dr0, %r28 */
1260 depwi 0,28,2, %r28 /* Clear DHASH_EN & IHASH_EN */
1261 .word 0x141c0240 /* mtdiag %r28, %dr0 */
1266 /* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */
1268 .word 0x144008bc /* mfdiag %dr2, %r28 */
1269 depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */
1270 .word 0x145c1840 /* mtdiag %r28, %dr2 */
1274 /* Switch back to virtual mode */
1275 rsm PSW_SM_I, %r0 /* prep to load iia queue */
1283 rsm PSW_SM_Q, %r0 /* prep to load iia queue */
1284 mtctl %r0, %cr17 /* Clear IIASQ tail */
1285 mtctl %r0, %cr17 /* Clear IIASQ head */
1286 mtctl %r1, %cr18 /* IIAOQ head */
1288 mtctl %r1, %cr18 /* IIAOQ tail */
1289 load32 KERNEL_PSW, %r1
1299 ENDPROC(disable_sr_hashing_asm)