1 /* 32 and 64-bit millicode, original author Hewlett-Packard
2 adapted for gcc by Paul Bame <bame@debian.org>
3 and Alan Modra <alan@linuxcare.com.au>.
5 Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
7 This file is part of GCC and is released under the terms of
8 of the GNU General Public License as published by the Free Software
9 Foundation; either version 2, or (at your option) any later version.
10 See the file COPYING in the top-level GCC source directory for a copy
17 /* Hardware General Registers. */
51 /* Hardware Space Registers. */
61 /* Hardware Floating Point Registers. */
79 /* Hardware Control Registers. */
81 sar: .reg %cr11 /* Shift Amount Register */
83 /* Software Architecture General Registers. */
84 rp: .reg r2 /* return pointer */
86 mrp: .reg r2 /* millicode return pointer */
88 mrp: .reg r31 /* millicode return pointer */
90 ret0: .reg r28 /* return value */
91 ret1: .reg r29 /* return value (high part of double) */
92 sp: .reg r30 /* stack pointer */
93 dp: .reg r27 /* data pointer */
94 arg0: .reg r26 /* argument */
95 arg1: .reg r25 /* argument or high part of double argument */
96 arg2: .reg r24 /* argument */
97 arg3: .reg r23 /* argument or high part of double argument */
99 /* Software Architecture Space Registers. */
100 /* sr0 ; return link from BLE */
101 sret: .reg sr1 /* return value */
102 sarg: .reg sr1 /* argument */
103 /* sr4 ; PC SPACE tracker */
104 /* sr5 ; process private data */
106 /* Frame Offsets (millicode convention!) Used when calling other
107 millicode routines. Stack unwinding is dependent upon these
109 r31_slot: .equ -20 /* "current RP" slot */
110 sr0_slot: .equ -16 /* "static link" slot */
111 #if defined(CONFIG_64BIT)
112 mrp_slot: .equ -16 /* "current RP" slot */
113 psp_slot: .equ -8 /* "previous SP" slot */
115 mrp_slot: .equ -20 /* "current RP" slot (replacing "r31_slot") */
119 #define DEFINE(name,value)name: .EQU value
120 #define RDEFINE(name,value)name: .REG value
122 #define MILLI_BE(lbl) BE lbl(sr7,r0)
123 #define MILLI_BEN(lbl) BE,n lbl(sr7,r0)
124 #define MILLI_BLE(lbl) BLE lbl(sr7,r0)
125 #define MILLI_BLEN(lbl) BLE,n lbl(sr7,r0)
126 #define MILLIRETN BE,n 0(sr0,mrp)
127 #define MILLIRET BE 0(sr0,mrp)
128 #define MILLI_RETN BE,n 0(sr0,mrp)
129 #define MILLI_RET BE 0(sr0,mrp)
131 #define MILLI_BE(lbl) B lbl
132 #define MILLI_BEN(lbl) B,n lbl
133 #define MILLI_BLE(lbl) BL lbl,mrp
134 #define MILLI_BLEN(lbl) BL,n lbl,mrp
135 #define MILLIRETN BV,n 0(mrp)
136 #define MILLIRET BV 0(mrp)
137 #define MILLI_RETN BV,n 0(mrp)
138 #define MILLI_RET BV 0(mrp)
141 #define CAT(a,b) a##b
143 #define SUBSPA_MILLI .section .text
144 #define SUBSPA_MILLI_DIV .section .text.div,"ax",@progbits! .align 16
145 #define SUBSPA_MILLI_MUL .section .text.mul,"ax",@progbits! .align 16
147 #define SUBSPA_DATA .section .data
149 #define GLOBAL $global$
150 #define GSYM(sym) !sym:
151 #define LSYM(sym) !CAT(.L,sym:)
152 #define LREF(sym) CAT(.L,sym)
158 .export $$dyncall,millicode
162 bb,>=,n %r22,30,LREF(1) ; branch if not plabel address
163 depi 0,31,2,%r22 ; clear the two least significant bits
164 ldw 4(%r22),%r19 ; load new LTP value
165 ldw 0(%r22),%r22 ; load address of target
167 bv %r0(%r22) ; branch to the real target
168 stw %r2,-24(%r30) ; save return address into frame marker
174 /* ROUTINES: $$divI, $$divoI
176 Single precision divide for signed binary integers.
178 The quotient is truncated towards zero.
179 The sign of the quotient is the XOR of the signs of the dividend and
181 Divide by zero is trapped.
182 Divide of -2**31 by -1 is trapped for $$divoI but not for $$divI.
188 . sr0 == return space when called externally
195 OTHER REGISTERS AFFECTED:
199 . Causes a trap under the following conditions:
200 . divisor is zero (traps with ADDIT,= 0,25,0)
201 . dividend==-2**31 and divisor==-1 and routine is $$divoI
202 . (traps with ADDO 26,25,0)
203 . Changes memory at the following places:
208 . Suitable for internal or external millicode.
209 . Assumes the special millicode register conventions.
212 . Branchs to other millicode routines using BE
213 . $$div_# for # being 2,3,4,5,6,7,8,9,10,12,14,15
215 . For selected divisors, calls a divide by constant routine written by
216 . Karl Pettis. Eligible divisors are 1..15 excluding 11 and 13.
218 . The only overflow case is -2**31 divided by -1.
219 . Both routines return -2**31 but only $$divoI traps. */
222 RDEFINE(retreg,ret1) /* r29 */
226 .import $$divI_2,millicode
227 .import $$divI_3,millicode
228 .import $$divI_4,millicode
229 .import $$divI_5,millicode
230 .import $$divI_6,millicode
231 .import $$divI_7,millicode
232 .import $$divI_8,millicode
233 .import $$divI_9,millicode
234 .import $$divI_10,millicode
235 .import $$divI_12,millicode
236 .import $$divI_14,millicode
237 .import $$divI_15,millicode
238 .export $$divI,millicode
239 .export $$divoI,millicode
244 comib,=,n -1,arg1,LREF(negative1) /* when divisor == -1 */
246 ldo -1(arg1),temp /* is there at most one bit set ? */
247 and,<> arg1,temp,r0 /* if not, don't use power of 2 divide */
248 addi,> 0,arg1,r0 /* if divisor > 0, use power of 2 divide */
251 addi,>= 0,arg0,retreg /* if numerator is negative, add the */
252 add arg0,temp,retreg /* (denominaotr -1) to correct for shifts */
253 extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
254 extrs retreg,15,16,retreg /* retreg = retreg >> 16 */
255 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
256 ldi 0xcc,temp1 /* setup 0xcc in temp1 */
257 extru,= arg1,23,8,temp /* test denominator with 0xff00 */
258 extrs retreg,23,24,retreg /* retreg = retreg >> 8 */
259 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
260 ldi 0xaa,temp /* setup 0xaa in temp */
261 extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
262 extrs retreg,27,28,retreg /* retreg = retreg >> 4 */
263 and,= arg1,temp1,r0 /* test denominator with 0xcc */
264 extrs retreg,29,30,retreg /* retreg = retreg >> 2 */
265 and,= arg1,temp,r0 /* test denominator with 0xaa */
266 extrs retreg,30,31,retreg /* retreg = retreg >> 1 */
269 addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power of 2 */
270 b,n LREF(regular_seq)
271 sub r0,arg1,temp /* make denominator positive */
272 comb,=,n arg1,temp,LREF(regular_seq) /* test against 0x80000000 and 0 */
273 ldo -1(temp),retreg /* is there at most one bit set ? */
274 and,= temp,retreg,r0 /* if so, the denominator is power of 2 */
275 b,n LREF(regular_seq)
276 sub r0,arg0,retreg /* negate numerator */
277 comb,=,n arg0,retreg,LREF(regular_seq) /* test against 0x80000000 */
278 copy retreg,arg0 /* set up arg0, arg1 and temp */
279 copy temp,arg1 /* before branching to pow2 */
283 comib,>>=,n 15,arg1,LREF(small_divisor)
284 add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
286 subi 0,retreg,retreg /* make it positive */
287 sub 0,arg1,temp /* clear carry, */
288 /* negate the divisor */
289 ds 0,temp,0 /* set V-bit to the comple- */
290 /* ment of the divisor sign */
291 add retreg,retreg,retreg /* shift msb bit into carry */
292 ds r0,arg1,temp /* 1st divide step, if no carry */
293 addc retreg,retreg,retreg /* shift retreg with/into carry */
294 ds temp,arg1,temp /* 2nd divide step */
295 addc retreg,retreg,retreg /* shift retreg with/into carry */
296 ds temp,arg1,temp /* 3rd divide step */
297 addc retreg,retreg,retreg /* shift retreg with/into carry */
298 ds temp,arg1,temp /* 4th divide step */
299 addc retreg,retreg,retreg /* shift retreg with/into carry */
300 ds temp,arg1,temp /* 5th divide step */
301 addc retreg,retreg,retreg /* shift retreg with/into carry */
302 ds temp,arg1,temp /* 6th divide step */
303 addc retreg,retreg,retreg /* shift retreg with/into carry */
304 ds temp,arg1,temp /* 7th divide step */
305 addc retreg,retreg,retreg /* shift retreg with/into carry */
306 ds temp,arg1,temp /* 8th divide step */
307 addc retreg,retreg,retreg /* shift retreg with/into carry */
308 ds temp,arg1,temp /* 9th divide step */
309 addc retreg,retreg,retreg /* shift retreg with/into carry */
310 ds temp,arg1,temp /* 10th divide step */
311 addc retreg,retreg,retreg /* shift retreg with/into carry */
312 ds temp,arg1,temp /* 11th divide step */
313 addc retreg,retreg,retreg /* shift retreg with/into carry */
314 ds temp,arg1,temp /* 12th divide step */
315 addc retreg,retreg,retreg /* shift retreg with/into carry */
316 ds temp,arg1,temp /* 13th divide step */
317 addc retreg,retreg,retreg /* shift retreg with/into carry */
318 ds temp,arg1,temp /* 14th divide step */
319 addc retreg,retreg,retreg /* shift retreg with/into carry */
320 ds temp,arg1,temp /* 15th divide step */
321 addc retreg,retreg,retreg /* shift retreg with/into carry */
322 ds temp,arg1,temp /* 16th divide step */
323 addc retreg,retreg,retreg /* shift retreg with/into carry */
324 ds temp,arg1,temp /* 17th divide step */
325 addc retreg,retreg,retreg /* shift retreg with/into carry */
326 ds temp,arg1,temp /* 18th divide step */
327 addc retreg,retreg,retreg /* shift retreg with/into carry */
328 ds temp,arg1,temp /* 19th divide step */
329 addc retreg,retreg,retreg /* shift retreg with/into carry */
330 ds temp,arg1,temp /* 20th divide step */
331 addc retreg,retreg,retreg /* shift retreg with/into carry */
332 ds temp,arg1,temp /* 21st divide step */
333 addc retreg,retreg,retreg /* shift retreg with/into carry */
334 ds temp,arg1,temp /* 22nd divide step */
335 addc retreg,retreg,retreg /* shift retreg with/into carry */
336 ds temp,arg1,temp /* 23rd divide step */
337 addc retreg,retreg,retreg /* shift retreg with/into carry */
338 ds temp,arg1,temp /* 24th divide step */
339 addc retreg,retreg,retreg /* shift retreg with/into carry */
340 ds temp,arg1,temp /* 25th divide step */
341 addc retreg,retreg,retreg /* shift retreg with/into carry */
342 ds temp,arg1,temp /* 26th divide step */
343 addc retreg,retreg,retreg /* shift retreg with/into carry */
344 ds temp,arg1,temp /* 27th divide step */
345 addc retreg,retreg,retreg /* shift retreg with/into carry */
346 ds temp,arg1,temp /* 28th divide step */
347 addc retreg,retreg,retreg /* shift retreg with/into carry */
348 ds temp,arg1,temp /* 29th divide step */
349 addc retreg,retreg,retreg /* shift retreg with/into carry */
350 ds temp,arg1,temp /* 30th divide step */
351 addc retreg,retreg,retreg /* shift retreg with/into carry */
352 ds temp,arg1,temp /* 31st divide step */
353 addc retreg,retreg,retreg /* shift retreg with/into carry */
354 ds temp,arg1,temp /* 32nd divide step, */
355 addc retreg,retreg,retreg /* shift last retreg bit into retreg */
356 xor,>= arg0,arg1,0 /* get correct sign of quotient */
357 sub 0,retreg,retreg /* based on operand signs */
363 #if defined(CONFIG_64BIT)
364 /* Clear the upper 32 bits of the arg1 register. We are working with */
365 /* small divisors (and 32-bit integers) We must not be mislead */
366 /* by "1" bits left in the upper 32 bits. */
371 /* table for divisor == 0,1, ... ,15 */
372 addit,= 0,arg1,r0 /* trap if divisor == 0 */
374 MILLIRET /* divisor == 1 */
376 MILLI_BEN($$divI_2) /* divisor == 2 */
378 MILLI_BEN($$divI_3) /* divisor == 3 */
380 MILLI_BEN($$divI_4) /* divisor == 4 */
382 MILLI_BEN($$divI_5) /* divisor == 5 */
384 MILLI_BEN($$divI_6) /* divisor == 6 */
386 MILLI_BEN($$divI_7) /* divisor == 7 */
388 MILLI_BEN($$divI_8) /* divisor == 8 */
390 MILLI_BEN($$divI_9) /* divisor == 9 */
392 MILLI_BEN($$divI_10) /* divisor == 10 */
394 b LREF(normal) /* divisor == 11 */
396 MILLI_BEN($$divI_12) /* divisor == 12 */
398 b LREF(normal) /* divisor == 13 */
400 MILLI_BEN($$divI_14) /* divisor == 14 */
402 MILLI_BEN($$divI_15) /* divisor == 15 */
406 sub 0,arg0,retreg /* result is negation of dividend */
408 addo arg0,arg1,r0 /* trap iff dividend==0x80000000 && divisor==-1 */
417 . Single precision divide for unsigned integers.
419 . Quotient is truncated towards zero.
420 . Traps on divide by zero.
426 . sr0 == return space when called externally
433 OTHER REGISTERS AFFECTED:
437 . Causes a trap under the following conditions:
439 . Changes memory at the following places:
444 . Does not create a stack frame.
445 . Suitable for internal or external millicode.
446 . Assumes the special millicode register conventions.
449 . Branchs to other millicode routines using BE:
450 . $$divU_# for 3,5,6,7,9,10,12,14,15
452 . For selected small divisors calls the special divide by constant
453 . routines written by Karl Pettis. These are: 3,5,6,7,9,10,12,14,15. */
456 RDEFINE(retreg,ret1) /* r29 */
460 .export $$divU,millicode
461 .import $$divU_3,millicode
462 .import $$divU_5,millicode
463 .import $$divU_6,millicode
464 .import $$divU_7,millicode
465 .import $$divU_9,millicode
466 .import $$divU_10,millicode
467 .import $$divU_12,millicode
468 .import $$divU_14,millicode
469 .import $$divU_15,millicode
474 /* The subtract is not nullified since it does no harm and can be used
475 by the two cases that branch back to "normal". */
476 ldo -1(arg1),temp /* is there at most one bit set ? */
477 and,= arg1,temp,r0 /* if so, denominator is power of 2 */
479 addit,= 0,arg1,0 /* trap for zero dvr */
481 extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
482 extru retreg,15,16,retreg /* retreg = retreg >> 16 */
483 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
484 ldi 0xcc,temp1 /* setup 0xcc in temp1 */
485 extru,= arg1,23,8,temp /* test denominator with 0xff00 */
486 extru retreg,23,24,retreg /* retreg = retreg >> 8 */
487 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
488 ldi 0xaa,temp /* setup 0xaa in temp */
489 extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
490 extru retreg,27,28,retreg /* retreg = retreg >> 4 */
491 and,= arg1,temp1,r0 /* test denominator with 0xcc */
492 extru retreg,29,30,retreg /* retreg = retreg >> 2 */
493 and,= arg1,temp,r0 /* test denominator with 0xaa */
494 extru retreg,30,31,retreg /* retreg = retreg >> 1 */
498 comib,>= 15,arg1,LREF(special_divisor)
499 subi 0,arg1,temp /* clear carry, negate the divisor */
500 ds r0,temp,r0 /* set V-bit to 1 */
502 add arg0,arg0,retreg /* shift msb bit into carry */
503 ds r0,arg1,temp /* 1st divide step, if no carry */
504 addc retreg,retreg,retreg /* shift retreg with/into carry */
505 ds temp,arg1,temp /* 2nd divide step */
506 addc retreg,retreg,retreg /* shift retreg with/into carry */
507 ds temp,arg1,temp /* 3rd divide step */
508 addc retreg,retreg,retreg /* shift retreg with/into carry */
509 ds temp,arg1,temp /* 4th divide step */
510 addc retreg,retreg,retreg /* shift retreg with/into carry */
511 ds temp,arg1,temp /* 5th divide step */
512 addc retreg,retreg,retreg /* shift retreg with/into carry */
513 ds temp,arg1,temp /* 6th divide step */
514 addc retreg,retreg,retreg /* shift retreg with/into carry */
515 ds temp,arg1,temp /* 7th divide step */
516 addc retreg,retreg,retreg /* shift retreg with/into carry */
517 ds temp,arg1,temp /* 8th divide step */
518 addc retreg,retreg,retreg /* shift retreg with/into carry */
519 ds temp,arg1,temp /* 9th divide step */
520 addc retreg,retreg,retreg /* shift retreg with/into carry */
521 ds temp,arg1,temp /* 10th divide step */
522 addc retreg,retreg,retreg /* shift retreg with/into carry */
523 ds temp,arg1,temp /* 11th divide step */
524 addc retreg,retreg,retreg /* shift retreg with/into carry */
525 ds temp,arg1,temp /* 12th divide step */
526 addc retreg,retreg,retreg /* shift retreg with/into carry */
527 ds temp,arg1,temp /* 13th divide step */
528 addc retreg,retreg,retreg /* shift retreg with/into carry */
529 ds temp,arg1,temp /* 14th divide step */
530 addc retreg,retreg,retreg /* shift retreg with/into carry */
531 ds temp,arg1,temp /* 15th divide step */
532 addc retreg,retreg,retreg /* shift retreg with/into carry */
533 ds temp,arg1,temp /* 16th divide step */
534 addc retreg,retreg,retreg /* shift retreg with/into carry */
535 ds temp,arg1,temp /* 17th divide step */
536 addc retreg,retreg,retreg /* shift retreg with/into carry */
537 ds temp,arg1,temp /* 18th divide step */
538 addc retreg,retreg,retreg /* shift retreg with/into carry */
539 ds temp,arg1,temp /* 19th divide step */
540 addc retreg,retreg,retreg /* shift retreg with/into carry */
541 ds temp,arg1,temp /* 20th divide step */
542 addc retreg,retreg,retreg /* shift retreg with/into carry */
543 ds temp,arg1,temp /* 21st divide step */
544 addc retreg,retreg,retreg /* shift retreg with/into carry */
545 ds temp,arg1,temp /* 22nd divide step */
546 addc retreg,retreg,retreg /* shift retreg with/into carry */
547 ds temp,arg1,temp /* 23rd divide step */
548 addc retreg,retreg,retreg /* shift retreg with/into carry */
549 ds temp,arg1,temp /* 24th divide step */
550 addc retreg,retreg,retreg /* shift retreg with/into carry */
551 ds temp,arg1,temp /* 25th divide step */
552 addc retreg,retreg,retreg /* shift retreg with/into carry */
553 ds temp,arg1,temp /* 26th divide step */
554 addc retreg,retreg,retreg /* shift retreg with/into carry */
555 ds temp,arg1,temp /* 27th divide step */
556 addc retreg,retreg,retreg /* shift retreg with/into carry */
557 ds temp,arg1,temp /* 28th divide step */
558 addc retreg,retreg,retreg /* shift retreg with/into carry */
559 ds temp,arg1,temp /* 29th divide step */
560 addc retreg,retreg,retreg /* shift retreg with/into carry */
561 ds temp,arg1,temp /* 30th divide step */
562 addc retreg,retreg,retreg /* shift retreg with/into carry */
563 ds temp,arg1,temp /* 31st divide step */
564 addc retreg,retreg,retreg /* shift retreg with/into carry */
565 ds temp,arg1,temp /* 32nd divide step, */
567 addc retreg,retreg,retreg /* shift last retreg bit into retreg */
569 /* Handle the cases where divisor is a small constant or has high bit on. */
570 LSYM(special_divisor)
572 /* comib,>,n 0,arg1,LREF(big_divisor) ; nullify previous instruction */
574 /* Pratap 8/13/90. The 815 Stirling chip set has a bug that prevents us from
575 generating such a blr, comib sequence. A problem in nullification. So I
576 rewrote this code. */
578 #if defined(CONFIG_64BIT)
579 /* Clear the upper 32 bits of the arg1 register. We are working with
580 small divisors (and 32-bit unsigned integers) We must not be mislead
581 by "1" bits left in the upper 32 bits. */
584 comib,> 0,arg1,LREF(big_divisor)
589 LSYM(zero_divisor) /* this label is here to provide external visibility */
590 addit,= 0,arg1,0 /* trap for zero dvr */
592 MILLIRET /* divisor == 1 */
594 MILLIRET /* divisor == 2 */
595 extru arg0,30,31,retreg
596 MILLI_BEN($$divU_3) /* divisor == 3 */
598 MILLIRET /* divisor == 4 */
599 extru arg0,29,30,retreg
600 MILLI_BEN($$divU_5) /* divisor == 5 */
602 MILLI_BEN($$divU_6) /* divisor == 6 */
604 MILLI_BEN($$divU_7) /* divisor == 7 */
606 MILLIRET /* divisor == 8 */
607 extru arg0,28,29,retreg
608 MILLI_BEN($$divU_9) /* divisor == 9 */
610 MILLI_BEN($$divU_10) /* divisor == 10 */
612 b LREF(normal) /* divisor == 11 */
613 ds r0,temp,r0 /* set V-bit to 1 */
614 MILLI_BEN($$divU_12) /* divisor == 12 */
616 b LREF(normal) /* divisor == 13 */
617 ds r0,temp,r0 /* set V-bit to 1 */
618 MILLI_BEN($$divU_14) /* divisor == 14 */
620 MILLI_BEN($$divU_15) /* divisor == 15 */
623 /* Handle the case where the high bit is on in the divisor.
624 Compute: if( dividend>=divisor) quotient=1; else quotient=0;
625 Note: dividend>==divisor iff dividend-divisor does not borrow
626 and not borrow iff carry. */
640 . $$remI returns the remainder of the division of two signed 32-bit
641 . integers. The sign of the remainder is the same as the sign of
649 . sr0 == return space when called externally
656 OTHER REGISTERS AFFECTED:
660 . Causes a trap under the following conditions: DIVIDE BY ZERO
661 . Changes memory at the following places: NONE
665 . Does not create a stack frame
666 . Is usable for internal or external microcode
669 . Calls other millicode routines via mrp: NONE
670 . Calls other millicode routines: NONE */
682 .export $$remI,MILLICODE
683 .export $$remoI,MILLICODE
684 ldo -1(arg1),tmp /* is there at most one bit set ? */
685 and,<> arg1,tmp,r0 /* if not, don't use power of 2 */
686 addi,> 0,arg1,r0 /* if denominator > 0, use power */
690 comb,>,n 0,arg0,LREF(neg_num) /* is numerator < 0 ? */
691 and arg0,tmp,retreg /* get the result */
694 subi 0,arg0,arg0 /* negate numerator */
695 and arg0,tmp,retreg /* get the result */
696 subi 0,retreg,retreg /* negate result */
699 addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power */
701 b,n LREF(regular_seq)
702 sub r0,arg1,tmp /* make denominator positive */
703 comb,=,n arg1,tmp,LREF(regular_seq) /* test against 0x80000000 and 0 */
704 ldo -1(tmp),retreg /* is there at most one bit set ? */
705 and,= tmp,retreg,r0 /* if not, go to regular_seq */
706 b,n LREF(regular_seq)
707 comb,>,n 0,arg0,LREF(neg_num_2) /* if arg0 < 0, negate it */
708 and arg0,retreg,retreg
711 subi 0,arg0,tmp /* test against 0x80000000 */
712 and tmp,retreg,retreg
716 addit,= 0,arg1,0 /* trap if div by zero */
717 add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
718 sub 0,retreg,retreg /* make it positive */
719 sub 0,arg1, tmp /* clear carry, */
720 /* negate the divisor */
721 ds 0, tmp,0 /* set V-bit to the comple- */
722 /* ment of the divisor sign */
723 or 0,0, tmp /* clear tmp */
724 add retreg,retreg,retreg /* shift msb bit into carry */
725 ds tmp,arg1, tmp /* 1st divide step, if no carry */
726 /* out, msb of quotient = 0 */
727 addc retreg,retreg,retreg /* shift retreg with/into carry */
729 ds tmp,arg1, tmp /* 2nd divide step */
730 addc retreg,retreg,retreg /* shift retreg with/into carry */
731 ds tmp,arg1, tmp /* 3rd divide step */
732 addc retreg,retreg,retreg /* shift retreg with/into carry */
733 ds tmp,arg1, tmp /* 4th divide step */
734 addc retreg,retreg,retreg /* shift retreg with/into carry */
735 ds tmp,arg1, tmp /* 5th divide step */
736 addc retreg,retreg,retreg /* shift retreg with/into carry */
737 ds tmp,arg1, tmp /* 6th divide step */
738 addc retreg,retreg,retreg /* shift retreg with/into carry */
739 ds tmp,arg1, tmp /* 7th divide step */
740 addc retreg,retreg,retreg /* shift retreg with/into carry */
741 ds tmp,arg1, tmp /* 8th divide step */
742 addc retreg,retreg,retreg /* shift retreg with/into carry */
743 ds tmp,arg1, tmp /* 9th divide step */
744 addc retreg,retreg,retreg /* shift retreg with/into carry */
745 ds tmp,arg1, tmp /* 10th divide step */
746 addc retreg,retreg,retreg /* shift retreg with/into carry */
747 ds tmp,arg1, tmp /* 11th divide step */
748 addc retreg,retreg,retreg /* shift retreg with/into carry */
749 ds tmp,arg1, tmp /* 12th divide step */
750 addc retreg,retreg,retreg /* shift retreg with/into carry */
751 ds tmp,arg1, tmp /* 13th divide step */
752 addc retreg,retreg,retreg /* shift retreg with/into carry */
753 ds tmp,arg1, tmp /* 14th divide step */
754 addc retreg,retreg,retreg /* shift retreg with/into carry */
755 ds tmp,arg1, tmp /* 15th divide step */
756 addc retreg,retreg,retreg /* shift retreg with/into carry */
757 ds tmp,arg1, tmp /* 16th divide step */
758 addc retreg,retreg,retreg /* shift retreg with/into carry */
759 ds tmp,arg1, tmp /* 17th divide step */
760 addc retreg,retreg,retreg /* shift retreg with/into carry */
761 ds tmp,arg1, tmp /* 18th divide step */
762 addc retreg,retreg,retreg /* shift retreg with/into carry */
763 ds tmp,arg1, tmp /* 19th divide step */
764 addc retreg,retreg,retreg /* shift retreg with/into carry */
765 ds tmp,arg1, tmp /* 20th divide step */
766 addc retreg,retreg,retreg /* shift retreg with/into carry */
767 ds tmp,arg1, tmp /* 21st divide step */
768 addc retreg,retreg,retreg /* shift retreg with/into carry */
769 ds tmp,arg1, tmp /* 22nd divide step */
770 addc retreg,retreg,retreg /* shift retreg with/into carry */
771 ds tmp,arg1, tmp /* 23rd divide step */
772 addc retreg,retreg,retreg /* shift retreg with/into carry */
773 ds tmp,arg1, tmp /* 24th divide step */
774 addc retreg,retreg,retreg /* shift retreg with/into carry */
775 ds tmp,arg1, tmp /* 25th divide step */
776 addc retreg,retreg,retreg /* shift retreg with/into carry */
777 ds tmp,arg1, tmp /* 26th divide step */
778 addc retreg,retreg,retreg /* shift retreg with/into carry */
779 ds tmp,arg1, tmp /* 27th divide step */
780 addc retreg,retreg,retreg /* shift retreg with/into carry */
781 ds tmp,arg1, tmp /* 28th divide step */
782 addc retreg,retreg,retreg /* shift retreg with/into carry */
783 ds tmp,arg1, tmp /* 29th divide step */
784 addc retreg,retreg,retreg /* shift retreg with/into carry */
785 ds tmp,arg1, tmp /* 30th divide step */
786 addc retreg,retreg,retreg /* shift retreg with/into carry */
787 ds tmp,arg1, tmp /* 31st divide step */
788 addc retreg,retreg,retreg /* shift retreg with/into carry */
789 ds tmp,arg1, tmp /* 32nd divide step, */
790 addc retreg,retreg,retreg /* shift last bit into retreg */
791 movb,>=,n tmp,retreg,LREF(finish) /* branch if pos. tmp */
792 add,< arg1,0,0 /* if arg1 > 0, add arg1 */
793 add,tr tmp,arg1,retreg /* for correcting remainder tmp */
794 sub tmp,arg1,retreg /* else add absolute value arg1 */
796 add,>= arg0,0,0 /* set sign of remainder */
797 sub 0,retreg,retreg /* to sign of dividend */
810 . Single precision divide for remainder with unsigned binary integers.
812 . The remainder must be dividend-(dividend/divisor)*divisor.
813 . Divide by zero is trapped.
819 . sr0 == return space when called externally
826 OTHER REGISTERS AFFECTED:
830 . Causes a trap under the following conditions: DIVIDE BY ZERO
831 . Changes memory at the following places: NONE
835 . Does not create a stack frame.
836 . Suitable for internal or external millicode.
837 . Assumes the special millicode register conventions.
840 . Calls other millicode routines using mrp: NONE
841 . Calls other millicode routines: NONE */
845 RDEFINE(rmndr,ret1) /* r29 */
848 .export $$remU,millicode
853 ldo -1(arg1),temp /* is there at most one bit set ? */
854 and,= arg1,temp,r0 /* if not, don't use power of 2 */
856 addit,= 0,arg1,r0 /* trap on div by zero */
857 and arg0,temp,rmndr /* get the result for power of 2 */
860 comib,>=,n 0,arg1,LREF(special_case)
861 subi 0,arg1,rmndr /* clear carry, negate the divisor */
862 ds r0,rmndr,r0 /* set V-bit to 1 */
863 add arg0,arg0,temp /* shift msb bit into carry */
864 ds r0,arg1,rmndr /* 1st divide step, if no carry */
865 addc temp,temp,temp /* shift temp with/into carry */
866 ds rmndr,arg1,rmndr /* 2nd divide step */
867 addc temp,temp,temp /* shift temp with/into carry */
868 ds rmndr,arg1,rmndr /* 3rd divide step */
869 addc temp,temp,temp /* shift temp with/into carry */
870 ds rmndr,arg1,rmndr /* 4th divide step */
871 addc temp,temp,temp /* shift temp with/into carry */
872 ds rmndr,arg1,rmndr /* 5th divide step */
873 addc temp,temp,temp /* shift temp with/into carry */
874 ds rmndr,arg1,rmndr /* 6th divide step */
875 addc temp,temp,temp /* shift temp with/into carry */
876 ds rmndr,arg1,rmndr /* 7th divide step */
877 addc temp,temp,temp /* shift temp with/into carry */
878 ds rmndr,arg1,rmndr /* 8th divide step */
879 addc temp,temp,temp /* shift temp with/into carry */
880 ds rmndr,arg1,rmndr /* 9th divide step */
881 addc temp,temp,temp /* shift temp with/into carry */
882 ds rmndr,arg1,rmndr /* 10th divide step */
883 addc temp,temp,temp /* shift temp with/into carry */
884 ds rmndr,arg1,rmndr /* 11th divide step */
885 addc temp,temp,temp /* shift temp with/into carry */
886 ds rmndr,arg1,rmndr /* 12th divide step */
887 addc temp,temp,temp /* shift temp with/into carry */
888 ds rmndr,arg1,rmndr /* 13th divide step */
889 addc temp,temp,temp /* shift temp with/into carry */
890 ds rmndr,arg1,rmndr /* 14th divide step */
891 addc temp,temp,temp /* shift temp with/into carry */
892 ds rmndr,arg1,rmndr /* 15th divide step */
893 addc temp,temp,temp /* shift temp with/into carry */
894 ds rmndr,arg1,rmndr /* 16th divide step */
895 addc temp,temp,temp /* shift temp with/into carry */
896 ds rmndr,arg1,rmndr /* 17th divide step */
897 addc temp,temp,temp /* shift temp with/into carry */
898 ds rmndr,arg1,rmndr /* 18th divide step */
899 addc temp,temp,temp /* shift temp with/into carry */
900 ds rmndr,arg1,rmndr /* 19th divide step */
901 addc temp,temp,temp /* shift temp with/into carry */
902 ds rmndr,arg1,rmndr /* 20th divide step */
903 addc temp,temp,temp /* shift temp with/into carry */
904 ds rmndr,arg1,rmndr /* 21st divide step */
905 addc temp,temp,temp /* shift temp with/into carry */
906 ds rmndr,arg1,rmndr /* 22nd divide step */
907 addc temp,temp,temp /* shift temp with/into carry */
908 ds rmndr,arg1,rmndr /* 23rd divide step */
909 addc temp,temp,temp /* shift temp with/into carry */
910 ds rmndr,arg1,rmndr /* 24th divide step */
911 addc temp,temp,temp /* shift temp with/into carry */
912 ds rmndr,arg1,rmndr /* 25th divide step */
913 addc temp,temp,temp /* shift temp with/into carry */
914 ds rmndr,arg1,rmndr /* 26th divide step */
915 addc temp,temp,temp /* shift temp with/into carry */
916 ds rmndr,arg1,rmndr /* 27th divide step */
917 addc temp,temp,temp /* shift temp with/into carry */
918 ds rmndr,arg1,rmndr /* 28th divide step */
919 addc temp,temp,temp /* shift temp with/into carry */
920 ds rmndr,arg1,rmndr /* 29th divide step */
921 addc temp,temp,temp /* shift temp with/into carry */
922 ds rmndr,arg1,rmndr /* 30th divide step */
923 addc temp,temp,temp /* shift temp with/into carry */
924 ds rmndr,arg1,rmndr /* 31st divide step */
925 addc temp,temp,temp /* shift temp with/into carry */
926 ds rmndr,arg1,rmndr /* 32nd divide step, */
927 comiclr,<= 0,rmndr,r0
928 add rmndr,arg1,rmndr /* correction */
932 /* Putting >= on the last DS and deleting COMICLR does not work! */
934 sub,>>= arg0,arg1,rmndr
952 . $$divI_10 $$divU_10
954 . $$divI_12 $$divU_12
956 . $$divI_14 $$divU_14
957 . $$divI_15 $$divU_15
959 . $$divI_17 $$divU_17
961 . Divide by selected constants for single precision binary integers.
966 . sr0 == return space when called externally
973 OTHER REGISTERS AFFECTED:
977 . Causes a trap under the following conditions: NONE
978 . Changes memory at the following places: NONE
982 . Does not create a stack frame.
983 . Suitable for internal or external millicode.
984 . Assumes the special millicode register conventions.
987 . Calls other millicode routines using mrp: NONE
988 . Calls other millicode routines: NONE */
991 /* TRUNCATED DIVISION BY SMALL INTEGERS
993 We are interested in q(x) = floor(x/y), where x >= 0 and y > 0
996 Let a = floor(z/y), for some choice of z. Note that z will be
997 chosen so that division by z is cheap.
999 Let r be the remainder(z/y). In other words, r = z - ay.
1001 Now, our method is to choose a value for b such that
1003 q'(x) = floor((ax+b)/z)
1005 is equal to q(x) over as large a range of x as possible. If the
1006 two are equal over a sufficiently large range, and if it is easy to
1007 form the product (ax), and it is easy to divide by z, then we can
1008 perform the division much faster than the general division algorithm.
1010 So, we want the following to be true:
1012 . For x in the following range:
1018 . k <= (ax+b)/z < (k+1)
1020 We want to determine b such that this is true for all k in the
1021 range {0..K} for some maximum K.
1023 Since (ax+b) is an increasing function of x, we can take each
1024 bound separately to determine the "best" value for b.
1026 (ax+b)/z < (k+1) implies
1028 (a((k+1)y-1)+b < (k+1)z implies
1030 b < a + (k+1)(z-ay) implies
1034 This needs to be true for all k in the range {0..K}. In
1035 particular, it is true for k = 0 and this leads to a maximum
1036 acceptable value for b.
1038 b < a+r or b <= a+r-1
1040 Taking the other bound, we have
1042 k <= (ax+b)/z implies
1044 k <= (aky+b)/z implies
1046 k(z-ay) <= b implies
1050 Clearly, the largest range for k will be achieved by maximizing b,
1051 when r is not zero. When r is zero, then the simplest choice for b
1052 is 0. When r is not 0, set
1056 Now, by construction, q'(x) = floor((ax+b)/z) = q(x) = floor(x/y)
1057 for all x in the range:
1061 We need to determine what K is. Of our two bounds,
1063 . b < a+(k+1)r is satisfied for all k >= 0, by construction.
1069 This is always true if r = 0. If r is not 0 (the usual case), then
1070 K = floor((a+r-1)/r), is the maximum value for k.
1072 Therefore, the formula q'(x) = floor((ax+b)/z) yields the correct
1073 answer for q(x) = floor(x/y) when x is in the range
1075 (0,(K+1)y-1) K = floor((a+r-1)/r)
1077 To be most useful, we want (K+1)y-1 = (max x) >= 2**32-1 so that
1078 the formula for q'(x) yields the correct value of q(x) for all x
1079 representable by a single word in HPPA.
1081 We are also constrained in that computing the product (ax), adding
1082 b, and dividing by z must all be done quickly, otherwise we will be
1083 better off going through the general algorithm using the DS
1084 instruction, which uses approximately 70 cycles.
1086 For each y, there is a choice of z which satisfies the constraints
1087 for (K+1)y >= 2**32. We may not, however, be able to satisfy the
1088 timing constraints for arbitrary y. It seems that z being equal to
1089 a power of 2 or a power of 2 minus 1 is as good as we can do, since
1090 it minimizes the time to do division by z. We want the choice of z
1091 to also result in a value for (a) that minimizes the computation of
1092 the product (ax). This is best achieved if (a) has a regular bit
1093 pattern (so the multiplication can be done with shifts and adds).
1094 The value of (a) also needs to be less than 2**32 so the product is
1095 always guaranteed to fit in 2 words.
1097 In actual practice, the following should be done:
1099 1) For negative x, you should take the absolute value and remember
1100 . the fact so that the result can be negated. This obviously does
1101 . not apply in the unsigned case.
1102 2) For even y, you should factor out the power of 2 that divides y
1103 . and divide x by it. You can then proceed by dividing by the
1106 Here is a table of some odd values of y, and corresponding choices
1107 for z which are "good".
1109 y z r a (hex) max x (hex)
1111 3 2**32 1 55555555 100000001
1112 5 2**32 1 33333333 100000003
1113 7 2**24-1 0 249249 (infinite)
1114 9 2**24-1 0 1c71c7 (infinite)
1115 11 2**20-1 0 1745d (infinite)
1116 13 2**24-1 0 13b13b (infinite)
1117 15 2**32 1 11111111 10000000d
1118 17 2**32 1 f0f0f0f 10000000f
1120 If r is 1, then b = a+r-1 = a. This simplifies the computation
1121 of (ax+b), since you can compute (x+1)(a) instead. If r is 0,
1122 then b = 0 is ok to use which simplifies (ax+b).
1124 The bit patterns for 55555555, 33333333, and 11111111 are obviously
1125 very regular. The bit patterns for the other values of a above are:
1129 7 249249 001001001001001001001001 << regular >>
1130 9 1c71c7 000111000111000111000111 << regular >>
1131 11 1745d 000000010111010001011101 << irregular >>
1132 13 13b13b 000100111011000100111011 << irregular >>
1134 The bit patterns for (a) corresponding to (y) of 11 and 13 may be
1135 too irregular to warrant using this method.
1137 When z is a power of 2 minus 1, then the division by z is slightly
1138 more complicated, involving an iterative solution.
1140 The code presented here solves division by 1 through 17, except for
1141 11 and 13. There are algorithms for both signed and unsigned
1146 divisor positive negative unsigned
1161 Now, the algorithm for 7, 9, and 14 is an iterative one. That is,
1162 a loop body is executed until the tentative quotient is 0. The
1163 number of times the loop body is executed varies depending on the
1164 dividend, but is never more than two times. If the dividend is
1165 less than the divisor, then the loop body is not executed at all.
1166 Each iteration adds 4 cycles to the timings.
1168 divisor positive negative unsigned
1170 . 7 19+4n 20+4n 20+4n n = number of iterations
1171 . 9 21+4n 22+4n 21+4n
1172 . 14 21+4n 22+4n 20+4n
1174 To give an idea of how the number of iterations varies, here is a
1175 table of dividend versus number of iterations when dividing by 7.
1177 smallest largest required
1178 dividend dividend iterations
1182 0x1000006 0xffffffff 2
1184 There is some overlap in the range of numbers requiring 1 and 2
1188 RDEFINE(x2,arg0) /* r26 */
1189 RDEFINE(t1,arg1) /* r25 */
1190 RDEFINE(x1,ret1) /* r29 */
1198 /* NONE of these routines require a stack frame
1199 ALL of these routines are unwindable from millicode */
1201 GSYM($$divide_by_constant)
1202 .export $$divide_by_constant,millicode
1203 /* Provides a "nice" label for the code covered by the unwind descriptor
1204 for things like gprof. */
1206 /* DIVISION BY 2 (shift by 1) */
1208 .export $$divI_2,millicode
1212 extrs arg0,30,31,ret1
1215 /* DIVISION BY 4 (shift by 2) */
1217 .export $$divI_4,millicode
1221 extrs arg0,29,30,ret1
1224 /* DIVISION BY 8 (shift by 3) */
1226 .export $$divI_8,millicode
1230 extrs arg0,28,29,ret1
1232 /* DIVISION BY 16 (shift by 4) */
1234 .export $$divI_16,millicode
1238 extrs arg0,27,28,ret1
1240 /****************************************************************************
1242 * DIVISION BY DIVISORS OF FFFFFFFF, and powers of 2 times these
1244 * includes 3,5,15,17 and also 6,10,12
1246 ****************************************************************************/
1248 /* DIVISION BY 3 (use z = 2**32; a = 55555555) */
1251 .export $$divI_3,millicode
1252 comb,<,N x2,0,LREF(neg3)
1254 addi 1,x2,x2 /* this cannot overflow */
1255 extru x2,1,2,x1 /* multiply by 5 to get started */
1261 subi 1,x2,x2 /* this cannot overflow */
1262 extru x2,1,2,x1 /* multiply by 5 to get started */
1268 .export $$divU_3,millicode
1269 addi 1,x2,x2 /* this CAN overflow */
1271 shd x1,x2,30,t1 /* multiply by 5 to get started */
1276 /* DIVISION BY 5 (use z = 2**32; a = 33333333) */
1279 .export $$divI_5,millicode
1280 comb,<,N x2,0,LREF(neg5)
1282 addi 3,x2,t1 /* this cannot overflow */
1283 sh1add x2,t1,x2 /* multiply by 3 to get started */
1288 sub 0,x2,x2 /* negate x2 */
1289 addi 1,x2,x2 /* this cannot overflow */
1290 shd 0,x2,31,x1 /* get top bit (can be 1) */
1291 sh1add x2,x2,x2 /* multiply by 3 to get started */
1296 .export $$divU_5,millicode
1297 addi 1,x2,x2 /* this CAN overflow */
1299 shd x1,x2,31,t1 /* multiply by 3 to get started */
1304 /* DIVISION BY 6 (shift to divide by 2 then divide by 3) */
1306 .export $$divI_6,millicode
1307 comb,<,N x2,0,LREF(neg6)
1308 extru x2,30,31,x2 /* divide by 2 */
1309 addi 5,x2,t1 /* compute 5*(x2+1) = 5*x2+5 */
1310 sh2add x2,t1,x2 /* multiply by 5 to get started */
1315 subi 2,x2,x2 /* negate, divide by 2, and add 1 */
1316 /* negation and adding 1 are done */
1317 /* at the same time by the SUBI */
1320 sh2add x2,x2,x2 /* multiply by 5 to get started */
1325 .export $$divU_6,millicode
1326 extru x2,30,31,x2 /* divide by 2 */
1327 addi 1,x2,x2 /* cannot carry */
1328 shd 0,x2,30,x1 /* multiply by 5 to get started */
1333 /* DIVISION BY 10 (shift to divide by 2 then divide by 5) */
1335 .export $$divU_10,millicode
1336 extru x2,30,31,x2 /* divide by 2 */
1337 addi 3,x2,t1 /* compute 3*(x2+1) = (3*x2)+3 */
1338 sh1add x2,t1,x2 /* multiply by 3 to get started */
1341 shd x1,x2,28,t1 /* multiply by 0x11 */
1346 shd x1,x2,24,t1 /* multiply by 0x101 */
1351 shd x1,x2,16,t1 /* multiply by 0x10001 */
1358 .export $$divI_10,millicode
1359 comb,< x2,0,LREF(neg10)
1361 extru x2,30,31,x2 /* divide by 2 */
1362 addib,TR 1,x2,LREF(pos) /* add 1 (cannot overflow) */
1363 sh1add x2,x2,x2 /* multiply by 3 to get started */
1366 subi 2,x2,x2 /* negate, divide by 2, and add 1 */
1367 /* negation and adding 1 are done */
1368 /* at the same time by the SUBI */
1370 sh1add x2,x2,x2 /* multiply by 3 to get started */
1372 shd x1,x2,28,t1 /* multiply by 0x11 */
1377 shd x1,x2,24,t1 /* multiply by 0x101 */
1382 shd x1,x2,16,t1 /* multiply by 0x10001 */
1389 /* DIVISION BY 12 (shift to divide by 4 then divide by 3) */
1391 .export $$divI_12,millicode
1392 comb,< x2,0,LREF(neg12)
1394 extru x2,29,30,x2 /* divide by 4 */
1395 addib,tr 1,x2,LREF(pos) /* compute 5*(x2+1) = 5*x2+5 */
1396 sh2add x2,x2,x2 /* multiply by 5 to get started */
1399 subi 4,x2,x2 /* negate, divide by 4, and add 1 */
1400 /* negation and adding 1 are done */
1401 /* at the same time by the SUBI */
1404 sh2add x2,x2,x2 /* multiply by 5 to get started */
1407 .export $$divU_12,millicode
1408 extru x2,29,30,x2 /* divide by 4 */
1409 addi 5,x2,t1 /* cannot carry */
1410 sh2add x2,t1,x2 /* multiply by 5 to get started */
1414 /* DIVISION BY 15 (use z = 2**32; a = 11111111) */
1416 .export $$divI_15,millicode
1417 comb,< x2,0,LREF(neg15)
1419 addib,tr 1,x2,LREF(pos)+4
1427 .export $$divU_15,millicode
1428 addi 1,x2,x2 /* this CAN overflow */
1432 /* DIVISION BY 17 (use z = 2**32; a = f0f0f0f) */
1434 .export $$divI_17,millicode
1435 comb,<,n x2,0,LREF(neg17)
1436 addi 1,x2,x2 /* this cannot overflow */
1437 shd 0,x2,28,t1 /* multiply by 0xf to get started */
1444 subi 1,x2,x2 /* this cannot overflow */
1445 shd 0,x2,28,t1 /* multiply by 0xf to get started */
1452 .export $$divU_17,millicode
1453 addi 1,x2,x2 /* this CAN overflow */
1455 shd x1,x2,28,t1 /* multiply by 0xf to get started */
1463 /* DIVISION BY DIVISORS OF FFFFFF, and powers of 2 times these
1464 includes 7,9 and also 14
1472 Also, in order to divide by z = 2**24-1, we approximate by dividing
1473 by (z+1) = 2**24 (which is easy), and then correcting.
1478 So to compute (ax)/z, compute q' = (ax)/(z+1) and r = (ax) mod (z+1)
1479 Then the true remainder of (ax)/z is (q'+r). Repeat the process
1480 with this new remainder, adding the tentative quotients together,
1481 until a tentative quotient is 0 (and then we are done). There is
1482 one last correction to be done. It is possible that (q'+r) = z.
1483 If so, then (q'+r)/(z+1) = 0 and it looks like we are done. But,
1484 in fact, we need to add 1 more to the quotient. Now, it turns
1485 out that this happens if and only if the original value x is
1486 an exact multiple of y. So, to avoid a three instruction test at
1487 the end, instead use 1 instruction to add 1 to x at the beginning. */
1489 /* DIVISION BY 7 (use z = 2**24-1; a = 249249) */
1491 .export $$divI_7,millicode
1492 comb,<,n x2,0,LREF(neg7)
1494 addi 1,x2,x2 /* cannot overflow */
1509 /* computed <t1,x2>. Now divide it by (2**24 - 1) */
1512 shd,= t1,x2,24,t1 /* tentative quotient */
1514 addb,tr t1,x1,LREF(2) /* add to previous quotient */
1515 extru x2,31,24,x2 /* new remainder (unadjusted) */
1520 addb,tr t1,x2,LREF(1) /* adjust remainder */
1521 extru,= x2,7,8,t1 /* new quotient */
1524 subi 1,x2,x2 /* negate x2 and add 1 */
1541 /* computed <t1,x2>. Now divide it by (2**24 - 1) */
1544 shd,= t1,x2,24,t1 /* tentative quotient */
1546 addb,tr t1,x1,LREF(4) /* add to previous quotient */
1547 extru x2,31,24,x2 /* new remainder (unadjusted) */
1550 sub 0,x1,x1 /* negate result */
1553 addb,tr t1,x2,LREF(3) /* adjust remainder */
1554 extru,= x2,7,8,t1 /* new quotient */
1557 .export $$divU_7,millicode
1558 addi 1,x2,x2 /* can carry */
1565 /* DIVISION BY 9 (use z = 2**24-1; a = 1c71c7) */
1567 .export $$divI_9,millicode
1568 comb,<,n x2,0,LREF(neg9)
1569 addi 1,x2,x2 /* cannot overflow */
1577 subi 1,x2,x2 /* negate and add 1 */
1585 .export $$divU_9,millicode
1586 addi 1,x2,x2 /* can carry */
1594 /* DIVISION BY 14 (shift to divide by 2 then divide by 7) */
1596 .export $$divI_14,millicode
1597 comb,<,n x2,0,LREF(neg14)
1599 .export $$divU_14,millicode
1600 b LREF(7) /* go to 7 case */
1601 extru x2,30,31,x2 /* divide by 2 */
1604 subi 2,x2,x2 /* negate (and add 2) */
1606 extru x2,30,31,x2 /* divide by 2 */
1613 /* VERSION "@(#)$$mulI $ Revision: 12.4 $ $ Date: 94/03/17 17:18:51 $" */
1614 /******************************************************************************
1615 This routine is used on PA2.0 processors when gcc -mno-fpregs is used
1622 $$mulI multiplies two single word integers, giving a single
1631 sr0 == return space when called externally
1640 OTHER REGISTERS AFFECTED:
1646 Causes a trap under the following conditions: NONE
1647 Changes memory at the following places: NONE
1649 PERMISSIBLE CONTEXT:
1652 Does not create a stack frame
1653 Is usable for internal or external microcode
1657 Calls other millicode routines via mrp: NONE
1658 Calls other millicode routines: NONE
1660 ***************************************************************************/
1668 #define a0__128a0 zdep a0,24,25,a0
1669 #define a0__256a0 zdep a0,23,24,a0
1670 #define a1_ne_0_b_l0 comb,<> a1,0,LREF(l0)
1671 #define a1_ne_0_b_l1 comb,<> a1,0,LREF(l1)
1672 #define a1_ne_0_b_l2 comb,<> a1,0,LREF(l2)
1673 #define b_n_ret_t0 b,n LREF(ret_t0)
1674 #define b_e_shift b LREF(e_shift)
1675 #define b_e_t0ma0 b LREF(e_t0ma0)
1676 #define b_e_t0 b LREF(e_t0)
1677 #define b_e_t0a0 b LREF(e_t0a0)
1678 #define b_e_t02a0 b LREF(e_t02a0)
1679 #define b_e_t04a0 b LREF(e_t04a0)
1680 #define b_e_2t0 b LREF(e_2t0)
1681 #define b_e_2t0a0 b LREF(e_2t0a0)
1682 #define b_e_2t04a0 b LREF(e2t04a0)
1683 #define b_e_3t0 b LREF(e_3t0)
1684 #define b_e_4t0 b LREF(e_4t0)
1685 #define b_e_4t0a0 b LREF(e_4t0a0)
1686 #define b_e_4t08a0 b LREF(e4t08a0)
1687 #define b_e_5t0 b LREF(e_5t0)
1688 #define b_e_8t0 b LREF(e_8t0)
1689 #define b_e_8t0a0 b LREF(e_8t0a0)
1690 #define r__r_a0 add r,a0,r
1691 #define r__r_2a0 sh1add a0,r,r
1692 #define r__r_4a0 sh2add a0,r,r
1693 #define r__r_8a0 sh3add a0,r,r
1694 #define r__r_t0 add r,t0,r
1695 #define r__r_2t0 sh1add t0,r,r
1696 #define r__r_4t0 sh2add t0,r,r
1697 #define r__r_8t0 sh3add t0,r,r
1698 #define t0__3a0 sh1add a0,a0,t0
1699 #define t0__4a0 sh2add a0,0,t0
1700 #define t0__5a0 sh2add a0,a0,t0
1701 #define t0__8a0 sh3add a0,0,t0
1702 #define t0__9a0 sh3add a0,a0,t0
1703 #define t0__16a0 zdep a0,27,28,t0
1704 #define t0__32a0 zdep a0,26,27,t0
1705 #define t0__64a0 zdep a0,25,26,t0
1706 #define t0__128a0 zdep a0,24,25,t0
1707 #define t0__t0ma0 sub t0,a0,t0
1708 #define t0__t0_a0 add t0,a0,t0
1709 #define t0__t0_2a0 sh1add a0,t0,t0
1710 #define t0__t0_4a0 sh2add a0,t0,t0
1711 #define t0__t0_8a0 sh3add a0,t0,t0
1712 #define t0__2t0_a0 sh1add t0,a0,t0
1713 #define t0__3t0 sh1add t0,t0,t0
1714 #define t0__4t0 sh2add t0,0,t0
1715 #define t0__4t0_a0 sh2add t0,a0,t0
1716 #define t0__5t0 sh2add t0,t0,t0
1717 #define t0__8t0 sh3add t0,0,t0
1718 #define t0__8t0_a0 sh3add t0,a0,t0
1719 #define t0__9t0 sh3add t0,t0,t0
1720 #define t0__16t0 zdep t0,27,28,t0
1721 #define t0__32t0 zdep t0,26,27,t0
1722 #define t0__256a0 zdep a0,23,24,t0
1730 .export $$mulI,millicode
1732 combt,<<= a1,a0,LREF(l4) /* swap args if unsigned a1>a0 */
1733 copy 0,r /* zero out the result */
1734 xor a0,a1,a0 /* swap a0 & a1 using the */
1735 xor a0,a1,a1 /* old xor trick */
1738 combt,<= 0,a0,LREF(l3) /* if a0>=0 then proceed like unsigned */
1739 zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
1740 sub,> 0,a1,t0 /* otherwise negate both and */
1741 combt,<=,n a0,t0,LREF(l2) /* swap back if |a0|<|a1| */
1743 movb,tr,n t0,a0,LREF(l2) /* 10th inst. */
1745 LSYM(l0) r__r_t0 /* add in this partial product */
1746 LSYM(l1) a0__256a0 /* a0 <<= 8 ****************** */
1747 LSYM(l2) zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
1748 LSYM(l3) blr t0,0 /* case on these 8 bits ****** */
1749 extru a1,23,24,a1 /* a1 >>= 8 ****************** */
1751 /*16 insts before this. */
1752 /* a0 <<= 8 ************************** */
1753 LSYM(x0) a1_ne_0_b_l2 ! a0__256a0 ! MILLIRETN ! nop
1754 LSYM(x1) a1_ne_0_b_l1 ! r__r_a0 ! MILLIRETN ! nop
1755 LSYM(x2) a1_ne_0_b_l1 ! r__r_2a0 ! MILLIRETN ! nop
1756 LSYM(x3) a1_ne_0_b_l0 ! t0__3a0 ! MILLIRET ! r__r_t0
1757 LSYM(x4) a1_ne_0_b_l1 ! r__r_4a0 ! MILLIRETN ! nop
1758 LSYM(x5) a1_ne_0_b_l0 ! t0__5a0 ! MILLIRET ! r__r_t0
1759 LSYM(x6) t0__3a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
1760 LSYM(x7) t0__3a0 ! a1_ne_0_b_l0 ! r__r_4a0 ! b_n_ret_t0
1761 LSYM(x8) a1_ne_0_b_l1 ! r__r_8a0 ! MILLIRETN ! nop
1762 LSYM(x9) a1_ne_0_b_l0 ! t0__9a0 ! MILLIRET ! r__r_t0
1763 LSYM(x10) t0__5a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
1764 LSYM(x11) t0__3a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
1765 LSYM(x12) t0__3a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
1766 LSYM(x13) t0__5a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
1767 LSYM(x14) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
1768 LSYM(x15) t0__5a0 ! a1_ne_0_b_l0 ! t0__3t0 ! b_n_ret_t0
1769 LSYM(x16) t0__16a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1770 LSYM(x17) t0__9a0 ! a1_ne_0_b_l0 ! t0__t0_8a0 ! b_n_ret_t0
1771 LSYM(x18) t0__9a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
1772 LSYM(x19) t0__9a0 ! a1_ne_0_b_l0 ! t0__2t0_a0 ! b_n_ret_t0
1773 LSYM(x20) t0__5a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
1774 LSYM(x21) t0__5a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
1775 LSYM(x22) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
1776 LSYM(x23) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
1777 LSYM(x24) t0__3a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
1778 LSYM(x25) t0__5a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
1779 LSYM(x26) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
1780 LSYM(x27) t0__3a0 ! a1_ne_0_b_l0 ! t0__9t0 ! b_n_ret_t0
1781 LSYM(x28) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1782 LSYM(x29) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
1783 LSYM(x30) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
1784 LSYM(x31) t0__32a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
1785 LSYM(x32) t0__32a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1786 LSYM(x33) t0__8a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
1787 LSYM(x34) t0__16a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
1788 LSYM(x35) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__t0_8a0
1789 LSYM(x36) t0__9a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
1790 LSYM(x37) t0__9a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
1791 LSYM(x38) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
1792 LSYM(x39) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
1793 LSYM(x40) t0__5a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
1794 LSYM(x41) t0__5a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
1795 LSYM(x42) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
1796 LSYM(x43) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
1797 LSYM(x44) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1798 LSYM(x45) t0__9a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
1799 LSYM(x46) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_a0
1800 LSYM(x47) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_2a0
1801 LSYM(x48) t0__3a0 ! a1_ne_0_b_l0 ! t0__16t0 ! b_n_ret_t0
1802 LSYM(x49) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_4a0
1803 LSYM(x50) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
1804 LSYM(x51) t0__9a0 ! t0__t0_8a0 ! b_e_t0 ! t0__3t0
1805 LSYM(x52) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1806 LSYM(x53) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
1807 LSYM(x54) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
1808 LSYM(x55) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__2t0_a0
1809 LSYM(x56) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1810 LSYM(x57) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__3t0
1811 LSYM(x58) t0__3a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
1812 LSYM(x59) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__3t0
1813 LSYM(x60) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
1814 LSYM(x61) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
1815 LSYM(x62) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
1816 LSYM(x63) t0__64a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
1817 LSYM(x64) t0__64a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1818 LSYM(x65) t0__8a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
1819 LSYM(x66) t0__32a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
1820 LSYM(x67) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
1821 LSYM(x68) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1822 LSYM(x69) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
1823 LSYM(x70) t0__64a0 ! t0__t0_4a0 ! b_e_t0 ! t0__t0_2a0
1824 LSYM(x71) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__t0ma0
1825 LSYM(x72) t0__9a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
1826 LSYM(x73) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_t0
1827 LSYM(x74) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
1828 LSYM(x75) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
1829 LSYM(x76) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1830 LSYM(x77) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
1831 LSYM(x78) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__2t0_a0
1832 LSYM(x79) t0__16a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
1833 LSYM(x80) t0__16a0 ! t0__5t0 ! b_e_shift ! r__r_t0
1834 LSYM(x81) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_t0
1835 LSYM(x82) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
1836 LSYM(x83) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
1837 LSYM(x84) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1838 LSYM(x85) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
1839 LSYM(x86) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
1840 LSYM(x87) t0__9a0 ! t0__9t0 ! b_e_t02a0 ! t0__t0_4a0
1841 LSYM(x88) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1842 LSYM(x89) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
1843 LSYM(x90) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
1844 LSYM(x91) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__2t0_a0
1845 LSYM(x92) t0__5a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
1846 LSYM(x93) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__3t0
1847 LSYM(x94) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__t0_2a0
1848 LSYM(x95) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
1849 LSYM(x96) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
1850 LSYM(x97) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
1851 LSYM(x98) t0__32a0 ! t0__3t0 ! b_e_t0 ! t0__t0_2a0
1852 LSYM(x99) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
1853 LSYM(x100) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
1854 LSYM(x101) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
1855 LSYM(x102) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
1856 LSYM(x103) t0__5a0 ! t0__5t0 ! b_e_t02a0 ! t0__4t0_a0
1857 LSYM(x104) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
1858 LSYM(x105) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
1859 LSYM(x106) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__4t0_a0
1860 LSYM(x107) t0__9a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__8t0_a0
1861 LSYM(x108) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
1862 LSYM(x109) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
1863 LSYM(x110) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__2t0_a0
1864 LSYM(x111) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
1865 LSYM(x112) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__16t0
1866 LSYM(x113) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__3t0
1867 LSYM(x114) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__3t0
1868 LSYM(x115) t0__9a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__3t0
1869 LSYM(x116) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__4t0_a0
1870 LSYM(x117) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
1871 LSYM(x118) t0__3a0 ! t0__4t0_a0 ! b_e_t0a0 ! t0__9t0
1872 LSYM(x119) t0__3a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__9t0
1873 LSYM(x120) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
1874 LSYM(x121) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
1875 LSYM(x122) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
1876 LSYM(x123) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
1877 LSYM(x124) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
1878 LSYM(x125) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
1879 LSYM(x126) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
1880 LSYM(x127) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
1881 LSYM(x128) t0__128a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1882 LSYM(x129) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0_a0 ! b_n_ret_t0
1883 LSYM(x130) t0__64a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
1884 LSYM(x131) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
1885 LSYM(x132) t0__8a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1886 LSYM(x133) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
1887 LSYM(x134) t0__8a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
1888 LSYM(x135) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__3t0
1889 LSYM(x136) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1890 LSYM(x137) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
1891 LSYM(x138) t0__8a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
1892 LSYM(x139) t0__8a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__4t0_a0
1893 LSYM(x140) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__5t0
1894 LSYM(x141) t0__8a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__2t0_a0
1895 LSYM(x142) t0__9a0 ! t0__8t0 ! b_e_2t0 ! t0__t0ma0
1896 LSYM(x143) t0__16a0 ! t0__9t0 ! b_e_t0 ! t0__t0ma0
1897 LSYM(x144) t0__9a0 ! t0__8t0 ! b_e_shift ! r__r_2t0
1898 LSYM(x145) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__2t0_a0
1899 LSYM(x146) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
1900 LSYM(x147) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
1901 LSYM(x148) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1902 LSYM(x149) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
1903 LSYM(x150) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
1904 LSYM(x151) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
1905 LSYM(x152) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1906 LSYM(x153) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
1907 LSYM(x154) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
1908 LSYM(x155) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__5t0
1909 LSYM(x156) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
1910 LSYM(x157) t0__32a0 ! t0__t0ma0 ! b_e_t02a0 ! t0__5t0
1911 LSYM(x158) t0__16a0 ! t0__5t0 ! b_e_2t0 ! t0__t0ma0
1912 LSYM(x159) t0__32a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
1913 LSYM(x160) t0__5a0 ! t0__4t0 ! b_e_shift ! r__r_8t0
1914 LSYM(x161) t0__8a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
1915 LSYM(x162) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_2t0
1916 LSYM(x163) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__2t0_a0
1917 LSYM(x164) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_4t0
1918 LSYM(x165) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
1919 LSYM(x166) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__2t0_a0
1920 LSYM(x167) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
1921 LSYM(x168) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
1922 LSYM(x169) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__8t0_a0
1923 LSYM(x170) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__5t0
1924 LSYM(x171) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__9t0
1925 LSYM(x172) t0__5a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__2t0_a0
1926 LSYM(x173) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__9t0
1927 LSYM(x174) t0__32a0 ! t0__t0_2a0 ! b_e_t04a0 ! t0__5t0
1928 LSYM(x175) t0__8a0 ! t0__2t0_a0 ! b_e_5t0 ! t0__2t0_a0
1929 LSYM(x176) t0__5a0 ! t0__4t0_a0 ! b_e_8t0 ! t0__t0_a0
1930 LSYM(x177) t0__5a0 ! t0__4t0_a0 ! b_e_8t0a0 ! t0__t0_a0
1931 LSYM(x178) t0__5a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__8t0_a0
1932 LSYM(x179) t0__5a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__8t0_a0
1933 LSYM(x180) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
1934 LSYM(x181) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
1935 LSYM(x182) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__2t0_a0
1936 LSYM(x183) t0__9a0 ! t0__5t0 ! b_e_2t0a0 ! t0__2t0_a0
1937 LSYM(x184) t0__5a0 ! t0__9t0 ! b_e_4t0 ! t0__t0_a0
1938 LSYM(x185) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
1939 LSYM(x186) t0__32a0 ! t0__t0ma0 ! b_e_2t0 ! t0__3t0
1940 LSYM(x187) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__5t0
1941 LSYM(x188) t0__9a0 ! t0__5t0 ! b_e_4t0 ! t0__t0_2a0
1942 LSYM(x189) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
1943 LSYM(x190) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__5t0
1944 LSYM(x191) t0__64a0 ! t0__3t0 ! b_e_t0 ! t0__t0ma0
1945 LSYM(x192) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
1946 LSYM(x193) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
1947 LSYM(x194) t0__8a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
1948 LSYM(x195) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
1949 LSYM(x196) t0__8a0 ! t0__3t0 ! b_e_4t0 ! t0__2t0_a0
1950 LSYM(x197) t0__8a0 ! t0__3t0 ! b_e_4t0a0 ! t0__2t0_a0
1951 LSYM(x198) t0__64a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
1952 LSYM(x199) t0__8a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
1953 LSYM(x200) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_8t0
1954 LSYM(x201) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__8t0_a0
1955 LSYM(x202) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__4t0_a0
1956 LSYM(x203) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__4t0_a0
1957 LSYM(x204) t0__8a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
1958 LSYM(x205) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__5t0
1959 LSYM(x206) t0__64a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__3t0
1960 LSYM(x207) t0__8a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
1961 LSYM(x208) t0__5a0 ! t0__5t0 ! b_e_8t0 ! t0__t0_a0
1962 LSYM(x209) t0__5a0 ! t0__5t0 ! b_e_8t0a0 ! t0__t0_a0
1963 LSYM(x210) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__5t0
1964 LSYM(x211) t0__5a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__5t0
1965 LSYM(x212) t0__3a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__4t0_a0
1966 LSYM(x213) t0__3a0 ! t0__4t0_a0 ! b_e_4t0a0 ! t0__4t0_a0
1967 LSYM(x214) t0__9a0 ! t0__t0_4a0 ! b_e_2t04a0 ! t0__8t0_a0
1968 LSYM(x215) t0__5a0 ! t0__4t0_a0 ! b_e_5t0 ! t0__2t0_a0
1969 LSYM(x216) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
1970 LSYM(x217) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
1971 LSYM(x218) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
1972 LSYM(x219) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
1973 LSYM(x220) t0__3a0 ! t0__9t0 ! b_e_4t0 ! t0__2t0_a0
1974 LSYM(x221) t0__3a0 ! t0__9t0 ! b_e_4t0a0 ! t0__2t0_a0
1975 LSYM(x222) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__3t0
1976 LSYM(x223) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
1977 LSYM(x224) t0__9a0 ! t0__3t0 ! b_e_8t0 ! t0__t0_a0
1978 LSYM(x225) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
1979 LSYM(x226) t0__3a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__32t0
1980 LSYM(x227) t0__9a0 ! t0__5t0 ! b_e_t02a0 ! t0__5t0
1981 LSYM(x228) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
1982 LSYM(x229) t0__9a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__3t0
1983 LSYM(x230) t0__9a0 ! t0__5t0 ! b_e_5t0 ! t0__t0_a0
1984 LSYM(x231) t0__9a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
1985 LSYM(x232) t0__3a0 ! t0__2t0_a0 ! b_e_8t0 ! t0__4t0_a0
1986 LSYM(x233) t0__3a0 ! t0__2t0_a0 ! b_e_8t0a0 ! t0__4t0_a0
1987 LSYM(x234) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__9t0
1988 LSYM(x235) t0__3a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__9t0
1989 LSYM(x236) t0__9a0 ! t0__2t0_a0 ! b_e_4t08a0 ! t0__3t0
1990 LSYM(x237) t0__16a0 ! t0__5t0 ! b_e_3t0 ! t0__t0ma0
1991 LSYM(x238) t0__3a0 ! t0__4t0_a0 ! b_e_2t04a0 ! t0__9t0
1992 LSYM(x239) t0__16a0 ! t0__5t0 ! b_e_t0ma0 ! t0__3t0
1993 LSYM(x240) t0__9a0 ! t0__t0_a0 ! b_e_8t0 ! t0__3t0
1994 LSYM(x241) t0__9a0 ! t0__t0_a0 ! b_e_8t0a0 ! t0__3t0
1995 LSYM(x242) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__8t0_a0
1996 LSYM(x243) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__3t0
1997 LSYM(x244) t0__5a0 ! t0__3t0 ! b_e_4t0 ! t0__4t0_a0
1998 LSYM(x245) t0__8a0 ! t0__3t0 ! b_e_5t0 ! t0__2t0_a0
1999 LSYM(x246) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__3t0
2000 LSYM(x247) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__3t0
2001 LSYM(x248) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_8t0
2002 LSYM(x249) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__8t0_a0
2003 LSYM(x250) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__5t0
2004 LSYM(x251) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__5t0
2005 LSYM(x252) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
2006 LSYM(x253) t0__64a0 ! t0__t0ma0 ! b_e_t0 ! t0__4t0_a0
2007 LSYM(x254) t0__128a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
2008 LSYM(x255) t0__256a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
2009 /*1040 insts before this. */
2010 LSYM(ret_t0) MILLIRET
2012 LSYM(e_shift) a1_ne_0_b_l2
2013 a0__256a0 /* a0 <<= 8 *********** */
2015 LSYM(e_t0ma0) a1_ne_0_b_l0
2019 LSYM(e_t0a0) a1_ne_0_b_l0
2023 LSYM(e_t02a0) a1_ne_0_b_l0
2027 LSYM(e_t04a0) a1_ne_0_b_l0
2031 LSYM(e_2t0) a1_ne_0_b_l1
2034 LSYM(e_2t0a0) a1_ne_0_b_l0
2038 LSYM(e2t04a0) t0__t0_2a0
2042 LSYM(e_3t0) a1_ne_0_b_l0
2046 LSYM(e_4t0) a1_ne_0_b_l1
2049 LSYM(e_4t0a0) a1_ne_0_b_l0
2053 LSYM(e4t08a0) t0__t0_2a0
2057 LSYM(e_5t0) a1_ne_0_b_l0
2061 LSYM(e_8t0) a1_ne_0_b_l1
2064 LSYM(e_8t0a0) a1_ne_0_b_l0