arch/powerpc/include/asm/cputable.h

   1 #ifndef __ASM_POWERPC_CPUTABLE_H
   2 #define __ASM_POWERPC_CPUTABLE_H
   3
   4
   5 #include <asm/asm-compat.h>
   6 #include <asm/feature-fixups.h>
   7 #include <uapi/asm/cputable.h>
   8
   9 #ifndef __ASSEMBLY__
  10
  11 /* This structure can grow, it's real size is used by head.S code
  12  * via the mkdefs mechanism.
  13  */
  14 struct cpu_spec;
  15
  16 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  17 typedef void (*cpu_restore_t)(void);
  18
  19 enum powerpc_oprofile_type {
  20         PPC_OPROFILE_INVALID = 0,
  21         PPC_OPROFILE_RS64 = 1,
  22         PPC_OPROFILE_POWER4 = 2,
  23         PPC_OPROFILE_G4 = 3,
  24         PPC_OPROFILE_FSL_EMB = 4,
  25         PPC_OPROFILE_CELL = 5,
  26         PPC_OPROFILE_PA6T = 6,
  27 };
  28
  29 enum powerpc_pmc_type {
  30         PPC_PMC_DEFAULT = 0,
  31         PPC_PMC_IBM = 1,
  32         PPC_PMC_PA6T = 2,
  33         PPC_PMC_G4 = 3,
  34 };
  35
  36 struct pt_regs;
  37
  38 extern int machine_check_generic(struct pt_regs *regs);
  39 extern int machine_check_4xx(struct pt_regs *regs);
  40 extern int machine_check_440A(struct pt_regs *regs);
  41 extern int machine_check_e500mc(struct pt_regs *regs);
  42 extern int machine_check_e500(struct pt_regs *regs);
  43 extern int machine_check_e200(struct pt_regs *regs);
  44 extern int machine_check_47x(struct pt_regs *regs);
  45
  46 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
  47 struct cpu_spec {
  48         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  49         unsigned int    pvr_mask;
  50         unsigned int    pvr_value;
  51
  52         char            *cpu_name;
  53         unsigned long   cpu_features;           /* Kernel features */
  54         unsigned int    cpu_user_features;      /* Userland features */
  55         unsigned int    mmu_features;           /* MMU features */
  56
  57         /* cache line sizes */
  58         unsigned int    icache_bsize;
  59         unsigned int    dcache_bsize;
  60
  61         /* number of performance monitor counters */
  62         unsigned int    num_pmcs;
  63         enum powerpc_pmc_type pmc_type;
  64
  65         /* this is called to initialize various CPU bits like L1 cache,
  66          * BHT, SPD, etc... from head.S before branching to identify_machine
  67          */
  68         cpu_setup_t     cpu_setup;
  69         /* Used to restore cpu setup on secondary processors and at resume */
  70         cpu_restore_t   cpu_restore;
  71
  72         /* Used by oprofile userspace to select the right counters */
  73         char            *oprofile_cpu_type;
  74
  75         /* Processor specific oprofile operations */
  76         enum powerpc_oprofile_type oprofile_type;
  77
  78         /* Bit locations inside the mmcra change */
  79         unsigned long   oprofile_mmcra_sihv;
  80         unsigned long   oprofile_mmcra_sipr;
  81
  82         /* Bits to clear during an oprofile exception */
  83         unsigned long   oprofile_mmcra_clear;
  84
  85         /* Name of processor class, for the ELF AT_PLATFORM entry */
  86         char            *platform;
  87
  88         /* Processor specific machine check handling. Return negative
  89          * if the error is fatal, 1 if it was fully recovered and 0 to
  90          * pass up (not CPU originated) */
  91         int             (*machine_check)(struct pt_regs *regs);
  92 };
  93
  94 extern struct cpu_spec          *cur_cpu_spec;
  95
  96 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
  97
  98 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
  99 extern void do_feature_fixups(unsigned long value, void *fixup_start,
 100                               void *fixup_end);
 101
 102 extern const char *powerpc_base_platform;
 103
 104 #endif /* __ASSEMBLY__ */
 105
 106 /* CPU kernel features */
 107
 108 /* Retain the 32b definitions all use bottom half of word */
 109 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x00000001)
 110 #define CPU_FTR_L2CR                    ASM_CONST(0x00000002)
 111 #define CPU_FTR_SPEC7450                ASM_CONST(0x00000004)
 112 #define CPU_FTR_ALTIVEC                 ASM_CONST(0x00000008)
 113 #define CPU_FTR_TAU                     ASM_CONST(0x00000010)
 114 #define CPU_FTR_CAN_DOZE                ASM_CONST(0x00000020)
 115 #define CPU_FTR_USE_TB                  ASM_CONST(0x00000040)
 116 #define CPU_FTR_L2CSR                   ASM_CONST(0x00000080)
 117 #define CPU_FTR_601                     ASM_CONST(0x00000100)
 118 #define CPU_FTR_DBELL                   ASM_CONST(0x00000200)
 119 #define CPU_FTR_CAN_NAP                 ASM_CONST(0x00000400)
 120 #define CPU_FTR_L3CR                    ASM_CONST(0x00000800)
 121 #define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x00001000)
 122 #define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x00002000)
 123 #define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x00004000)
 124 #define CPU_FTR_NO_DPM                  ASM_CONST(0x00008000)
 125 #define CPU_FTR_476_DD2                 ASM_CONST(0x00010000)
 126 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x00020000)
 127 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x00040000)
 128 #define CPU_FTR_DEBUG_LVL_EXC           ASM_CONST(0x00080000)
 129 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x00100000)
 130 #define CPU_FTR_PPC_LE                  ASM_CONST(0x00200000)
 131 #define CPU_FTR_REAL_LE                 ASM_CONST(0x00400000)
 132 #define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x00800000)
 133 #define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x01000000)
 134 #define CPU_FTR_SPE                     ASM_CONST(0x02000000)
 135 #define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x04000000)
 136 #define CPU_FTR_LWSYNC                  ASM_CONST(0x08000000)
 137 #define CPU_FTR_NOEXECUTE               ASM_CONST(0x10000000)
 138 #define CPU_FTR_INDEXED_DCR             ASM_CONST(0x20000000)
 139 #define CPU_FTR_EMB_HV                  ASM_CONST(0x40000000)
 140
 141 /*
 142  * Add the 64-bit processor unique features in the top half of the word;
 143  * on 32-bit, make the names available but defined to be 0.
 144  */
 145 #ifdef __powerpc64__
 146 #define LONG_ASM_CONST(x)               ASM_CONST(x)
 147 #else
 148 #define LONG_ASM_CONST(x)               0
 149 #endif
 150
 151 #define CPU_FTR_HVMODE                  LONG_ASM_CONST(0x0000000100000000)
 152 #define CPU_FTR_ARCH_201                LONG_ASM_CONST(0x0000000200000000)
 153 #define CPU_FTR_ARCH_206                LONG_ASM_CONST(0x0000000400000000)
 154 #define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0000000800000000)
 155 #define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000001000000000)
 156 #define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000002000000000)
 157 #define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000004000000000)
 158 #define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000008000000000)
 159 #define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000010000000000)
 160 #define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000020000000000)
 161 #define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000040000000000)
 162 #define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0000080000000000)
 163 #define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0000100000000000)
 164 #define CPU_FTR_VSX                     LONG_ASM_CONST(0x0000200000000000)
 165 #define CPU_FTR_SAO                     LONG_ASM_CONST(0x0000400000000000)
 166 #define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0000800000000000)
 167 #define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0001000000000000)
 168 #define CPU_FTR_ASYM_SMT                LONG_ASM_CONST(0x0002000000000000)
 169 #define CPU_FTR_STCX_CHECKS_ADDRESS     LONG_ASM_CONST(0x0004000000000000)
 170 #define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0008000000000000)
 171 #define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0010000000000000)
 172 #define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x0020000000000000)
 173 #define CPU_FTR_VMX_COPY                LONG_ASM_CONST(0x0040000000000000)
 174 #define CPU_FTR_TM                      LONG_ASM_CONST(0x0080000000000000)
 175 #define CPU_FTR_BCTAR                   LONG_ASM_CONST(0x0100000000000000)
 176 #define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 177
 178 #ifndef __ASSEMBLY__
 179
 180 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
 181
 182 #define MMU_FTR_PPCAS_ARCH_V2   (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
 183                                  MMU_FTR_16M_PAGE)
 184
 185 /* We only set the altivec features if the kernel was compiled with altivec
 186  * support
 187  */
 188 #ifdef CONFIG_ALTIVEC
 189 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 190 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 191 #else
 192 #define CPU_FTR_ALTIVEC_COMP    0
 193 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 194 #endif
 195
 196 /* We only set the VSX features if the kernel was compiled with VSX
 197  * support
 198  */
 199 #ifdef CONFIG_VSX
 200 #define CPU_FTR_VSX_COMP        CPU_FTR_VSX
 201 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
 202 #else
 203 #define CPU_FTR_VSX_COMP        0
 204 #define PPC_FEATURE_HAS_VSX_COMP    0
 205 #endif
 206
 207 /* We only set the spe features if the kernel was compiled with spe
 208  * support
 209  */
 210 #ifdef CONFIG_SPE
 211 #define CPU_FTR_SPE_COMP        CPU_FTR_SPE
 212 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
 213 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
 214 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
 215 #else
 216 #define CPU_FTR_SPE_COMP        0
 217 #define PPC_FEATURE_HAS_SPE_COMP    0
 218 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
 219 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
 220 #endif
 221
 222 /* We need to mark all pages as being coherent if we're SMP or we have a
 223  * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
 224  * require it for PCI "streaming/prefetch" to work properly.
 225  * This is also required by 52xx family.
 226  */
 227 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
 228         || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
 229         || defined(CONFIG_PPC_MPC52xx)
 230 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 231 #else
 232 #define CPU_FTR_COMMON                  0
 233 #endif
 234
 235 /* The powersave features NAP & DOZE seems to confuse BDI when
 236    debugging. So if a BDI is used, disable theses
 237  */
 238 #ifndef CONFIG_BDI_SWITCH
 239 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 240 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 241 #else
 242 #define CPU_FTR_MAYBE_CAN_DOZE  0
 243 #define CPU_FTR_MAYBE_CAN_NAP   0
 244 #endif
 245
 246 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
 247                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
 248                      !defined(CONFIG_BOOKE))
 249
 250 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
 251         CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
 252 #define CPU_FTRS_603    (CPU_FTR_COMMON | \
 253             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 254             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 255 #define CPU_FTRS_604    (CPU_FTR_COMMON | \
 256             CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
 257 #define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
 258             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 259             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 260 #define CPU_FTRS_740    (CPU_FTR_COMMON | \
 261             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 262             CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 263             CPU_FTR_PPC_LE)
 264 #define CPU_FTRS_750    (CPU_FTR_COMMON | \
 265             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 266             CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 267             CPU_FTR_PPC_LE)
 268 #define CPU_FTRS_750CL  (CPU_FTRS_750)
 269 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
 270 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
 271 #define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
 272 #define CPU_FTRS_750GX  (CPU_FTRS_750FX)
 273 #define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
 274             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 275             CPU_FTR_ALTIVEC_COMP | \
 276             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 277 #define CPU_FTRS_7400   (CPU_FTR_COMMON | \
 278             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 279             CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
 280             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 281 #define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
 282             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 283             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 284             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 285 #define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
 286             CPU_FTR_USE_TB | \
 287             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 288             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 289             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 290             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 291 #define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
 292             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 293             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 294             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 295             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 296 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
 297             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 298             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 299             CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 300 #define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
 301             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 302             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 303             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 304             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 305             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 306 #define CPU_FTRS_7455   (CPU_FTR_COMMON | \
 307             CPU_FTR_USE_TB | \
 308             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 309             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 310             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 311 #define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
 312             CPU_FTR_USE_TB | \
 313             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 314             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 315             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
 316             CPU_FTR_NEED_PAIRED_STWCX)
 317 #define CPU_FTRS_7447   (CPU_FTR_COMMON | \
 318             CPU_FTR_USE_TB | \
 319             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 320             CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 321             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 322 #define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
 323             CPU_FTR_USE_TB | \
 324             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 325             CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 326             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 327 #define CPU_FTRS_7448   (CPU_FTR_COMMON | \
 328             CPU_FTR_USE_TB | \
 329             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 330             CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 331             CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 332 #define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
 333             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 334 #define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
 335             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
 336 #define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
 337             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 338             CPU_FTR_COMMON)
 339 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
 340             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 341             CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 342 #define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_USE_TB)
 343 #define CPU_FTRS_8XX    (CPU_FTR_USE_TB)
 344 #define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 345 #define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 346 #define CPU_FTRS_440x6  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
 347             CPU_FTR_INDEXED_DCR)
 348 #define CPU_FTRS_47X    (CPU_FTRS_440x6)
 349 #define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 350             CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
 351             CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
 352             CPU_FTR_DEBUG_LVL_EXC)
 353 #define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 354             CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
 355             CPU_FTR_NOEXECUTE)
 356 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 357             CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
 358             CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 359 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 360             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 361             CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
 362 #define CPU_FTRS_E5500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 363             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 364             CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 365             CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
 366 #define CPU_FTRS_E6500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 367             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 368             CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 369             CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
 370 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 371
 372 /* 64-bit CPUs */
 373 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
 374             CPU_FTR_IABR | CPU_FTR_PPC_LE)
 375 #define CPU_FTRS_RS64   (CPU_FTR_USE_TB | \
 376             CPU_FTR_IABR | \
 377             CPU_FTR_MMCRA | CPU_FTR_CTRL)
 378 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 379             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 380             CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
 381             CPU_FTR_STCX_CHECKS_ADDRESS)
 382 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 383             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
 384             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
 385             CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
 386             CPU_FTR_HVMODE)
 387 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 388             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 389             CPU_FTR_MMCRA | CPU_FTR_SMT | \
 390             CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
 391             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
 392 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 393             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 394             CPU_FTR_MMCRA | CPU_FTR_SMT | \
 395             CPU_FTR_COHERENT_ICACHE | \
 396             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 397             CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
 398             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
 399 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 400             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 401             CPU_FTR_MMCRA | CPU_FTR_SMT | \
 402             CPU_FTR_COHERENT_ICACHE | \
 403             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 404             CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
 405             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 406             CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
 407             CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
 408 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 409             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 410             CPU_FTR_MMCRA | CPU_FTR_SMT | \
 411             CPU_FTR_COHERENT_ICACHE | \
 412             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 413             CPU_FTR_DSCR | CPU_FTR_SAO  | \
 414             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 415             CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
 416             CPU_FTR_DBELL | CPU_FTR_HAS_PPR)
 417 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 418             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 419             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 420             CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
 421             CPU_FTR_UNALIGNED_LD_STD)
 422 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 423             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
 424             CPU_FTR_PURR | CPU_FTR_REAL_LE)
 425 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 426
 427 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
 428                      CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
 429
 430 #ifdef __powerpc64__
 431 #ifdef CONFIG_PPC_BOOK3E
 432 #define CPU_FTRS_POSSIBLE       (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
 433 #else
 434 #define CPU_FTRS_POSSIBLE       \
 435             (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
 436             CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
 437             CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL |         \
 438             CPU_FTRS_PA6T | CPU_FTR_VSX)
 439 #endif
 440 #else
 441 enum {
 442         CPU_FTRS_POSSIBLE =
 443 #if CLASSIC_PPC
 444             CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 445             CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 446             CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 447             CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 448             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 449             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 450             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 451             CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
 452             CPU_FTRS_CLASSIC32 |
 453 #else
 454             CPU_FTRS_GENERIC_32 |
 455 #endif
 456 #ifdef CONFIG_8xx
 457             CPU_FTRS_8XX |
 458 #endif
 459 #ifdef CONFIG_40x
 460             CPU_FTRS_40X |
 461 #endif
 462 #ifdef CONFIG_44x
 463             CPU_FTRS_44X | CPU_FTRS_440x6 |
 464 #endif
 465 #ifdef CONFIG_PPC_47x
 466             CPU_FTRS_47X | CPU_FTR_476_DD2 |
 467 #endif
 468 #ifdef CONFIG_E200
 469             CPU_FTRS_E200 |
 470 #endif
 471 #ifdef CONFIG_E500
 472             CPU_FTRS_E500 | CPU_FTRS_E500_2 |
 473 #endif
 474 #ifdef CONFIG_PPC_E500MC
 475             CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
 476 #endif
 477             0,
 478 };
 479 #endif /* __powerpc64__ */
 480
 481 #ifdef __powerpc64__
 482 #ifdef CONFIG_PPC_BOOK3E
 483 #define CPU_FTRS_ALWAYS         (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
 484 #else
 485 #define CPU_FTRS_ALWAYS         \
 486             (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
 487             CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
 488             CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
 489 #endif
 490 #else
 491 enum {
 492         CPU_FTRS_ALWAYS =
 493 #if CLASSIC_PPC
 494             CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 495             CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 496             CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 497             CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 498             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 499             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 500             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 501             CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
 502             CPU_FTRS_CLASSIC32 &
 503 #else
 504             CPU_FTRS_GENERIC_32 &
 505 #endif
 506 #ifdef CONFIG_8xx
 507             CPU_FTRS_8XX &
 508 #endif
 509 #ifdef CONFIG_40x
 510             CPU_FTRS_40X &
 511 #endif
 512 #ifdef CONFIG_44x
 513             CPU_FTRS_44X & CPU_FTRS_440x6 &
 514 #endif
 515 #ifdef CONFIG_E200
 516             CPU_FTRS_E200 &
 517 #endif
 518 #ifdef CONFIG_E500
 519             CPU_FTRS_E500 & CPU_FTRS_E500_2 &
 520 #endif
 521 #ifdef CONFIG_PPC_E500MC
 522             CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
 523 #endif
 524             ~CPU_FTR_EMB_HV &   /* can be removed at runtime */
 525             CPU_FTRS_POSSIBLE,
 526 };
 527 #endif /* __powerpc64__ */
 528
 529 static inline int cpu_has_feature(unsigned long feature)
 530 {
 531         return (CPU_FTRS_ALWAYS & feature) ||
 532                (CPU_FTRS_POSSIBLE
 533                 & cur_cpu_spec->cpu_features
 534                 & feature);
 535 }
 536
 537 #define HBP_NUM 1
 538
 539 #endif /* !__ASSEMBLY__ */
 540
 541 #endif /* __ASM_POWERPC_CPUTABLE_H */