2 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
3 * Copyright 2001-2012 IBM Corporation.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef _POWERPC_EEH_H
21 #define _POWERPC_EEH_H
24 #include <linux/init.h>
25 #include <linux/list.h>
26 #include <linux/string.h>
27 #include <linux/time.h>
28 #include <linux/atomic.h>
36 /* EEH subsystem flags */
37 #define EEH_ENABLED 0x01 /* EEH enabled */
38 #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */
39 #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */
40 #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */
41 #define EEH_ENABLE_IO_FOR_LOG 0x10 /* Enable IO for log */
44 * Delay for PE reset, all in ms
46 * PCI specification has reset hold time of 100 milliseconds.
47 * We have 250 milliseconds here. The PCI bus settlement time
48 * is specified as 1.5 seconds and we have 1.8 seconds.
50 #define EEH_PE_RST_HOLD_TIME 250
51 #define EEH_PE_RST_SETTLE_TIME 1800
54 * The struct is used to trace PE related EEH functionality.
55 * In theory, there will have one instance of the struct to
56 * be created against particular PE. In nature, PEs corelate
57 * to each other. the struct has to reflect that hierarchy in
58 * order to easily pick up those affected PEs when one particular
61 * Also, one particular PE might be composed of PCI device, PCI
62 * bus and its subordinate components. The struct also need ship
63 * the information. Further more, one particular PE is only meaingful
64 * in the corresponding PHB. Therefore, the root PEs should be created
65 * against existing PHBs in on-to-one fashion.
67 #define EEH_PE_INVALID (1 << 0) /* Invalid */
68 #define EEH_PE_PHB (1 << 1) /* PHB PE */
69 #define EEH_PE_DEVICE (1 << 2) /* Device PE */
70 #define EEH_PE_BUS (1 << 3) /* Bus PE */
72 #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
73 #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
74 #define EEH_PE_RESET (1 << 2) /* PE reset in progress */
76 #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
79 int type; /* PE type: PHB/Bus/Device */
80 int state; /* PE EEH dependent mode */
81 int config_addr; /* Traditional PCI address */
82 int addr; /* PE configuration address */
83 struct pci_controller *phb; /* Associated PHB */
84 struct pci_bus *bus; /* Top PCI bus for bus PE */
85 int check_count; /* Times of ignored error */
86 int freeze_count; /* Times of froze up */
87 struct timeval tstamp; /* Time on first-time freeze */
88 int false_positives; /* Times of reported #ff's */
89 atomic_t pass_dev_cnt; /* Count of passed through devs */
90 struct eeh_pe *parent; /* Parent PE */
91 void *data; /* PE auxillary data */
92 struct list_head child_list; /* Link PE to the child list */
93 struct list_head edevs; /* Link list of EEH devices */
94 struct list_head child; /* Child PEs */
97 #define eeh_pe_for_each_dev(pe, edev, tmp) \
98 list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
100 static inline bool eeh_pe_passed(struct eeh_pe *pe)
102 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
106 * The struct is used to trace EEH state for the associated
107 * PCI device node or PCI device. In future, it might
108 * represent PE as well so that the EEH device to form
109 * another tree except the currently existing tree of PCI
110 * buses and PCI devices
112 #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
113 #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
114 #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
115 #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
116 #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
118 #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
119 #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
120 #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */
123 int mode; /* EEH mode */
124 int class_code; /* Class code of the device */
125 int config_addr; /* Config address */
126 int pe_config_addr; /* PE config address */
127 u32 config_space[16]; /* Saved PCI config space */
128 int pcix_cap; /* Saved PCIx capability */
129 int pcie_cap; /* Saved PCIe capability */
130 int aer_cap; /* Saved AER capability */
131 struct eeh_pe *pe; /* Associated PE */
132 struct list_head list; /* Form link list in the PE */
133 struct pci_controller *phb; /* Associated PHB */
134 struct device_node *dn; /* Associated device node */
135 struct pci_dev *pdev; /* Associated PCI device */
136 struct pci_bus *bus; /* PCI bus for partial hotplug */
139 static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
141 return edev ? edev->dn : NULL;
144 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
146 return edev ? edev->pdev : NULL;
149 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
151 return edev ? edev->pe : NULL;
154 /* Return values from eeh_ops::next_error */
156 EEH_NEXT_ERR_NONE = 0,
158 EEH_NEXT_ERR_FROZEN_PE,
159 EEH_NEXT_ERR_FENCED_PHB,
160 EEH_NEXT_ERR_DEAD_PHB,
161 EEH_NEXT_ERR_DEAD_IOC
165 * The struct is used to trace the registered EEH operation
166 * callback functions. Actually, those operation callback
167 * functions are heavily platform dependent. That means the
168 * platform should register its own EEH operation callback
169 * functions before any EEH further operations.
171 #define EEH_OPT_DISABLE 0 /* EEH disable */
172 #define EEH_OPT_ENABLE 1 /* EEH enable */
173 #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
174 #define EEH_OPT_THAW_DMA 3 /* DMA enable */
175 #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */
176 #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
177 #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
178 #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
179 #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
180 #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
181 #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
182 #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
183 #define EEH_PE_STATE_NORMAL 0 /* Normal state */
184 #define EEH_PE_STATE_RESET 1 /* PE reset asserted */
185 #define EEH_PE_STATE_STOPPED_IO_DMA 2 /* Frozen PE */
186 #define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA, Enabled IO */
187 #define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */
188 #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
189 #define EEH_RESET_HOT 1 /* Hot reset */
190 #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
191 #define EEH_LOG_TEMP 1 /* EEH temporary error log */
192 #define EEH_LOG_PERM 2 /* EEH permanent error log */
197 int (*post_init)(void);
198 void* (*of_probe)(struct device_node *dn, void *flag);
199 int (*dev_probe)(struct pci_dev *dev, void *flag);
200 int (*set_option)(struct eeh_pe *pe, int option);
201 int (*get_pe_addr)(struct eeh_pe *pe);
202 int (*get_state)(struct eeh_pe *pe, int *state);
203 int (*reset)(struct eeh_pe *pe, int option);
204 int (*wait_state)(struct eeh_pe *pe, int max_wait);
205 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
206 int (*configure_bridge)(struct eeh_pe *pe);
207 int (*err_inject)(struct eeh_pe *pe, int type, int func,
208 unsigned long addr, unsigned long mask);
209 int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
210 int (*write_config)(struct device_node *dn, int where, int size, u32 val);
211 int (*next_error)(struct eeh_pe **pe);
212 int (*restore_config)(struct device_node *dn);
215 extern int eeh_subsystem_flags;
216 extern struct eeh_ops *eeh_ops;
217 extern raw_spinlock_t confirm_error_lock;
219 static inline void eeh_add_flag(int flag)
221 eeh_subsystem_flags |= flag;
224 static inline void eeh_clear_flag(int flag)
226 eeh_subsystem_flags &= ~flag;
229 static inline bool eeh_has_flag(int flag)
231 return !!(eeh_subsystem_flags & flag);
234 static inline bool eeh_enabled(void)
236 if (eeh_has_flag(EEH_FORCE_DISABLED) ||
237 !eeh_has_flag(EEH_ENABLED))
243 static inline void eeh_serialize_lock(unsigned long *flags)
245 raw_spin_lock_irqsave(&confirm_error_lock, *flags);
248 static inline void eeh_serialize_unlock(unsigned long flags)
250 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
254 * Max number of EEH freezes allowed before we consider the device
255 * to be permanently disabled.
257 #define EEH_MAX_ALLOWED_FREEZES 5
259 typedef void *(*eeh_traverse_func)(void *data, void *flag);
260 void eeh_set_pe_aux_size(int size);
261 int eeh_phb_pe_create(struct pci_controller *phb);
262 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
263 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
264 int eeh_add_to_parent_pe(struct eeh_dev *edev);
265 int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
266 void eeh_pe_update_time_stamp(struct eeh_pe *pe);
267 void *eeh_pe_traverse(struct eeh_pe *root,
268 eeh_traverse_func fn, void *flag);
269 void *eeh_pe_dev_traverse(struct eeh_pe *root,
270 eeh_traverse_func fn, void *flag);
271 void eeh_pe_restore_bars(struct eeh_pe *pe);
272 const char *eeh_pe_loc_get(struct eeh_pe *pe);
273 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
275 void *eeh_dev_init(struct device_node *dn, void *data);
276 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
278 int __init eeh_ops_register(struct eeh_ops *ops);
279 int __exit eeh_ops_unregister(const char *name);
280 int eeh_check_failure(const volatile void __iomem *token);
281 int eeh_dev_check_failure(struct eeh_dev *edev);
282 void eeh_addr_cache_build(void);
283 void eeh_add_device_early(struct device_node *);
284 void eeh_add_device_tree_early(struct device_node *);
285 void eeh_add_device_late(struct pci_dev *);
286 void eeh_add_device_tree_late(struct pci_bus *);
287 void eeh_add_sysfs_files(struct pci_bus *);
288 void eeh_remove_device(struct pci_dev *);
289 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
290 int eeh_pe_reset_and_recover(struct eeh_pe *pe);
291 int eeh_dev_open(struct pci_dev *pdev);
292 void eeh_dev_release(struct pci_dev *pdev);
293 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
294 int eeh_pe_set_option(struct eeh_pe *pe, int option);
295 int eeh_pe_get_state(struct eeh_pe *pe);
296 int eeh_pe_reset(struct eeh_pe *pe, int option);
297 int eeh_pe_configure(struct eeh_pe *pe);
300 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
302 * If this macro yields TRUE, the caller relays to eeh_check_failure()
303 * which does further tests out of line.
305 #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
308 * Reads from a device which has been isolated by EEH will return
309 * all 1s. This macro gives an all-1s value of the given size (in
310 * bytes: 1, 2, or 4) for comparing with the result of a read.
312 #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
314 #else /* !CONFIG_EEH */
316 static inline bool eeh_enabled(void)
321 static inline int eeh_init(void)
326 static inline void *eeh_dev_init(struct device_node *dn, void *data)
331 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
333 static inline int eeh_check_failure(const volatile void __iomem *token)
338 #define eeh_dev_check_failure(x) (0)
340 static inline void eeh_addr_cache_build(void) { }
342 static inline void eeh_add_device_early(struct device_node *dn) { }
344 static inline void eeh_add_device_tree_early(struct device_node *dn) { }
346 static inline void eeh_add_device_late(struct pci_dev *dev) { }
348 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
350 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
352 static inline void eeh_remove_device(struct pci_dev *dev) { }
354 #define EEH_POSSIBLE_ERROR(val, type) (0)
355 #define EEH_IO_ERROR_VALUE(size) (-1UL)
356 #endif /* CONFIG_EEH */
360 * MMIO read/write operations with EEH support.
362 static inline u8 eeh_readb(const volatile void __iomem *addr)
365 if (EEH_POSSIBLE_ERROR(val, u8))
366 eeh_check_failure(addr);
370 static inline u16 eeh_readw(const volatile void __iomem *addr)
372 u16 val = in_le16(addr);
373 if (EEH_POSSIBLE_ERROR(val, u16))
374 eeh_check_failure(addr);
378 static inline u32 eeh_readl(const volatile void __iomem *addr)
380 u32 val = in_le32(addr);
381 if (EEH_POSSIBLE_ERROR(val, u32))
382 eeh_check_failure(addr);
386 static inline u64 eeh_readq(const volatile void __iomem *addr)
388 u64 val = in_le64(addr);
389 if (EEH_POSSIBLE_ERROR(val, u64))
390 eeh_check_failure(addr);
394 static inline u16 eeh_readw_be(const volatile void __iomem *addr)
396 u16 val = in_be16(addr);
397 if (EEH_POSSIBLE_ERROR(val, u16))
398 eeh_check_failure(addr);
402 static inline u32 eeh_readl_be(const volatile void __iomem *addr)
404 u32 val = in_be32(addr);
405 if (EEH_POSSIBLE_ERROR(val, u32))
406 eeh_check_failure(addr);
410 static inline u64 eeh_readq_be(const volatile void __iomem *addr)
412 u64 val = in_be64(addr);
413 if (EEH_POSSIBLE_ERROR(val, u64))
414 eeh_check_failure(addr);
418 static inline void eeh_memcpy_fromio(void *dest, const
419 volatile void __iomem *src,
422 _memcpy_fromio(dest, src, n);
424 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes
425 * were copied. Check all four bytes.
427 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
428 eeh_check_failure(src);
431 /* in-string eeh macros */
432 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
435 _insb(addr, buf, ns);
436 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
437 eeh_check_failure(addr);
440 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
443 _insw(addr, buf, ns);
444 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
445 eeh_check_failure(addr);
448 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
451 _insl(addr, buf, nl);
452 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
453 eeh_check_failure(addr);
456 #endif /* CONFIG_PPC64 */
457 #endif /* __KERNEL__ */
458 #endif /* _POWERPC_EEH_H */