1 #ifndef _ASM_POWERPC_MMU_HASH64_H_
2 #define _ASM_POWERPC_MMU_HASH64_H_
4 * PowerPC64 memory management structures
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #include <asm/asm-compat.h>
19 * This is necessary to get the definition of PGTABLE_RANGE which we
20 * need for various slices related matters. Note that this isn't the
21 * complete pgtable.h but only a portion of it.
23 #include <asm/pgtable-ppc64.h>
30 #define STE_ESID_V 0x80
31 #define STE_ESID_KS 0x20
32 #define STE_ESID_KP 0x10
33 #define STE_ESID_N 0x08
35 #define STE_VSID_SHIFT 12
37 /* Location of cpu0's segment table */
38 #define STAB0_PAGE 0x8
39 #define STAB0_OFFSET (STAB0_PAGE << 12)
40 #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
43 extern char initial_stab[];
44 #endif /* ! __ASSEMBLY */
50 #define SLB_NUM_BOLTED 3
51 #define SLB_CACHE_ENTRIES 8
52 #define SLB_MIN_SIZE 32
54 /* Bits in the SLB ESID word */
55 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
57 /* Bits in the SLB VSID word */
58 #define SLB_VSID_SHIFT 12
59 #define SLB_VSID_SHIFT_1T 24
60 #define SLB_VSID_SSIZE_SHIFT 62
61 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
62 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
63 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
64 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
65 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
66 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
67 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
68 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
69 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
70 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
71 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
72 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
73 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
74 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
76 #define SLB_VSID_KERNEL (SLB_VSID_KP)
77 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
79 #define SLBIE_C (0x08000000)
80 #define SLBIE_SSIZE_SHIFT 25
86 #define HPTES_PER_GROUP 8
88 #define HPTE_V_SSIZE_SHIFT 62
89 #define HPTE_V_AVPN_SHIFT 7
90 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
91 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
92 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
93 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
94 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
95 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
96 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
97 #define HPTE_V_VALID ASM_CONST(0x0000000000000001)
99 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
100 #define HPTE_R_TS ASM_CONST(0x4000000000000000)
101 #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
102 #define HPTE_R_RPN_SHIFT 12
103 #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
104 #define HPTE_R_PP ASM_CONST(0x0000000000000003)
105 #define HPTE_R_N ASM_CONST(0x0000000000000004)
106 #define HPTE_R_G ASM_CONST(0x0000000000000008)
107 #define HPTE_R_M ASM_CONST(0x0000000000000010)
108 #define HPTE_R_I ASM_CONST(0x0000000000000020)
109 #define HPTE_R_W ASM_CONST(0x0000000000000040)
110 #define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
111 #define HPTE_R_C ASM_CONST(0x0000000000000080)
112 #define HPTE_R_R ASM_CONST(0x0000000000000100)
113 #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
115 #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
116 #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
118 /* Values for PP (assumes Ks=0, Kp=1) */
119 #define PP_RWXX 0 /* Supervisor read/write, User none */
120 #define PP_RWRX 1 /* Supervisor read/write, User read */
121 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
122 #define PP_RXRX 3 /* Supervisor read, User read */
123 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
125 /* Fields for tlbiel instruction in architecture 2.06 */
126 #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
127 #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
128 #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
129 #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
130 #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
131 #define TLBIEL_INVAL_SET_SHIFT 12
133 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
142 extern struct hash_pte *htab_address;
143 extern unsigned long htab_size_bytes;
144 extern unsigned long htab_hash_mask;
147 * Page size definition
149 * shift : is the "PAGE_SHIFT" value for that page size
150 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
151 * directly to a slbmte "vsid" value
152 * penc : is the HPTE encoding mask for the "LP" field:
157 unsigned int shift; /* number of bits */
158 unsigned int penc; /* HPTE encoding */
159 unsigned int tlbiel; /* tlbiel supported for that page size */
160 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
161 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
163 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
165 static inline int shift_to_mmu_psize(unsigned int shift)
169 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
170 if (mmu_psize_defs[psize].shift == shift)
175 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
177 if (mmu_psize_defs[mmu_psize].shift)
178 return mmu_psize_defs[mmu_psize].shift;
182 #endif /* __ASSEMBLY__ */
186 * These are the values used by hardware in the B field of
187 * SLB entries and the first dword of MMU hashtable entries.
188 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
190 #define MMU_SEGSIZE_256M 0
191 #define MMU_SEGSIZE_1T 1
194 * encode page number shift.
195 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
196 * 12 bits. This enable us to address upto 76 bit va.
197 * For hpt hash from a va we can ignore the page size bits of va and for
198 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
199 * we work in all cases including 4k page size.
205 static inline int segment_shift(int ssize)
207 if (ssize == MMU_SEGSIZE_256M)
213 * The current system page and segment sizes
215 extern int mmu_linear_psize;
216 extern int mmu_virtual_psize;
217 extern int mmu_vmalloc_psize;
218 extern int mmu_vmemmap_psize;
219 extern int mmu_io_psize;
220 extern int mmu_kernel_ssize;
221 extern int mmu_highuser_ssize;
222 extern u16 mmu_slb_size;
223 extern unsigned long tce_alloc_start, tce_alloc_end;
226 * If the processor supports 64k normal pages but not 64k cache
227 * inhibited pages, we have to be prepared to switch processes
228 * to use 4k pages when they create cache-inhibited mappings.
229 * If this is the case, mmu_ci_restrictions will be set to 1.
231 extern int mmu_ci_restrictions;
234 * This computes the AVPN and B fields of the first dword of a HPTE,
235 * for use when we want to match an existing PTE. The bottom 7 bits
236 * of the returned value are zero.
238 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
243 * The AVA field omits the low-order 23 bits of the 78 bits VA.
244 * These bits are not needed in the PTE, because the
245 * low-order b of these bits are part of the byte offset
246 * into the virtual page and, if b < 23, the high-order
247 * 23-b of these bits are always used in selecting the
248 * PTEGs to be searched
250 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
251 v <<= HPTE_V_AVPN_SHIFT;
252 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
257 * This function sets the AVPN and L fields of the HPTE appropriately
260 static inline unsigned long hpte_encode_v(unsigned long vpn,
261 int psize, int ssize)
264 v = hpte_encode_avpn(vpn, psize, ssize);
265 if (psize != MMU_PAGE_4K)
271 * This function sets the ARPN, and LP fields of the HPTE appropriately
272 * for the page size. We assume the pa is already "clean" that is properly
273 * aligned for the requested page size
275 static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
279 /* A 4K page needs no special encoding */
280 if (psize == MMU_PAGE_4K)
281 return pa & HPTE_R_RPN;
283 unsigned int penc = mmu_psize_defs[psize].penc;
284 unsigned int shift = mmu_psize_defs[psize].shift;
285 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
291 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
293 static inline unsigned long hpt_vpn(unsigned long ea,
294 unsigned long vsid, int ssize)
297 int s_shift = segment_shift(ssize);
299 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
300 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
304 * This hashes a virtual address
306 static inline unsigned long hpt_hash(unsigned long vpn,
307 unsigned int shift, int ssize)
310 unsigned long hash, vsid;
312 /* VPN_SHIFT can be atmost 12 */
313 if (ssize == MMU_SEGSIZE_256M) {
314 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
315 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
316 ((vpn & mask) >> (shift - VPN_SHIFT));
318 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
319 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
320 hash = vsid ^ (vsid << 25) ^
321 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
323 return hash & 0x7fffffffffUL;
326 extern int __hash_page_4K(unsigned long ea, unsigned long access,
327 unsigned long vsid, pte_t *ptep, unsigned long trap,
328 unsigned int local, int ssize, int subpage_prot);
329 extern int __hash_page_64K(unsigned long ea, unsigned long access,
330 unsigned long vsid, pte_t *ptep, unsigned long trap,
331 unsigned int local, int ssize);
333 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
334 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
335 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
336 pte_t *ptep, unsigned long trap, int local, int ssize,
337 unsigned int shift, unsigned int mmu_psize);
338 extern void hash_failure_debug(unsigned long ea, unsigned long access,
339 unsigned long vsid, unsigned long trap,
340 int ssize, int psize, unsigned long pte);
341 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
342 unsigned long pstart, unsigned long prot,
343 int psize, int ssize);
344 extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
345 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
347 extern void hpte_init_native(void);
348 extern void hpte_init_lpar(void);
349 extern void hpte_init_beat(void);
350 extern void hpte_init_beat_v3(void);
352 extern void stabs_alloc(void);
353 extern void slb_initialize(void);
354 extern void slb_flush_and_rebolt(void);
355 extern void stab_initialize(unsigned long stab);
357 extern void slb_vmalloc_update(void);
358 extern void slb_set_size(u16 size);
359 #endif /* __ASSEMBLY__ */
362 * VSID allocation (256MB segment)
364 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
365 * from mmu context id and effective segment id of the address.
367 * For user processes max context id is limited to ((1ul << 19) - 5)
368 * for kernel space, we use the top 4 context ids to map address as below
369 * NOTE: each context only support 64TB now.
370 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
371 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
372 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
373 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
375 * The proto-VSIDs are then scrambled into real VSIDs with the
376 * multiplicative hash:
378 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
380 * VSID_MULTIPLIER is prime, so in particular it is
381 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
382 * Because the modulus is 2^n-1 we can compute it efficiently without
383 * a divide or extra multiply (see below). The scramble function gives
384 * robust scattering in the hash table (at least based on some initial
387 * We also consider VSID 0 special. We use VSID 0 for slb entries mapping
388 * bad address. This enables us to consolidate bad address handling in
391 * We also need to avoid the last segment of the last context, because that
392 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
393 * because of the modulo operation in vsid scramble. But the vmemmap
394 * (which is what uses region 0xf) will never be close to 64TB in size
395 * (it's 56 bytes per page of system memory).
398 #define CONTEXT_BITS 19
400 #define ESID_BITS_1T 6
404 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
405 * available for user + kernel mapping. The top 4 contexts are used for
406 * kernel mapping. Each segment contains 2^28 bytes. Each
407 * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
408 * (19 == 37 + 28 - 46).
410 #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5)
413 * This should be computed such that protovosid * vsid_mulitplier
414 * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
416 #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
417 #define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS)
418 #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
420 #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
421 #define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T)
422 #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
425 #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
428 * This macro generates asm code to compute the VSID scramble
429 * function. Used in slb_allocate() and do_stab_bolted. The function
430 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
432 * rt = register continaing the proto-VSID and into which the
433 * VSID will be stored
434 * rx = scratch register (clobbered)
436 * - rt and rx must be different registers
437 * - The answer will end up in the low VSID_BITS bits of rt. The higher
438 * bits may contain other garbage, so you may need to mask the
441 #define ASM_VSID_SCRAMBLE(rt, rx, size) \
442 lis rx,VSID_MULTIPLIER_##size@h; \
443 ori rx,rx,VSID_MULTIPLIER_##size@l; \
444 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
446 srdi rx,rt,VSID_BITS_##size; \
447 clrldi rt,rt,(64-VSID_BITS_##size); \
448 add rt,rt,rx; /* add high and low bits */ \
449 /* NOTE: explanation based on VSID_BITS_##size = 36 \
450 * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
451 * 2^36-1+2^28-1. That in particular means that if r3 >= \
452 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
453 * the bit clear, r3 already has the answer we want, if it \
454 * doesn't, the answer is the low 36 bits of r3+1. So in all \
455 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
457 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
460 /* 4 bits per slice and we have one slice per 1TB */
461 #define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
465 #ifdef CONFIG_PPC_SUBPAGE_PROT
467 * For the sub-page protection option, we extend the PGD with one of
468 * these. Basically we have a 3-level tree, with the top level being
469 * the protptrs array. To optimize speed and memory consumption when
470 * only addresses < 4GB are being protected, pointers to the first
471 * four pages of sub-page protection words are stored in the low_prot
473 * Each page of sub-page protection words protects 1GB (4 bytes
474 * protects 64k). For the 3-level tree, each page of pointers then
477 struct subpage_prot_table {
478 unsigned long maxaddr; /* only addresses < this are protected */
479 unsigned int **protptrs[2];
480 unsigned int *low_prot[4];
483 #define SBP_L1_BITS (PAGE_SHIFT - 2)
484 #define SBP_L2_BITS (PAGE_SHIFT - 3)
485 #define SBP_L1_COUNT (1 << SBP_L1_BITS)
486 #define SBP_L2_COUNT (1 << SBP_L2_BITS)
487 #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
488 #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
490 extern void subpage_prot_free(struct mm_struct *mm);
491 extern void subpage_prot_init_new_context(struct mm_struct *mm);
493 static inline void subpage_prot_free(struct mm_struct *mm) {}
494 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
495 #endif /* CONFIG_PPC_SUBPAGE_PROT */
497 typedef unsigned long mm_context_id_t;
502 u16 user_psize; /* page size index */
504 #ifdef CONFIG_PPC_MM_SLICES
505 u64 low_slices_psize; /* SLB page size encodings */
506 unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
508 u16 sllp; /* SLB page size encoding */
510 unsigned long vdso_base;
511 #ifdef CONFIG_PPC_SUBPAGE_PROT
512 struct subpage_prot_table spt;
513 #endif /* CONFIG_PPC_SUBPAGE_PROT */
514 #ifdef CONFIG_PPC_ICSWX
515 struct spinlock *cop_lockp; /* guard acop and cop_pid */
516 unsigned long acop; /* mask of enabled coprocessor types */
517 unsigned int cop_pid; /* pid value used with coprocessors */
518 #endif /* CONFIG_PPC_ICSWX */
519 #ifdef CONFIG_PPC_64K_PAGES
520 /* for 4K PTE fragment support */
528 * The code below is equivalent to this function for arguments
529 * < 2^VSID_BITS, which is all this should ever be called
530 * with. However gcc is not clever enough to compute the
531 * modulus (2^n-1) without a second multiply.
533 #define vsid_scramble(protovsid, size) \
534 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
537 #define vsid_scramble(protovsid, size) \
540 x = (protovsid) * VSID_MULTIPLIER_##size; \
541 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
542 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
546 /* Returns the segment size indicator for a user address */
547 static inline int user_segment_size(unsigned long addr)
549 /* Use 1T segments if possible for addresses >= 1T */
550 if (addr >= (1UL << SID_SHIFT_1T))
551 return mmu_highuser_ssize;
552 return MMU_SEGSIZE_256M;
555 static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
559 * Bad address. We return VSID 0 for that
561 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
564 if (ssize == MMU_SEGSIZE_256M)
565 return vsid_scramble((context << ESID_BITS)
566 | (ea >> SID_SHIFT), 256M);
567 return vsid_scramble((context << ESID_BITS_1T)
568 | (ea >> SID_SHIFT_1T), 1T);
572 * This is only valid for addresses >= PAGE_OFFSET
574 * For kernel space, we use the top 4 context ids to map address as below
575 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
576 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
577 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
578 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
580 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
582 unsigned long context;
585 * kernel take the top 4 context from the available range
587 context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1;
588 return get_vsid(context, ea, ssize);
590 #endif /* __ASSEMBLY__ */
592 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */