1 #ifndef _ASM_POWERPC_MMU_HASH64_H_
2 #define _ASM_POWERPC_MMU_HASH64_H_
4 * PowerPC64 memory management structures
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #include <asm/asm-compat.h>
19 * This is necessary to get the definition of PGTABLE_RANGE which we
20 * need for various slices related matters. Note that this isn't the
21 * complete pgtable.h but only a portion of it.
23 #include <asm/pgtable-ppc64.h>
29 #define STE_ESID_V 0x80
30 #define STE_ESID_KS 0x20
31 #define STE_ESID_KP 0x10
32 #define STE_ESID_N 0x08
34 #define STE_VSID_SHIFT 12
36 /* Location of cpu0's segment table */
37 #define STAB0_PAGE 0x8
38 #define STAB0_OFFSET (STAB0_PAGE << 12)
39 #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
42 extern char initial_stab[];
43 #endif /* ! __ASSEMBLY */
49 #define SLB_NUM_BOLTED 3
50 #define SLB_CACHE_ENTRIES 8
51 #define SLB_MIN_SIZE 32
53 /* Bits in the SLB ESID word */
54 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
56 /* Bits in the SLB VSID word */
57 #define SLB_VSID_SHIFT 12
58 #define SLB_VSID_SHIFT_1T 24
59 #define SLB_VSID_SSIZE_SHIFT 62
60 #define SLB_VSID_B ASM_CONST(0xc000000000000000)
61 #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
62 #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
63 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
64 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
65 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
66 #define SLB_VSID_L ASM_CONST(0x0000000000000100)
67 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
68 #define SLB_VSID_LP ASM_CONST(0x0000000000000030)
69 #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
70 #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
71 #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
72 #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
73 #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
75 #define SLB_VSID_KERNEL (SLB_VSID_KP)
76 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
78 #define SLBIE_C (0x08000000)
79 #define SLBIE_SSIZE_SHIFT 25
85 #define HPTES_PER_GROUP 8
87 #define HPTE_V_SSIZE_SHIFT 62
88 #define HPTE_V_AVPN_SHIFT 7
89 #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
90 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
91 #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
92 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
93 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
94 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
95 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
96 #define HPTE_V_VALID ASM_CONST(0x0000000000000001)
98 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
99 #define HPTE_R_TS ASM_CONST(0x4000000000000000)
100 #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
101 #define HPTE_R_RPN_SHIFT 12
102 #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
103 #define HPTE_R_PP ASM_CONST(0x0000000000000003)
104 #define HPTE_R_N ASM_CONST(0x0000000000000004)
105 #define HPTE_R_G ASM_CONST(0x0000000000000008)
106 #define HPTE_R_M ASM_CONST(0x0000000000000010)
107 #define HPTE_R_I ASM_CONST(0x0000000000000020)
108 #define HPTE_R_W ASM_CONST(0x0000000000000040)
109 #define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
110 #define HPTE_R_C ASM_CONST(0x0000000000000080)
111 #define HPTE_R_R ASM_CONST(0x0000000000000100)
112 #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
114 #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
115 #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
117 /* Values for PP (assumes Ks=0, Kp=1) */
118 #define PP_RWXX 0 /* Supervisor read/write, User none */
119 #define PP_RWRX 1 /* Supervisor read/write, User read */
120 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
121 #define PP_RXRX 3 /* Supervisor read, User read */
122 #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
124 /* Fields for tlbiel instruction in architecture 2.06 */
125 #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
126 #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
127 #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
128 #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
129 #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
130 #define TLBIEL_INVAL_SET_SHIFT 12
132 #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
141 extern struct hash_pte *htab_address;
142 extern unsigned long htab_size_bytes;
143 extern unsigned long htab_hash_mask;
146 * Page size definition
148 * shift : is the "PAGE_SHIFT" value for that page size
149 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
150 * directly to a slbmte "vsid" value
151 * penc : is the HPTE encoding mask for the "LP" field:
156 unsigned int shift; /* number of bits */
157 unsigned int penc; /* HPTE encoding */
158 unsigned int tlbiel; /* tlbiel supported for that page size */
159 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
160 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
163 #endif /* __ASSEMBLY__ */
167 * These are the values used by hardware in the B field of
168 * SLB entries and the first dword of MMU hashtable entries.
169 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
171 #define MMU_SEGSIZE_256M 0
172 #define MMU_SEGSIZE_1T 1
175 * encode page number shift.
176 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
177 * 12 bits. This enable us to address upto 76 bit va.
178 * For hpt hash from a va we can ignore the page size bits of va and for
179 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
180 * we work in all cases including 4k page size.
186 static inline int segment_shift(int ssize)
188 if (ssize == MMU_SEGSIZE_256M)
194 * The current system page and segment sizes
196 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
197 extern int mmu_linear_psize;
198 extern int mmu_virtual_psize;
199 extern int mmu_vmalloc_psize;
200 extern int mmu_vmemmap_psize;
201 extern int mmu_io_psize;
202 extern int mmu_kernel_ssize;
203 extern int mmu_highuser_ssize;
204 extern u16 mmu_slb_size;
205 extern unsigned long tce_alloc_start, tce_alloc_end;
208 * If the processor supports 64k normal pages but not 64k cache
209 * inhibited pages, we have to be prepared to switch processes
210 * to use 4k pages when they create cache-inhibited mappings.
211 * If this is the case, mmu_ci_restrictions will be set to 1.
213 extern int mmu_ci_restrictions;
216 * This computes the AVPN and B fields of the first dword of a HPTE,
217 * for use when we want to match an existing PTE. The bottom 7 bits
218 * of the returned value are zero.
220 static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
225 * The AVA field omits the low-order 23 bits of the 78 bits VA.
226 * These bits are not needed in the PTE, because the
227 * low-order b of these bits are part of the byte offset
228 * into the virtual page and, if b < 23, the high-order
229 * 23-b of these bits are always used in selecting the
230 * PTEGs to be searched
232 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
233 v <<= HPTE_V_AVPN_SHIFT;
234 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
239 * This function sets the AVPN and L fields of the HPTE appropriately
242 static inline unsigned long hpte_encode_v(unsigned long vpn,
243 int psize, int ssize)
246 v = hpte_encode_avpn(vpn, psize, ssize);
247 if (psize != MMU_PAGE_4K)
253 * This function sets the ARPN, and LP fields of the HPTE appropriately
254 * for the page size. We assume the pa is already "clean" that is properly
255 * aligned for the requested page size
257 static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
261 /* A 4K page needs no special encoding */
262 if (psize == MMU_PAGE_4K)
263 return pa & HPTE_R_RPN;
265 unsigned int penc = mmu_psize_defs[psize].penc;
266 unsigned int shift = mmu_psize_defs[psize].shift;
267 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
273 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
275 static inline unsigned long hpt_vpn(unsigned long ea,
276 unsigned long vsid, int ssize)
279 int s_shift = segment_shift(ssize);
281 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
282 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
286 * This hashes a virtual address
288 static inline unsigned long hpt_hash(unsigned long vpn,
289 unsigned int shift, int ssize)
292 unsigned long hash, vsid;
294 /* VPN_SHIFT can be atmost 12 */
295 if (ssize == MMU_SEGSIZE_256M) {
296 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
297 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
298 ((vpn & mask) >> (shift - VPN_SHIFT));
300 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
301 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
302 hash = vsid ^ (vsid << 25) ^
303 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
305 return hash & 0x7fffffffffUL;
308 extern int __hash_page_4K(unsigned long ea, unsigned long access,
309 unsigned long vsid, pte_t *ptep, unsigned long trap,
310 unsigned int local, int ssize, int subpage_prot);
311 extern int __hash_page_64K(unsigned long ea, unsigned long access,
312 unsigned long vsid, pte_t *ptep, unsigned long trap,
313 unsigned int local, int ssize);
315 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
316 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
317 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
318 pte_t *ptep, unsigned long trap, int local, int ssize,
319 unsigned int shift, unsigned int mmu_psize);
320 extern void hash_failure_debug(unsigned long ea, unsigned long access,
321 unsigned long vsid, unsigned long trap,
322 int ssize, int psize, unsigned long pte);
323 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
324 unsigned long pstart, unsigned long prot,
325 int psize, int ssize);
326 extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
327 extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
329 extern void hpte_init_native(void);
330 extern void hpte_init_lpar(void);
331 extern void hpte_init_beat(void);
332 extern void hpte_init_beat_v3(void);
334 extern void stabs_alloc(void);
335 extern void slb_initialize(void);
336 extern void slb_flush_and_rebolt(void);
337 extern void stab_initialize(unsigned long stab);
339 extern void slb_vmalloc_update(void);
340 extern void slb_set_size(u16 size);
341 #endif /* __ASSEMBLY__ */
344 * VSID allocation (256MB segment)
346 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
347 * from mmu context id and effective segment id of the address.
349 * For user processes max context id is limited to ((1ul << 19) - 5)
350 * for kernel space, we use the top 4 context ids to map address as below
351 * NOTE: each context only support 64TB now.
352 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
353 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
354 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
355 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
357 * The proto-VSIDs are then scrambled into real VSIDs with the
358 * multiplicative hash:
360 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
362 * VSID_MULTIPLIER is prime, so in particular it is
363 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
364 * Because the modulus is 2^n-1 we can compute it efficiently without
365 * a divide or extra multiply (see below). The scramble function gives
366 * robust scattering in the hash table (at least based on some initial
369 * We also consider VSID 0 special. We use VSID 0 for slb entries mapping
370 * bad address. This enables us to consolidate bad address handling in
373 * We also need to avoid the last segment of the last context, because that
374 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
375 * because of the modulo operation in vsid scramble. But the vmemmap
376 * (which is what uses region 0xf) will never be close to 64TB in size
377 * (it's 56 bytes per page of system memory).
380 #define CONTEXT_BITS 19
382 #define ESID_BITS_1T 6
386 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
387 * available for user + kernel mapping. The top 4 contexts are used for
388 * kernel mapping. Each segment contains 2^28 bytes. Each
389 * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
390 * (19 == 37 + 28 - 46).
392 #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5)
395 * This should be computed such that protovosid * vsid_mulitplier
396 * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
398 #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
399 #define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS)
400 #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
402 #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
403 #define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T)
404 #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
407 #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
410 * This macro generates asm code to compute the VSID scramble
411 * function. Used in slb_allocate() and do_stab_bolted. The function
412 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
414 * rt = register continaing the proto-VSID and into which the
415 * VSID will be stored
416 * rx = scratch register (clobbered)
418 * - rt and rx must be different registers
419 * - The answer will end up in the low VSID_BITS bits of rt. The higher
420 * bits may contain other garbage, so you may need to mask the
423 #define ASM_VSID_SCRAMBLE(rt, rx, size) \
424 lis rx,VSID_MULTIPLIER_##size@h; \
425 ori rx,rx,VSID_MULTIPLIER_##size@l; \
426 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
428 srdi rx,rt,VSID_BITS_##size; \
429 clrldi rt,rt,(64-VSID_BITS_##size); \
430 add rt,rt,rx; /* add high and low bits */ \
431 /* NOTE: explanation based on VSID_BITS_##size = 36 \
432 * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
433 * 2^36-1+2^28-1. That in particular means that if r3 >= \
434 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
435 * the bit clear, r3 already has the answer we want, if it \
436 * doesn't, the answer is the low 36 bits of r3+1. So in all \
437 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
439 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
442 /* 4 bits per slice and we have one slice per 1TB */
443 #define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
447 #ifdef CONFIG_PPC_SUBPAGE_PROT
449 * For the sub-page protection option, we extend the PGD with one of
450 * these. Basically we have a 3-level tree, with the top level being
451 * the protptrs array. To optimize speed and memory consumption when
452 * only addresses < 4GB are being protected, pointers to the first
453 * four pages of sub-page protection words are stored in the low_prot
455 * Each page of sub-page protection words protects 1GB (4 bytes
456 * protects 64k). For the 3-level tree, each page of pointers then
459 struct subpage_prot_table {
460 unsigned long maxaddr; /* only addresses < this are protected */
461 unsigned int **protptrs[2];
462 unsigned int *low_prot[4];
465 #define SBP_L1_BITS (PAGE_SHIFT - 2)
466 #define SBP_L2_BITS (PAGE_SHIFT - 3)
467 #define SBP_L1_COUNT (1 << SBP_L1_BITS)
468 #define SBP_L2_COUNT (1 << SBP_L2_BITS)
469 #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
470 #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
472 extern void subpage_prot_free(struct mm_struct *mm);
473 extern void subpage_prot_init_new_context(struct mm_struct *mm);
475 static inline void subpage_prot_free(struct mm_struct *mm) {}
476 static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
477 #endif /* CONFIG_PPC_SUBPAGE_PROT */
479 typedef unsigned long mm_context_id_t;
484 u16 user_psize; /* page size index */
486 #ifdef CONFIG_PPC_MM_SLICES
487 u64 low_slices_psize; /* SLB page size encodings */
488 unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
490 u16 sllp; /* SLB page size encoding */
492 unsigned long vdso_base;
493 #ifdef CONFIG_PPC_SUBPAGE_PROT
494 struct subpage_prot_table spt;
495 #endif /* CONFIG_PPC_SUBPAGE_PROT */
496 #ifdef CONFIG_PPC_ICSWX
497 struct spinlock *cop_lockp; /* guard acop and cop_pid */
498 unsigned long acop; /* mask of enabled coprocessor types */
499 unsigned int cop_pid; /* pid value used with coprocessors */
500 #endif /* CONFIG_PPC_ICSWX */
506 * The code below is equivalent to this function for arguments
507 * < 2^VSID_BITS, which is all this should ever be called
508 * with. However gcc is not clever enough to compute the
509 * modulus (2^n-1) without a second multiply.
511 #define vsid_scramble(protovsid, size) \
512 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
515 #define vsid_scramble(protovsid, size) \
518 x = (protovsid) * VSID_MULTIPLIER_##size; \
519 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
520 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
524 /* Returns the segment size indicator for a user address */
525 static inline int user_segment_size(unsigned long addr)
527 /* Use 1T segments if possible for addresses >= 1T */
528 if (addr >= (1UL << SID_SHIFT_1T))
529 return mmu_highuser_ssize;
530 return MMU_SEGSIZE_256M;
533 static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
537 * Bad address. We return VSID 0 for that
539 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
542 if (ssize == MMU_SEGSIZE_256M)
543 return vsid_scramble((context << ESID_BITS)
544 | (ea >> SID_SHIFT), 256M);
545 return vsid_scramble((context << ESID_BITS_1T)
546 | (ea >> SID_SHIFT_1T), 1T);
550 * This is only valid for addresses >= PAGE_OFFSET
552 * For kernel space, we use the top 4 context ids to map address as below
553 * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
554 * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
555 * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
556 * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
558 static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
560 unsigned long context;
563 * kernel take the top 4 context from the available range
565 context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1;
566 return get_vsid(context, ea, ssize);
568 #endif /* __ASSEMBLY__ */
570 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */