arch/powerpc/include/asm/opal-api.h

   1 /*
   2  * OPAL API definitions.
   3  *
   4  * Copyright 2011-2015 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_API_H
  13 #define __OPAL_API_H
  14
  15 /****** OPAL APIs ******/
  16
  17 /* Return codes */
  18 #define OPAL_SUCCESS            0
  19 #define OPAL_PARAMETER          -1
  20 #define OPAL_BUSY               -2
  21 #define OPAL_PARTIAL            -3
  22 #define OPAL_CONSTRAINED        -4
  23 #define OPAL_CLOSED             -5
  24 #define OPAL_HARDWARE           -6
  25 #define OPAL_UNSUPPORTED        -7
  26 #define OPAL_PERMISSION         -8
  27 #define OPAL_NO_MEM             -9
  28 #define OPAL_RESOURCE           -10
  29 #define OPAL_INTERNAL_ERROR     -11
  30 #define OPAL_BUSY_EVENT         -12
  31 #define OPAL_HARDWARE_FROZEN    -13
  32 #define OPAL_WRONG_STATE        -14
  33 #define OPAL_ASYNC_COMPLETION   -15
  34 #define OPAL_EMPTY              -16
  35 #define OPAL_I2C_TIMEOUT        -17
  36 #define OPAL_I2C_INVALID_CMD    -18
  37 #define OPAL_I2C_LBUS_PARITY    -19
  38 #define OPAL_I2C_BKEND_OVERRUN  -20
  39 #define OPAL_I2C_BKEND_ACCESS   -21
  40 #define OPAL_I2C_ARBT_LOST      -22
  41 #define OPAL_I2C_NACK_RCVD      -23
  42 #define OPAL_I2C_STOP_ERR       -24
  43
  44 /* API Tokens (in r0) */
  45 #define OPAL_INVALID_CALL                      -1
  46 #define OPAL_TEST                               0
  47 #define OPAL_CONSOLE_WRITE                      1
  48 #define OPAL_CONSOLE_READ                       2
  49 #define OPAL_RTC_READ                           3
  50 #define OPAL_RTC_WRITE                          4
  51 #define OPAL_CEC_POWER_DOWN                     5
  52 #define OPAL_CEC_REBOOT                         6
  53 #define OPAL_READ_NVRAM                         7
  54 #define OPAL_WRITE_NVRAM                        8
  55 #define OPAL_HANDLE_INTERRUPT                   9
  56 #define OPAL_POLL_EVENTS                        10
  57 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  58 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  59 #define OPAL_PCI_CONFIG_READ_BYTE               13
  60 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  61 #define OPAL_PCI_CONFIG_READ_WORD               15
  62 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  63 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  64 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  65 #define OPAL_SET_XIVE                           19
  66 #define OPAL_GET_XIVE                           20
  67 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  68 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  69 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  70 #define OPAL_PCI_SHPC                           24
  71 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  72 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  73 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  74 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  75 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  76 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  77 #define OPAL_PCI_SET_PE                         31
  78 #define OPAL_PCI_SET_PELTV                      32
  79 #define OPAL_PCI_SET_MVE                        33
  80 #define OPAL_PCI_SET_MVE_ENABLE                 34
  81 #define OPAL_PCI_GET_XIVE_REISSUE               35
  82 #define OPAL_PCI_SET_XIVE_REISSUE               36
  83 #define OPAL_PCI_SET_XIVE_PE                    37
  84 #define OPAL_GET_XIVE_SOURCE                    38
  85 #define OPAL_GET_MSI_32                         39
  86 #define OPAL_GET_MSI_64                         40
  87 #define OPAL_START_CPU                          41
  88 #define OPAL_QUERY_CPU_STATUS                   42
  89 #define OPAL_WRITE_OPPANEL                      43 /* unimplemented */
  90 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
  91 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
  92 #define OPAL_PCI_RESET                          49
  93 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
  94 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
  95 #define OPAL_PCI_FENCE_PHB                      52
  96 #define OPAL_PCI_REINIT                         53
  97 #define OPAL_PCI_MASK_PE_ERROR                  54
  98 #define OPAL_SET_SLOT_LED_STATUS                55
  99 #define OPAL_GET_EPOW_STATUS                    56
 100 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 101 #define OPAL_RESERVED1                          58
 102 #define OPAL_RESERVED2                          59
 103 #define OPAL_PCI_NEXT_ERROR                     60
 104 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 105 #define OPAL_PCI_POLL                           62
 106 #define OPAL_PCI_MSI_EOI                        63
 107 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 108 #define OPAL_XSCOM_READ                         65
 109 #define OPAL_XSCOM_WRITE                        66
 110 #define OPAL_LPC_READ                           67
 111 #define OPAL_LPC_WRITE                          68
 112 #define OPAL_RETURN_CPU                         69
 113 #define OPAL_REINIT_CPUS                        70
 114 #define OPAL_ELOG_READ                          71
 115 #define OPAL_ELOG_WRITE                         72
 116 #define OPAL_ELOG_ACK                           73
 117 #define OPAL_ELOG_RESEND                        74
 118 #define OPAL_ELOG_SIZE                          75
 119 #define OPAL_FLASH_VALIDATE                     76
 120 #define OPAL_FLASH_MANAGE                       77
 121 #define OPAL_FLASH_UPDATE                       78
 122 #define OPAL_RESYNC_TIMEBASE                    79
 123 #define OPAL_CHECK_TOKEN                        80
 124 #define OPAL_DUMP_INIT                          81
 125 #define OPAL_DUMP_INFO                          82
 126 #define OPAL_DUMP_READ                          83
 127 #define OPAL_DUMP_ACK                           84
 128 #define OPAL_GET_MSG                            85
 129 #define OPAL_CHECK_ASYNC_COMPLETION             86
 130 #define OPAL_SYNC_HOST_REBOOT                   87
 131 #define OPAL_SENSOR_READ                        88
 132 #define OPAL_GET_PARAM                          89
 133 #define OPAL_SET_PARAM                          90
 134 #define OPAL_DUMP_RESEND                        91
 135 #define OPAL_ELOG_SEND                          92      /* Deprecated */
 136 #define OPAL_PCI_SET_PHB_CAPI_MODE              93
 137 #define OPAL_DUMP_INFO2                         94
 138 #define OPAL_WRITE_OPPANEL_ASYNC                95
 139 #define OPAL_PCI_ERR_INJECT                     96
 140 #define OPAL_PCI_EEH_FREEZE_SET                 97
 141 #define OPAL_HANDLE_HMI                         98
 142 #define OPAL_CONFIG_CPU_IDLE_STATE              99
 143 #define OPAL_SLW_SET_REG                        100
 144 #define OPAL_REGISTER_DUMP_REGION               101
 145 #define OPAL_UNREGISTER_DUMP_REGION             102
 146 #define OPAL_WRITE_TPO                          103
 147 #define OPAL_READ_TPO                           104
 148 #define OPAL_GET_DPO_STATUS                     105
 149 #define OPAL_OLD_I2C_REQUEST                    106     /* Deprecated */
 150 #define OPAL_IPMI_SEND                          107
 151 #define OPAL_IPMI_RECV                          108
 152 #define OPAL_I2C_REQUEST                        109
 153 #define OPAL_LAST                               109
 154
 155 /* Device tree flags */
 156
 157 /* Flags set in power-mgmt nodes in device tree if
 158  * respective idle states are supported in the platform.
 159  */
 160 #define OPAL_PM_NAP_ENABLED             0x00010000
 161 #define OPAL_PM_SLEEP_ENABLED           0x00020000
 162 #define OPAL_PM_WINKLE_ENABLED          0x00040000
 163 #define OPAL_PM_SLEEP_ENABLED_ER1       0x00080000 /* with workaround */
 164
 165 #ifndef __ASSEMBLY__
 166
 167 /* Other enums */
 168 enum OpalVendorApiTokens {
 169         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 170 };
 171
 172 enum OpalFreezeState {
 173         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 174         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 175         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 176         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 177         OPAL_EEH_STOPPED_RESET = 4,
 178         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 179         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 180 };
 181
 182 enum OpalEehFreezeActionToken {
 183         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 184         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 185         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
 186
 187         OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
 188         OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
 189         OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
 190 };
 191
 192 enum OpalPciStatusToken {
 193         OPAL_EEH_NO_ERROR       = 0,
 194         OPAL_EEH_IOC_ERROR      = 1,
 195         OPAL_EEH_PHB_ERROR      = 2,
 196         OPAL_EEH_PE_ERROR       = 3,
 197         OPAL_EEH_PE_MMIO_ERROR  = 4,
 198         OPAL_EEH_PE_DMA_ERROR   = 5
 199 };
 200
 201 enum OpalPciErrorSeverity {
 202         OPAL_EEH_SEV_NO_ERROR   = 0,
 203         OPAL_EEH_SEV_IOC_DEAD   = 1,
 204         OPAL_EEH_SEV_PHB_DEAD   = 2,
 205         OPAL_EEH_SEV_PHB_FENCED = 3,
 206         OPAL_EEH_SEV_PE_ER      = 4,
 207         OPAL_EEH_SEV_INF        = 5
 208 };
 209
 210 enum OpalErrinjectType {
 211         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
 212         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
 213 };
 214
 215 enum OpalErrinjectFunc {
 216         /* IOA bus specific errors */
 217         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
 218         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
 219         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
 220         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
 221         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
 222         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
 223         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
 224         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
 225         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
 226         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
 227         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
 228         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
 229         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
 230         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
 231         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
 232         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
 233         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
 234         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
 235         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
 236         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
 237 };
 238
 239 enum OpalShpcAction {
 240         OPAL_SHPC_GET_LINK_STATE = 0,
 241         OPAL_SHPC_GET_SLOT_STATE = 1
 242 };
 243
 244 enum OpalShpcLinkState {
 245         OPAL_SHPC_LINK_DOWN = 0,
 246         OPAL_SHPC_LINK_UP = 1
 247 };
 248
 249 enum OpalMmioWindowType {
 250         OPAL_M32_WINDOW_TYPE = 1,
 251         OPAL_M64_WINDOW_TYPE = 2,
 252         OPAL_IO_WINDOW_TYPE  = 3
 253 };
 254
 255 enum OpalShpcSlotState {
 256         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 257         OPAL_SHPC_DEV_PRESENT = 1
 258 };
 259
 260 enum OpalExceptionHandler {
 261         OPAL_MACHINE_CHECK_HANDLER          = 1,
 262         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 263         OPAL_SOFTPATCH_HANDLER              = 3
 264 };
 265
 266 enum OpalPendingState {
 267         OPAL_EVENT_OPAL_INTERNAL   = 0x1,
 268         OPAL_EVENT_NVRAM           = 0x2,
 269         OPAL_EVENT_RTC             = 0x4,
 270         OPAL_EVENT_CONSOLE_OUTPUT  = 0x8,
 271         OPAL_EVENT_CONSOLE_INPUT   = 0x10,
 272         OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
 273         OPAL_EVENT_ERROR_LOG       = 0x40,
 274         OPAL_EVENT_EPOW            = 0x80,
 275         OPAL_EVENT_LED_STATUS      = 0x100,
 276         OPAL_EVENT_PCI_ERROR       = 0x200,
 277         OPAL_EVENT_DUMP_AVAIL      = 0x400,
 278         OPAL_EVENT_MSG_PENDING     = 0x800,
 279 };
 280
 281 enum OpalThreadStatus {
 282         OPAL_THREAD_INACTIVE = 0x0,
 283         OPAL_THREAD_STARTED = 0x1,
 284         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 285 };
 286
 287 enum OpalPciBusCompare {
 288         OpalPciBusAny   = 0,    /* Any bus number match */
 289         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 290         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 291         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 292         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 293         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 294         OpalPciBusAll   = 7,    /* Match bus number exactly */
 295 };
 296
 297 enum OpalDeviceCompare {
 298         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 299         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 300 };
 301
 302 enum OpalFuncCompare {
 303         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 304         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 305 };
 306
 307 enum OpalPeAction {
 308         OPAL_UNMAP_PE = 0,
 309         OPAL_MAP_PE = 1
 310 };
 311
 312 enum OpalPeltvAction {
 313         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 314         OPAL_ADD_PE_TO_DOMAIN = 1
 315 };
 316
 317 enum OpalMveEnableAction {
 318         OPAL_DISABLE_MVE = 0,
 319         OPAL_ENABLE_MVE = 1
 320 };
 321
 322 enum OpalM64Action {
 323         OPAL_DISABLE_M64 = 0,
 324         OPAL_ENABLE_M64_SPLIT = 1,
 325         OPAL_ENABLE_M64_NON_SPLIT = 2
 326 };
 327
 328 enum OpalPciResetScope {
 329         OPAL_RESET_PHB_COMPLETE         = 1,
 330         OPAL_RESET_PCI_LINK             = 2,
 331         OPAL_RESET_PHB_ERROR            = 3,
 332         OPAL_RESET_PCI_HOT              = 4,
 333         OPAL_RESET_PCI_FUNDAMENTAL      = 5,
 334         OPAL_RESET_PCI_IODA_TABLE       = 6
 335 };
 336
 337 enum OpalPciReinitScope {
 338         /*
 339          * Note: we chose values that do not overlap
 340          * OpalPciResetScope as OPAL v2 used the same
 341          * enum for both
 342          */
 343         OPAL_REINIT_PCI_DEV = 1000
 344 };
 345
 346 enum OpalPciResetState {
 347         OPAL_DEASSERT_RESET = 0,
 348         OPAL_ASSERT_RESET   = 1
 349 };
 350
 351 enum OpalPciMaskAction {
 352         OPAL_UNMASK_ERROR_TYPE = 0,
 353         OPAL_MASK_ERROR_TYPE = 1
 354 };
 355
 356 enum OpalSlotLedType {
 357         OPAL_SLOT_LED_ID_TYPE = 0,
 358         OPAL_SLOT_LED_FAULT_TYPE = 1
 359 };
 360
 361 enum OpalLedAction {
 362         OPAL_TURN_OFF_LED = 0,
 363         OPAL_TURN_ON_LED = 1,
 364         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 365 };
 366
 367 enum OpalEpowStatus {
 368         OPAL_EPOW_NONE = 0,
 369         OPAL_EPOW_UPS = 1,
 370         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 371         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 372 };
 373
 374 /*
 375  * Address cycle types for LPC accesses. These also correspond
 376  * to the content of the first cell of the "reg" property for
 377  * device nodes on the LPC bus
 378  */
 379 enum OpalLPCAddressType {
 380         OPAL_LPC_MEM    = 0,
 381         OPAL_LPC_IO     = 1,
 382         OPAL_LPC_FW     = 2,
 383 };
 384
 385 enum opal_msg_type {
 386         OPAL_MSG_ASYNC_COMP = 0,        /* params[0] = token, params[1] = rc,
 387                                          * additional params function-specific
 388                                          */
 389         OPAL_MSG_MEM_ERR,
 390         OPAL_MSG_EPOW,
 391         OPAL_MSG_SHUTDOWN,              /* params[0] = 1 reboot, 0 shutdown */
 392         OPAL_MSG_HMI_EVT,
 393         OPAL_MSG_DPO,
 394         OPAL_MSG_TYPE_MAX,
 395 };
 396
 397 struct opal_msg {
 398         __be32 msg_type;
 399         __be32 reserved;
 400         __be64 params[8];
 401 };
 402
 403 /* System parameter permission */
 404 enum OpalSysparamPerm {
 405         OPAL_SYSPARAM_READ  = 0x1,
 406         OPAL_SYSPARAM_WRITE = 0x2,
 407         OPAL_SYSPARAM_RW    = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 408 };
 409
 410 enum {
 411         OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
 412 };
 413
 414 struct opal_ipmi_msg {
 415         uint8_t version;
 416         uint8_t netfn;
 417         uint8_t cmd;
 418         uint8_t data[];
 419 };
 420
 421 /* FSP memory errors handling */
 422 enum OpalMemErr_Version {
 423         OpalMemErr_V1 = 1,
 424 };
 425
 426 enum OpalMemErrType {
 427         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 428         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 429 };
 430
 431 /* Memory Reilience error type */
 432 enum OpalMemErr_ResilErrType {
 433         OPAL_MEM_RESILIENCE_CE          = 0,
 434         OPAL_MEM_RESILIENCE_UE,
 435         OPAL_MEM_RESILIENCE_UE_SCRUB,
 436 };
 437
 438 /* Dynamic Memory Deallocation type */
 439 enum OpalMemErr_DynErrType {
 440         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 441 };
 442
 443 /* OpalMemoryErrorData->flags */
 444 #define OPAL_MEM_CORRECTED_ERROR        0x0001
 445 #define OPAL_MEM_THRESHOLD_EXCEEDED     0x0002
 446 #define OPAL_MEM_ACK_REQUIRED           0x8000
 447
 448 struct OpalMemoryErrorData {
 449         enum OpalMemErr_Version version:8;      /* 0x00 */
 450         enum OpalMemErrType     type:8;         /* 0x01 */
 451         __be16                  flags;          /* 0x02 */
 452         uint8_t                 reserved_1[4];  /* 0x04 */
 453
 454         union {
 455                 /* Memory Resilience corrected/uncorrected error info */
 456                 struct {
 457                         enum OpalMemErr_ResilErrType    resil_err_type:8;
 458                         uint8_t                         reserved_1[7];
 459                         __be64                          physical_address_start;
 460                         __be64                          physical_address_end;
 461                 } resilience;
 462                 /* Dynamic memory deallocation error info */
 463                 struct {
 464                         enum OpalMemErr_DynErrType      dyn_err_type:8;
 465                         uint8_t                         reserved_1[7];
 466                         __be64                          physical_address_start;
 467                         __be64                          physical_address_end;
 468                 } dyn_dealloc;
 469         } u;
 470 };
 471
 472 /* HMI interrupt event */
 473 enum OpalHMI_Version {
 474         OpalHMIEvt_V1 = 1,
 475 };
 476
 477 enum OpalHMI_Severity {
 478         OpalHMI_SEV_NO_ERROR = 0,
 479         OpalHMI_SEV_WARNING = 1,
 480         OpalHMI_SEV_ERROR_SYNC = 2,
 481         OpalHMI_SEV_FATAL = 3,
 482 };
 483
 484 enum OpalHMI_Disposition {
 485         OpalHMI_DISPOSITION_RECOVERED = 0,
 486         OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
 487 };
 488
 489 enum OpalHMI_ErrType {
 490         OpalHMI_ERROR_MALFUNC_ALERT     = 0,
 491         OpalHMI_ERROR_PROC_RECOV_DONE,
 492         OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
 493         OpalHMI_ERROR_PROC_RECOV_MASKED,
 494         OpalHMI_ERROR_TFAC,
 495         OpalHMI_ERROR_TFMR_PARITY,
 496         OpalHMI_ERROR_HA_OVERFLOW_WARN,
 497         OpalHMI_ERROR_XSCOM_FAIL,
 498         OpalHMI_ERROR_XSCOM_DONE,
 499         OpalHMI_ERROR_SCOM_FIR,
 500         OpalHMI_ERROR_DEBUG_TRIG_FIR,
 501         OpalHMI_ERROR_HYP_RESOURCE,
 502         OpalHMI_ERROR_CAPP_RECOVERY,
 503 };
 504
 505 struct OpalHMIEvent {
 506         uint8_t         version;        /* 0x00 */
 507         uint8_t         severity;       /* 0x01 */
 508         uint8_t         type;           /* 0x02 */
 509         uint8_t         disposition;    /* 0x03 */
 510         uint8_t         reserved_1[4];  /* 0x04 */
 511
 512         __be64          hmer;
 513         /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
 514         __be64          tfmr;
 515 };
 516
 517 enum {
 518         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 519         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 520         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 521         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 522         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 523         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 524         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 525 };
 526
 527 struct OpalIoP7IOCErrorData {
 528         __be16 type;
 529
 530         /* GEM */
 531         __be64 gemXfir;
 532         __be64 gemRfir;
 533         __be64 gemRirqfir;
 534         __be64 gemMask;
 535         __be64 gemRwof;
 536
 537         /* LEM */
 538         __be64 lemFir;
 539         __be64 lemErrMask;
 540         __be64 lemAction0;
 541         __be64 lemAction1;
 542         __be64 lemWof;
 543
 544         union {
 545                 struct OpalIoP7IOCRgcErrorData {
 546                         __be64 rgcStatus;       /* 3E1C10 */
 547                         __be64 rgcLdcp;         /* 3E1C18 */
 548                 }rgc;
 549                 struct OpalIoP7IOCBiErrorData {
 550                         __be64 biLdcp0;         /* 3C0100, 3C0118 */
 551                         __be64 biLdcp1;         /* 3C0108, 3C0120 */
 552                         __be64 biLdcp2;         /* 3C0110, 3C0128 */
 553                         __be64 biFenceStatus;   /* 3C0130, 3C0130 */
 554
 555                         uint8_t biDownbound;    /* BI Downbound or Upbound */
 556                 }bi;
 557                 struct OpalIoP7IOCCiErrorData {
 558                         __be64 ciPortStatus;    /* 3Dn008 */
 559                         __be64 ciPortLdcp;      /* 3Dn010 */
 560
 561                         uint8_t ciPort;         /* Index of CI port: 0/1 */
 562                 }ci;
 563         };
 564 };
 565
 566 /**
 567  * This structure defines the overlay which will be used to store PHB error
 568  * data upon request.
 569  */
 570 enum {
 571         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 572 };
 573
 574 enum {
 575         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 576         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 577 };
 578
 579 enum {
 580         OPAL_P7IOC_NUM_PEST_REGS = 128,
 581         OPAL_PHB3_NUM_PEST_REGS = 256
 582 };
 583
 584 struct OpalIoPhbErrorCommon {
 585         __be32 version;
 586         __be32 ioType;
 587         __be32 len;
 588 };
 589
 590 struct OpalIoP7IOCPhbErrorData {
 591         struct OpalIoPhbErrorCommon common;
 592
 593         __be32 brdgCtl;
 594
 595         // P7IOC utl regs
 596         __be32 portStatusReg;
 597         __be32 rootCmplxStatus;
 598         __be32 busAgentStatus;
 599
 600         // P7IOC cfg regs
 601         __be32 deviceStatus;
 602         __be32 slotStatus;
 603         __be32 linkStatus;
 604         __be32 devCmdStatus;
 605         __be32 devSecStatus;
 606
 607         // cfg AER regs
 608         __be32 rootErrorStatus;
 609         __be32 uncorrErrorStatus;
 610         __be32 corrErrorStatus;
 611         __be32 tlpHdr1;
 612         __be32 tlpHdr2;
 613         __be32 tlpHdr3;
 614         __be32 tlpHdr4;
 615         __be32 sourceId;
 616
 617         __be32 rsv3;
 618
 619         // Record data about the call to allocate a buffer.
 620         __be64 errorClass;
 621         __be64 correlator;
 622
 623         //P7IOC MMIO Error Regs
 624         __be64 p7iocPlssr;                // n120
 625         __be64 p7iocCsr;                  // n110
 626         __be64 lemFir;                    // nC00
 627         __be64 lemErrorMask;              // nC18
 628         __be64 lemWOF;                    // nC40
 629         __be64 phbErrorStatus;            // nC80
 630         __be64 phbFirstErrorStatus;       // nC88
 631         __be64 phbErrorLog0;              // nCC0
 632         __be64 phbErrorLog1;              // nCC8
 633         __be64 mmioErrorStatus;           // nD00
 634         __be64 mmioFirstErrorStatus;      // nD08
 635         __be64 mmioErrorLog0;             // nD40
 636         __be64 mmioErrorLog1;             // nD48
 637         __be64 dma0ErrorStatus;           // nD80
 638         __be64 dma0FirstErrorStatus;      // nD88
 639         __be64 dma0ErrorLog0;             // nDC0
 640         __be64 dma0ErrorLog1;             // nDC8
 641         __be64 dma1ErrorStatus;           // nE00
 642         __be64 dma1FirstErrorStatus;      // nE08
 643         __be64 dma1ErrorLog0;             // nE40
 644         __be64 dma1ErrorLog1;             // nE48
 645         __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
 646         __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
 647 };
 648
 649 struct OpalIoPhb3ErrorData {
 650         struct OpalIoPhbErrorCommon common;
 651
 652         __be32 brdgCtl;
 653
 654         /* PHB3 UTL regs */
 655         __be32 portStatusReg;
 656         __be32 rootCmplxStatus;
 657         __be32 busAgentStatus;
 658
 659         /* PHB3 cfg regs */
 660         __be32 deviceStatus;
 661         __be32 slotStatus;
 662         __be32 linkStatus;
 663         __be32 devCmdStatus;
 664         __be32 devSecStatus;
 665
 666         /* cfg AER regs */
 667         __be32 rootErrorStatus;
 668         __be32 uncorrErrorStatus;
 669         __be32 corrErrorStatus;
 670         __be32 tlpHdr1;
 671         __be32 tlpHdr2;
 672         __be32 tlpHdr3;
 673         __be32 tlpHdr4;
 674         __be32 sourceId;
 675
 676         __be32 rsv3;
 677
 678         /* Record data about the call to allocate a buffer */
 679         __be64 errorClass;
 680         __be64 correlator;
 681
 682         /* PHB3 MMIO Error Regs */
 683         __be64 nFir;                    /* 000 */
 684         __be64 nFirMask;                /* 003 */
 685         __be64 nFirWOF;         /* 008 */
 686         __be64 phbPlssr;                /* 120 */
 687         __be64 phbCsr;          /* 110 */
 688         __be64 lemFir;          /* C00 */
 689         __be64 lemErrorMask;            /* C18 */
 690         __be64 lemWOF;          /* C40 */
 691         __be64 phbErrorStatus;  /* C80 */
 692         __be64 phbFirstErrorStatus;     /* C88 */
 693         __be64 phbErrorLog0;            /* CC0 */
 694         __be64 phbErrorLog1;            /* CC8 */
 695         __be64 mmioErrorStatus; /* D00 */
 696         __be64 mmioFirstErrorStatus;    /* D08 */
 697         __be64 mmioErrorLog0;           /* D40 */
 698         __be64 mmioErrorLog1;           /* D48 */
 699         __be64 dma0ErrorStatus; /* D80 */
 700         __be64 dma0FirstErrorStatus;    /* D88 */
 701         __be64 dma0ErrorLog0;           /* DC0 */
 702         __be64 dma0ErrorLog1;           /* DC8 */
 703         __be64 dma1ErrorStatus; /* E00 */
 704         __be64 dma1FirstErrorStatus;    /* E08 */
 705         __be64 dma1ErrorLog0;           /* E40 */
 706         __be64 dma1ErrorLog1;           /* E48 */
 707         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 708         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 709 };
 710
 711 enum {
 712         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 713         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 714 };
 715
 716 typedef struct oppanel_line {
 717         __be64 line;
 718         __be64 line_len;
 719 } oppanel_line_t;
 720
 721 /*
 722  * SG entries
 723  *
 724  * WARNING: The current implementation requires each entry
 725  * to represent a block that is 4k aligned *and* each block
 726  * size except the last one in the list to be as well.
 727  */
 728 struct opal_sg_entry {
 729         __be64 data;
 730         __be64 length;
 731 };
 732
 733 /*
 734  * Candiate image SG list.
 735  *
 736  * length = VER | length
 737  */
 738 struct opal_sg_list {
 739         __be64 length;
 740         __be64 next;
 741         struct opal_sg_entry entry[];
 742 };
 743
 744 /*
 745  * Dump region ID range usable by the OS
 746  */
 747 #define OPAL_DUMP_REGION_HOST_START             0x80
 748 #define OPAL_DUMP_REGION_LOG_BUF                0x80
 749 #define OPAL_DUMP_REGION_HOST_END               0xFF
 750
 751 /* CAPI modes for PHB */
 752 enum {
 753         OPAL_PHB_CAPI_MODE_PCIE         = 0,
 754         OPAL_PHB_CAPI_MODE_CAPI         = 1,
 755         OPAL_PHB_CAPI_MODE_SNOOP_OFF    = 2,
 756         OPAL_PHB_CAPI_MODE_SNOOP_ON     = 3,
 757 };
 758
 759 /* OPAL I2C request */
 760 struct opal_i2c_request {
 761         uint8_t type;
 762 #define OPAL_I2C_RAW_READ       0
 763 #define OPAL_I2C_RAW_WRITE      1
 764 #define OPAL_I2C_SM_READ        2
 765 #define OPAL_I2C_SM_WRITE       3
 766         uint8_t flags;
 767 #define OPAL_I2C_ADDR_10        0x01    /* Not supported yet */
 768         uint8_t subaddr_sz;             /* Max 4 */
 769         uint8_t reserved;
 770         __be16 addr;                    /* 7 or 10 bit address */
 771         __be16 reserved2;
 772         __be32 subaddr;         /* Sub-address if any */
 773         __be32 size;                    /* Data size */
 774         __be64 buffer_ra;               /* Buffer real address */
 775 };
 776
 777 #endif /* __ASSEMBLY__ */
 778
 779 #endif /* __OPAL_API_H */