arch/powerpc/include/asm/opal-api.h

   1 /*
   2  * PowerNV OPAL definitions.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_API_H
  13 #define __OPAL_API_H
  14
  15 /****** OPAL APIs ******/
  16
  17 /* Return codes */
  18 #define OPAL_SUCCESS            0
  19 #define OPAL_PARAMETER          -1
  20 #define OPAL_BUSY               -2
  21 #define OPAL_PARTIAL            -3
  22 #define OPAL_CONSTRAINED        -4
  23 #define OPAL_CLOSED             -5
  24 #define OPAL_HARDWARE           -6
  25 #define OPAL_UNSUPPORTED        -7
  26 #define OPAL_PERMISSION         -8
  27 #define OPAL_NO_MEM             -9
  28 #define OPAL_RESOURCE           -10
  29 #define OPAL_INTERNAL_ERROR     -11
  30 #define OPAL_BUSY_EVENT         -12
  31 #define OPAL_HARDWARE_FROZEN    -13
  32 #define OPAL_WRONG_STATE        -14
  33 #define OPAL_ASYNC_COMPLETION   -15
  34 #define OPAL_I2C_TIMEOUT        -17
  35 #define OPAL_I2C_INVALID_CMD    -18
  36 #define OPAL_I2C_LBUS_PARITY    -19
  37 #define OPAL_I2C_BKEND_OVERRUN  -20
  38 #define OPAL_I2C_BKEND_ACCESS   -21
  39 #define OPAL_I2C_ARBT_LOST      -22
  40 #define OPAL_I2C_NACK_RCVD      -23
  41 #define OPAL_I2C_STOP_ERR       -24
  42
  43 /* API Tokens (in r0) */
  44 #define OPAL_INVALID_CALL                       -1
  45 #define OPAL_CONSOLE_WRITE                      1
  46 #define OPAL_CONSOLE_READ                       2
  47 #define OPAL_RTC_READ                           3
  48 #define OPAL_RTC_WRITE                          4
  49 #define OPAL_CEC_POWER_DOWN                     5
  50 #define OPAL_CEC_REBOOT                         6
  51 #define OPAL_READ_NVRAM                         7
  52 #define OPAL_WRITE_NVRAM                        8
  53 #define OPAL_HANDLE_INTERRUPT                   9
  54 #define OPAL_POLL_EVENTS                        10
  55 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  56 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  57 #define OPAL_PCI_CONFIG_READ_BYTE               13
  58 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  59 #define OPAL_PCI_CONFIG_READ_WORD               15
  60 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  61 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  62 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  63 #define OPAL_SET_XIVE                           19
  64 #define OPAL_GET_XIVE                           20
  65 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  66 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  67 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  68 #define OPAL_PCI_SHPC                           24
  69 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  70 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  71 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  72 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  73 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  74 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  75 #define OPAL_PCI_SET_PE                         31
  76 #define OPAL_PCI_SET_PELTV                      32
  77 #define OPAL_PCI_SET_MVE                        33
  78 #define OPAL_PCI_SET_MVE_ENABLE                 34
  79 #define OPAL_PCI_GET_XIVE_REISSUE               35
  80 #define OPAL_PCI_SET_XIVE_REISSUE               36
  81 #define OPAL_PCI_SET_XIVE_PE                    37
  82 #define OPAL_GET_XIVE_SOURCE                    38
  83 #define OPAL_GET_MSI_32                         39
  84 #define OPAL_GET_MSI_64                         40
  85 #define OPAL_START_CPU                          41
  86 #define OPAL_QUERY_CPU_STATUS                   42
  87 #define OPAL_WRITE_OPPANEL                      43
  88 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
  89 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
  90 #define OPAL_PCI_RESET                          49
  91 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
  92 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
  93 #define OPAL_PCI_FENCE_PHB                      52
  94 #define OPAL_PCI_REINIT                         53
  95 #define OPAL_PCI_MASK_PE_ERROR                  54
  96 #define OPAL_SET_SLOT_LED_STATUS                55
  97 #define OPAL_GET_EPOW_STATUS                    56
  98 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
  99 #define OPAL_RESERVED1                          58
 100 #define OPAL_RESERVED2                          59
 101 #define OPAL_PCI_NEXT_ERROR                     60
 102 #define OPAL_PCI_EEH_FREEZE_STATUS2             61
 103 #define OPAL_PCI_POLL                           62
 104 #define OPAL_PCI_MSI_EOI                        63
 105 #define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 106 #define OPAL_XSCOM_READ                         65
 107 #define OPAL_XSCOM_WRITE                        66
 108 #define OPAL_LPC_READ                           67
 109 #define OPAL_LPC_WRITE                          68
 110 #define OPAL_RETURN_CPU                         69
 111 #define OPAL_REINIT_CPUS                        70
 112 #define OPAL_ELOG_READ                          71
 113 #define OPAL_ELOG_WRITE                         72
 114 #define OPAL_ELOG_ACK                           73
 115 #define OPAL_ELOG_RESEND                        74
 116 #define OPAL_ELOG_SIZE                          75
 117 #define OPAL_FLASH_VALIDATE                     76
 118 #define OPAL_FLASH_MANAGE                       77
 119 #define OPAL_FLASH_UPDATE                       78
 120 #define OPAL_RESYNC_TIMEBASE                    79
 121 #define OPAL_CHECK_TOKEN                        80
 122 #define OPAL_DUMP_INIT                          81
 123 #define OPAL_DUMP_INFO                          82
 124 #define OPAL_DUMP_READ                          83
 125 #define OPAL_DUMP_ACK                           84
 126 #define OPAL_GET_MSG                            85
 127 #define OPAL_CHECK_ASYNC_COMPLETION             86
 128 #define OPAL_SYNC_HOST_REBOOT                   87
 129 #define OPAL_SENSOR_READ                        88
 130 #define OPAL_GET_PARAM                          89
 131 #define OPAL_SET_PARAM                          90
 132 #define OPAL_DUMP_RESEND                        91
 133 #define OPAL_PCI_SET_PHB_CXL_MODE               93
 134 #define OPAL_DUMP_INFO2                         94
 135 #define OPAL_PCI_ERR_INJECT                     96
 136 #define OPAL_PCI_EEH_FREEZE_SET                 97
 137 #define OPAL_HANDLE_HMI                         98
 138 #define OPAL_CONFIG_CPU_IDLE_STATE              99
 139 #define OPAL_SLW_SET_REG                        100
 140 #define OPAL_REGISTER_DUMP_REGION               101
 141 #define OPAL_UNREGISTER_DUMP_REGION             102
 142 #define OPAL_WRITE_TPO                          103
 143 #define OPAL_READ_TPO                           104
 144 #define OPAL_IPMI_SEND                          107
 145 #define OPAL_IPMI_RECV                          108
 146 #define OPAL_I2C_REQUEST                        109
 147
 148 /* Device tree flags */
 149
 150 /* Flags set in power-mgmt nodes in device tree if
 151  * respective idle states are supported in the platform.
 152  */
 153 #define OPAL_PM_NAP_ENABLED     0x00010000
 154 #define OPAL_PM_SLEEP_ENABLED   0x00020000
 155 #define OPAL_PM_WINKLE_ENABLED  0x00040000
 156 #define OPAL_PM_SLEEP_ENABLED_ER1       0x00080000
 157
 158 #ifndef __ASSEMBLY__
 159
 160 /* Other enums */
 161 enum OpalVendorApiTokens {
 162         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 163 };
 164
 165 enum OpalFreezeState {
 166         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 167         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 168         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 169         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 170         OPAL_EEH_STOPPED_RESET = 4,
 171         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 172         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 173 };
 174
 175 enum OpalEehFreezeActionToken {
 176         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 177         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 178         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
 179
 180         OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
 181         OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
 182         OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
 183 };
 184
 185 enum OpalPciStatusToken {
 186         OPAL_EEH_NO_ERROR       = 0,
 187         OPAL_EEH_IOC_ERROR      = 1,
 188         OPAL_EEH_PHB_ERROR      = 2,
 189         OPAL_EEH_PE_ERROR       = 3,
 190         OPAL_EEH_PE_MMIO_ERROR  = 4,
 191         OPAL_EEH_PE_DMA_ERROR   = 5
 192 };
 193
 194 enum OpalPciErrorSeverity {
 195         OPAL_EEH_SEV_NO_ERROR   = 0,
 196         OPAL_EEH_SEV_IOC_DEAD   = 1,
 197         OPAL_EEH_SEV_PHB_DEAD   = 2,
 198         OPAL_EEH_SEV_PHB_FENCED = 3,
 199         OPAL_EEH_SEV_PE_ER      = 4,
 200         OPAL_EEH_SEV_INF        = 5
 201 };
 202
 203 enum OpalErrinjectType {
 204         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR        = 0,
 205         OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64      = 1,
 206 };
 207
 208 enum OpalErrinjectFunc {
 209         /* IOA bus specific errors */
 210         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR    = 0,
 211         OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA    = 1,
 212         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR     = 2,
 213         OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA     = 3,
 214         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR    = 4,
 215         OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA    = 5,
 216         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR    = 6,
 217         OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA    = 7,
 218         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR     = 8,
 219         OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA     = 9,
 220         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR    = 10,
 221         OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA    = 11,
 222         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR    = 12,
 223         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA    = 13,
 224         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER  = 14,
 225         OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET  = 15,
 226         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR    = 16,
 227         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA    = 17,
 228         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER  = 18,
 229         OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET  = 19,
 230 };
 231
 232 enum OpalShpcAction {
 233         OPAL_SHPC_GET_LINK_STATE = 0,
 234         OPAL_SHPC_GET_SLOT_STATE = 1
 235 };
 236
 237 enum OpalShpcLinkState {
 238         OPAL_SHPC_LINK_DOWN = 0,
 239         OPAL_SHPC_LINK_UP = 1
 240 };
 241
 242 enum OpalMmioWindowType {
 243         OPAL_M32_WINDOW_TYPE = 1,
 244         OPAL_M64_WINDOW_TYPE = 2,
 245         OPAL_IO_WINDOW_TYPE = 3
 246 };
 247
 248 enum OpalShpcSlotState {
 249         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 250         OPAL_SHPC_DEV_PRESENT = 1
 251 };
 252
 253 enum OpalExceptionHandler {
 254         OPAL_MACHINE_CHECK_HANDLER = 1,
 255         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 256         OPAL_SOFTPATCH_HANDLER = 3
 257 };
 258
 259 enum OpalPendingState {
 260         OPAL_EVENT_OPAL_INTERNAL        = 0x1,
 261         OPAL_EVENT_NVRAM                = 0x2,
 262         OPAL_EVENT_RTC                  = 0x4,
 263         OPAL_EVENT_CONSOLE_OUTPUT       = 0x8,
 264         OPAL_EVENT_CONSOLE_INPUT        = 0x10,
 265         OPAL_EVENT_ERROR_LOG_AVAIL      = 0x20,
 266         OPAL_EVENT_ERROR_LOG            = 0x40,
 267         OPAL_EVENT_EPOW                 = 0x80,
 268         OPAL_EVENT_LED_STATUS           = 0x100,
 269         OPAL_EVENT_PCI_ERROR            = 0x200,
 270         OPAL_EVENT_DUMP_AVAIL           = 0x400,
 271         OPAL_EVENT_MSG_PENDING          = 0x800,
 272 };
 273
 274 enum OpalMessageType {
 275         OPAL_MSG_ASYNC_COMP = 0,        /* params[0] = token, params[1] = rc,
 276                                          * additional params function-specific
 277                                          */
 278         OPAL_MSG_MEM_ERR,
 279         OPAL_MSG_EPOW,
 280         OPAL_MSG_SHUTDOWN,              /* params[0] = 1 reboot, 0 shutdown */
 281         OPAL_MSG_HMI_EVT,
 282         OPAL_MSG_TYPE_MAX,
 283 };
 284
 285 enum OpalThreadStatus {
 286         OPAL_THREAD_INACTIVE = 0x0,
 287         OPAL_THREAD_STARTED = 0x1,
 288         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 289 };
 290
 291 enum OpalPciBusCompare {
 292         OpalPciBusAny   = 0,    /* Any bus number match */
 293         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 294         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 295         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 296         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 297         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 298         OpalPciBusAll   = 7,    /* Match bus number exactly */
 299 };
 300
 301 enum OpalDeviceCompare {
 302         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 303         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 304 };
 305
 306 enum OpalFuncCompare {
 307         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 308         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 309 };
 310
 311 enum OpalPeAction {
 312         OPAL_UNMAP_PE = 0,
 313         OPAL_MAP_PE = 1
 314 };
 315
 316 enum OpalPeltvAction {
 317         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 318         OPAL_ADD_PE_TO_DOMAIN = 1
 319 };
 320
 321 enum OpalMveEnableAction {
 322         OPAL_DISABLE_MVE = 0,
 323         OPAL_ENABLE_MVE = 1
 324 };
 325
 326 enum OpalM64EnableAction {
 327         OPAL_DISABLE_M64 = 0,
 328         OPAL_ENABLE_M64_SPLIT = 1,
 329         OPAL_ENABLE_M64_NON_SPLIT = 2
 330 };
 331
 332 enum OpalPciResetScope {
 333         OPAL_RESET_PHB_COMPLETE         = 1,
 334         OPAL_RESET_PCI_LINK             = 2,
 335         OPAL_RESET_PHB_ERROR            = 3,
 336         OPAL_RESET_PCI_HOT              = 4,
 337         OPAL_RESET_PCI_FUNDAMENTAL      = 5,
 338         OPAL_RESET_PCI_IODA_TABLE       = 6
 339 };
 340
 341 enum OpalPciReinitScope {
 342         OPAL_REINIT_PCI_DEV = 1000
 343 };
 344
 345 enum OpalPciResetState {
 346         OPAL_DEASSERT_RESET = 0,
 347         OPAL_ASSERT_RESET = 1
 348 };
 349
 350 enum OpalPciMaskAction {
 351         OPAL_UNMASK_ERROR_TYPE = 0,
 352         OPAL_MASK_ERROR_TYPE = 1
 353 };
 354
 355 enum OpalSlotLedType {
 356         OPAL_SLOT_LED_ID_TYPE = 0,
 357         OPAL_SLOT_LED_FAULT_TYPE = 1
 358 };
 359
 360 enum OpalLedAction {
 361         OPAL_TURN_OFF_LED = 0,
 362         OPAL_TURN_ON_LED = 1,
 363         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 364 };
 365
 366 enum OpalEpowStatus {
 367         OPAL_EPOW_NONE = 0,
 368         OPAL_EPOW_UPS = 1,
 369         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 370         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 371 };
 372
 373 /*
 374  * Address cycle types for LPC accesses. These also correspond
 375  * to the content of the first cell of the "reg" property for
 376  * device nodes on the LPC bus
 377  */
 378 enum OpalLPCAddressType {
 379         OPAL_LPC_MEM    = 0,
 380         OPAL_LPC_IO     = 1,
 381         OPAL_LPC_FW     = 2,
 382 };
 383
 384 /* System parameter permission */
 385 enum OpalSysparamPerm {
 386         OPAL_SYSPARAM_READ      = 0x1,
 387         OPAL_SYSPARAM_WRITE     = 0x2,
 388         OPAL_SYSPARAM_RW        = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
 389 };
 390
 391 struct opal_msg {
 392         __be32 msg_type;
 393         __be32 reserved;
 394         __be64 params[8];
 395 };
 396
 397 enum {
 398         OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
 399 };
 400
 401 struct opal_ipmi_msg {
 402         uint8_t         version;
 403         uint8_t         netfn;
 404         uint8_t         cmd;
 405         uint8_t         data[];
 406 };
 407
 408 /* FSP memory errors handling */
 409 enum OpalMemErr_Version {
 410         OpalMemErr_V1 = 1,
 411 };
 412
 413 enum OpalMemErrType {
 414         OPAL_MEM_ERR_TYPE_RESILIENCE    = 0,
 415         OPAL_MEM_ERR_TYPE_DYN_DALLOC,
 416         OPAL_MEM_ERR_TYPE_SCRUB,
 417 };
 418
 419 /* Memory Reilience error type */
 420 enum OpalMemErr_ResilErrType {
 421         OPAL_MEM_RESILIENCE_CE          = 0,
 422         OPAL_MEM_RESILIENCE_UE,
 423         OPAL_MEM_RESILIENCE_UE_SCRUB,
 424 };
 425
 426 /* Dynamic Memory Deallocation type */
 427 enum OpalMemErr_DynErrType {
 428         OPAL_MEM_DYNAMIC_DEALLOC        = 0,
 429 };
 430
 431 /* OpalMemoryErrorData->flags */
 432 #define OPAL_MEM_CORRECTED_ERROR        0x0001
 433 #define OPAL_MEM_THRESHOLD_EXCEEDED     0x0002
 434 #define OPAL_MEM_ACK_REQUIRED           0x8000
 435
 436 struct OpalMemoryErrorData {
 437         enum OpalMemErr_Version version:8;      /* 0x00 */
 438         enum OpalMemErrType     type:8;         /* 0x01 */
 439         __be16                  flags;          /* 0x02 */
 440         uint8_t                 reserved_1[4];  /* 0x04 */
 441
 442         union {
 443                 /* Memory Resilience corrected/uncorrected error info */
 444                 struct {
 445                         enum OpalMemErr_ResilErrType resil_err_type:8;
 446                         uint8_t         reserved_1[7];
 447                         __be64          physical_address_start;
 448                         __be64          physical_address_end;
 449                 } resilience;
 450                 /* Dynamic memory deallocation error info */
 451                 struct {
 452                         enum OpalMemErr_DynErrType dyn_err_type:8;
 453                         uint8_t         reserved_1[7];
 454                         __be64          physical_address_start;
 455                         __be64          physical_address_end;
 456                 } dyn_dealloc;
 457         } u;
 458 };
 459
 460 /* HMI interrupt event */
 461 enum OpalHMI_Version {
 462         OpalHMIEvt_V1 = 1,
 463 };
 464
 465 enum OpalHMI_Severity {
 466         OpalHMI_SEV_NO_ERROR = 0,
 467         OpalHMI_SEV_WARNING = 1,
 468         OpalHMI_SEV_ERROR_SYNC = 2,
 469         OpalHMI_SEV_FATAL = 3,
 470 };
 471
 472 enum OpalHMI_Disposition {
 473         OpalHMI_DISPOSITION_RECOVERED = 0,
 474         OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
 475 };
 476
 477 enum OpalHMI_ErrType {
 478         OpalHMI_ERROR_MALFUNC_ALERT     = 0,
 479         OpalHMI_ERROR_PROC_RECOV_DONE,
 480         OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
 481         OpalHMI_ERROR_PROC_RECOV_MASKED,
 482         OpalHMI_ERROR_TFAC,
 483         OpalHMI_ERROR_TFMR_PARITY,
 484         OpalHMI_ERROR_HA_OVERFLOW_WARN,
 485         OpalHMI_ERROR_XSCOM_FAIL,
 486         OpalHMI_ERROR_XSCOM_DONE,
 487         OpalHMI_ERROR_SCOM_FIR,
 488         OpalHMI_ERROR_DEBUG_TRIG_FIR,
 489         OpalHMI_ERROR_HYP_RESOURCE,
 490 };
 491
 492 struct OpalHMIEvent {
 493         uint8_t         version;        /* 0x00 */
 494         uint8_t         severity;       /* 0x01 */
 495         uint8_t         type;           /* 0x02 */
 496         uint8_t         disposition;    /* 0x03 */
 497         uint8_t         reserved_1[4];  /* 0x04 */
 498
 499         __be64          hmer;
 500         /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
 501         __be64          tfmr;
 502 };
 503
 504 enum {
 505         OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
 506         OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
 507         OPAL_P7IOC_DIAG_TYPE_BI         = 2,
 508         OPAL_P7IOC_DIAG_TYPE_CI         = 3,
 509         OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
 510         OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
 511         OPAL_P7IOC_DIAG_TYPE_LAST       = 6
 512 };
 513
 514 struct OpalIoP7IOCErrorData {
 515         __be16 type;
 516
 517         /* GEM */
 518         __be64 gemXfir;
 519         __be64 gemRfir;
 520         __be64 gemRirqfir;
 521         __be64 gemMask;
 522         __be64 gemRwof;
 523
 524         /* LEM */
 525         __be64 lemFir;
 526         __be64 lemErrMask;
 527         __be64 lemAction0;
 528         __be64 lemAction1;
 529         __be64 lemWof;
 530
 531         union {
 532                 struct OpalIoP7IOCRgcErrorData {
 533                         __be64 rgcStatus;       /* 3E1C10 */
 534                         __be64 rgcLdcp;         /* 3E1C18 */
 535                 }rgc;
 536                 struct OpalIoP7IOCBiErrorData {
 537                         __be64 biLdcp0;         /* 3C0100, 3C0118 */
 538                         __be64 biLdcp1;         /* 3C0108, 3C0120 */
 539                         __be64 biLdcp2;         /* 3C0110, 3C0128 */
 540                         __be64 biFenceStatus;   /* 3C0130, 3C0130 */
 541
 542                             u8 biDownbound;     /* BI Downbound or Upbound */
 543                 }bi;
 544                 struct OpalIoP7IOCCiErrorData {
 545                         __be64 ciPortStatus;    /* 3Dn008 */
 546                         __be64 ciPortLdcp;      /* 3Dn010 */
 547
 548                             u8 ciPort;          /* Index of CI port: 0/1 */
 549                 }ci;
 550         };
 551 };
 552
 553 /**
 554  * This structure defines the overlay which will be used to store PHB error
 555  * data upon request.
 556  */
 557 enum {
 558         OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
 559 };
 560
 561 enum {
 562         OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
 563         OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
 564 };
 565
 566 enum {
 567         OPAL_P7IOC_NUM_PEST_REGS = 128,
 568         OPAL_PHB3_NUM_PEST_REGS = 256
 569 };
 570
 571 /* CAPI modes for PHB */
 572 enum {
 573         OPAL_PHB_CAPI_MODE_PCIE         = 0,
 574         OPAL_PHB_CAPI_MODE_CAPI         = 1,
 575         OPAL_PHB_CAPI_MODE_SNOOP_OFF    = 2,
 576         OPAL_PHB_CAPI_MODE_SNOOP_ON     = 3,
 577 };
 578
 579 struct OpalIoPhbErrorCommon {
 580         __be32 version;
 581         __be32 ioType;
 582         __be32 len;
 583 };
 584
 585 struct OpalIoP7IOCPhbErrorData {
 586         struct OpalIoPhbErrorCommon common;
 587
 588         __be32 brdgCtl;
 589
 590         // P7IOC utl regs
 591         __be32 portStatusReg;
 592         __be32 rootCmplxStatus;
 593         __be32 busAgentStatus;
 594
 595         // P7IOC cfg regs
 596         __be32 deviceStatus;
 597         __be32 slotStatus;
 598         __be32 linkStatus;
 599         __be32 devCmdStatus;
 600         __be32 devSecStatus;
 601
 602         // cfg AER regs
 603         __be32 rootErrorStatus;
 604         __be32 uncorrErrorStatus;
 605         __be32 corrErrorStatus;
 606         __be32 tlpHdr1;
 607         __be32 tlpHdr2;
 608         __be32 tlpHdr3;
 609         __be32 tlpHdr4;
 610         __be32 sourceId;
 611
 612         __be32 rsv3;
 613
 614         // Record data about the call to allocate a buffer.
 615         __be64 errorClass;
 616         __be64 correlator;
 617
 618         //P7IOC MMIO Error Regs
 619         __be64 p7iocPlssr;                // n120
 620         __be64 p7iocCsr;                  // n110
 621         __be64 lemFir;                    // nC00
 622         __be64 lemErrorMask;              // nC18
 623         __be64 lemWOF;                    // nC40
 624         __be64 phbErrorStatus;            // nC80
 625         __be64 phbFirstErrorStatus;       // nC88
 626         __be64 phbErrorLog0;              // nCC0
 627         __be64 phbErrorLog1;              // nCC8
 628         __be64 mmioErrorStatus;           // nD00
 629         __be64 mmioFirstErrorStatus;      // nD08
 630         __be64 mmioErrorLog0;             // nD40
 631         __be64 mmioErrorLog1;             // nD48
 632         __be64 dma0ErrorStatus;           // nD80
 633         __be64 dma0FirstErrorStatus;      // nD88
 634         __be64 dma0ErrorLog0;             // nDC0
 635         __be64 dma0ErrorLog1;             // nDC8
 636         __be64 dma1ErrorStatus;           // nE00
 637         __be64 dma1FirstErrorStatus;      // nE08
 638         __be64 dma1ErrorLog0;             // nE40
 639         __be64 dma1ErrorLog1;             // nE48
 640         __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
 641         __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
 642 };
 643
 644 struct OpalIoPhb3ErrorData {
 645         struct OpalIoPhbErrorCommon common;
 646
 647         __be32 brdgCtl;
 648
 649         /* PHB3 UTL regs */
 650         __be32 portStatusReg;
 651         __be32 rootCmplxStatus;
 652         __be32 busAgentStatus;
 653
 654         /* PHB3 cfg regs */
 655         __be32 deviceStatus;
 656         __be32 slotStatus;
 657         __be32 linkStatus;
 658         __be32 devCmdStatus;
 659         __be32 devSecStatus;
 660
 661         /* cfg AER regs */
 662         __be32 rootErrorStatus;
 663         __be32 uncorrErrorStatus;
 664         __be32 corrErrorStatus;
 665         __be32 tlpHdr1;
 666         __be32 tlpHdr2;
 667         __be32 tlpHdr3;
 668         __be32 tlpHdr4;
 669         __be32 sourceId;
 670
 671         __be32 rsv3;
 672
 673         /* Record data about the call to allocate a buffer */
 674         __be64 errorClass;
 675         __be64 correlator;
 676
 677         __be64 nFir;                    /* 000 */
 678         __be64 nFirMask;                /* 003 */
 679         __be64 nFirWOF;         /* 008 */
 680
 681         /* PHB3 MMIO Error Regs */
 682         __be64 phbPlssr;                /* 120 */
 683         __be64 phbCsr;          /* 110 */
 684         __be64 lemFir;          /* C00 */
 685         __be64 lemErrorMask;            /* C18 */
 686         __be64 lemWOF;          /* C40 */
 687         __be64 phbErrorStatus;  /* C80 */
 688         __be64 phbFirstErrorStatus;     /* C88 */
 689         __be64 phbErrorLog0;            /* CC0 */
 690         __be64 phbErrorLog1;            /* CC8 */
 691         __be64 mmioErrorStatus; /* D00 */
 692         __be64 mmioFirstErrorStatus;    /* D08 */
 693         __be64 mmioErrorLog0;           /* D40 */
 694         __be64 mmioErrorLog1;           /* D48 */
 695         __be64 dma0ErrorStatus; /* D80 */
 696         __be64 dma0FirstErrorStatus;    /* D88 */
 697         __be64 dma0ErrorLog0;           /* DC0 */
 698         __be64 dma0ErrorLog1;           /* DC8 */
 699         __be64 dma1ErrorStatus; /* E00 */
 700         __be64 dma1FirstErrorStatus;    /* E08 */
 701         __be64 dma1ErrorLog0;           /* E40 */
 702         __be64 dma1ErrorLog1;           /* E48 */
 703         __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
 704         __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
 705 };
 706
 707 enum {
 708         OPAL_REINIT_CPUS_HILE_BE        = (1 << 0),
 709         OPAL_REINIT_CPUS_HILE_LE        = (1 << 1),
 710 };
 711
 712 typedef struct oppanel_line {
 713         const char *    line;
 714         uint64_t        line_len;
 715 } oppanel_line_t;
 716
 717 /*
 718  * SG entries
 719  *
 720  * WARNING: The current implementation requires each entry
 721  * to represent a block that is 4k aligned *and* each block
 722  * size except the last one in the list to be as well.
 723  */
 724 struct opal_sg_entry {
 725         __be64 data;
 726         __be64 length;
 727 };
 728
 729 /* SG list */
 730 struct opal_sg_list {
 731         __be64 length;
 732         __be64 next;
 733         struct opal_sg_entry entry[];
 734 };
 735
 736 /*
 737  * Dump region ID range usable by the OS
 738  */
 739 #define OPAL_DUMP_REGION_HOST_START             0x80
 740 #define OPAL_DUMP_REGION_LOG_BUF                0x80
 741 #define OPAL_DUMP_REGION_HOST_END               0xFF
 742
 743 /* OPAL I2C request */
 744 struct opal_i2c_request {
 745         uint8_t type;
 746 #define OPAL_I2C_RAW_READ       0
 747 #define OPAL_I2C_RAW_WRITE      1
 748 #define OPAL_I2C_SM_READ        2
 749 #define OPAL_I2C_SM_WRITE       3
 750         uint8_t flags;
 751 #define OPAL_I2C_ADDR_10        0x01    /* Not supported yet */
 752         uint8_t subaddr_sz;             /* Max 4 */
 753         uint8_t reserved;
 754         __be16 addr;                    /* 7 or 10 bit address */
 755         __be16 reserved2;
 756         __be32 subaddr;         /* Sub-address if any */
 757         __be32 size;                    /* Data size */
 758         __be64 buffer_ra;               /* Buffer real address */
 759 };
 760
 761 #endif /* __ASSEMBLY__ */
 762
 763 #endif /* __OPAL_API_H */