2 * PowerNV OPAL definitions.
4 * Copyright 2011 IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
15 /****** Takeover interface ********/
17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only).
20 * This is exclusively used in prom_init.c
25 struct opal_takeover_args {
29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */
39 * WARNING: The current implementation requires each entry
40 * to represent a block that is 4k aligned *and* each block
41 * size except the last one in the list to be as well.
43 struct opal_sg_entry {
50 unsigned long num_entries;
51 struct opal_sg_list *next;
52 struct opal_sg_entry entry[];
55 /* We calculate number of sg entries based on PAGE_SIZE */
56 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
58 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
60 extern long opal_do_takeover(struct opal_takeover_args *args);
63 extern int opal_enter_rtas(struct rtas_args *args,
67 #endif /* __ASSEMBLY__ */
69 /****** OPAL APIs ******/
72 #define OPAL_SUCCESS 0
73 #define OPAL_PARAMETER -1
75 #define OPAL_PARTIAL -3
76 #define OPAL_CONSTRAINED -4
77 #define OPAL_CLOSED -5
78 #define OPAL_HARDWARE -6
79 #define OPAL_UNSUPPORTED -7
80 #define OPAL_PERMISSION -8
81 #define OPAL_NO_MEM -9
82 #define OPAL_RESOURCE -10
83 #define OPAL_INTERNAL_ERROR -11
84 #define OPAL_BUSY_EVENT -12
85 #define OPAL_HARDWARE_FROZEN -13
86 #define OPAL_WRONG_STATE -14
87 #define OPAL_ASYNC_COMPLETION -15
89 /* API Tokens (in r0) */
90 #define OPAL_CONSOLE_WRITE 1
91 #define OPAL_CONSOLE_READ 2
92 #define OPAL_RTC_READ 3
93 #define OPAL_RTC_WRITE 4
94 #define OPAL_CEC_POWER_DOWN 5
95 #define OPAL_CEC_REBOOT 6
96 #define OPAL_READ_NVRAM 7
97 #define OPAL_WRITE_NVRAM 8
98 #define OPAL_HANDLE_INTERRUPT 9
99 #define OPAL_POLL_EVENTS 10
100 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
101 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
102 #define OPAL_PCI_CONFIG_READ_BYTE 13
103 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
104 #define OPAL_PCI_CONFIG_READ_WORD 15
105 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
106 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
107 #define OPAL_PCI_CONFIG_WRITE_WORD 18
108 #define OPAL_SET_XIVE 19
109 #define OPAL_GET_XIVE 20
110 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
111 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
112 #define OPAL_PCI_EEH_FREEZE_STATUS 23
113 #define OPAL_PCI_SHPC 24
114 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
115 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
116 #define OPAL_PCI_PHB_MMIO_ENABLE 27
117 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
118 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
119 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
120 #define OPAL_PCI_SET_PE 31
121 #define OPAL_PCI_SET_PELTV 32
122 #define OPAL_PCI_SET_MVE 33
123 #define OPAL_PCI_SET_MVE_ENABLE 34
124 #define OPAL_PCI_GET_XIVE_REISSUE 35
125 #define OPAL_PCI_SET_XIVE_REISSUE 36
126 #define OPAL_PCI_SET_XIVE_PE 37
127 #define OPAL_GET_XIVE_SOURCE 38
128 #define OPAL_GET_MSI_32 39
129 #define OPAL_GET_MSI_64 40
130 #define OPAL_START_CPU 41
131 #define OPAL_QUERY_CPU_STATUS 42
132 #define OPAL_WRITE_OPPANEL 43
133 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
134 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
135 #define OPAL_PCI_RESET 49
136 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
137 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
138 #define OPAL_PCI_FENCE_PHB 52
139 #define OPAL_PCI_REINIT 53
140 #define OPAL_PCI_MASK_PE_ERROR 54
141 #define OPAL_SET_SLOT_LED_STATUS 55
142 #define OPAL_GET_EPOW_STATUS 56
143 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
144 #define OPAL_RESERVED1 58
145 #define OPAL_RESERVED2 59
146 #define OPAL_PCI_NEXT_ERROR 60
147 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
148 #define OPAL_PCI_POLL 62
149 #define OPAL_PCI_MSI_EOI 63
150 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
151 #define OPAL_XSCOM_READ 65
152 #define OPAL_XSCOM_WRITE 66
153 #define OPAL_LPC_READ 67
154 #define OPAL_LPC_WRITE 68
155 #define OPAL_RETURN_CPU 69
156 #define OPAL_ELOG_READ 71
157 #define OPAL_ELOG_WRITE 72
158 #define OPAL_ELOG_ACK 73
159 #define OPAL_ELOG_RESEND 74
160 #define OPAL_ELOG_SIZE 75
161 #define OPAL_FLASH_VALIDATE 76
162 #define OPAL_FLASH_MANAGE 77
163 #define OPAL_FLASH_UPDATE 78
164 #define OPAL_RESYNC_TIMEBASE 79
165 #define OPAL_DUMP_INIT 81
166 #define OPAL_DUMP_INFO 82
167 #define OPAL_DUMP_READ 83
168 #define OPAL_DUMP_ACK 84
169 #define OPAL_GET_MSG 85
170 #define OPAL_CHECK_ASYNC_COMPLETION 86
171 #define OPAL_SYNC_HOST_REBOOT 87
172 #define OPAL_SENSOR_READ 88
173 #define OPAL_GET_PARAM 89
174 #define OPAL_SET_PARAM 90
175 #define OPAL_DUMP_RESEND 91
176 #define OPAL_DUMP_INFO2 94
181 enum OpalVendorApiTokens {
182 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
185 enum OpalFreezeState {
186 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
187 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
188 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
189 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
190 OPAL_EEH_STOPPED_RESET = 4,
191 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
192 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
195 enum OpalEehFreezeActionToken {
196 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
197 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
198 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
201 enum OpalPciStatusToken {
202 OPAL_EEH_NO_ERROR = 0,
203 OPAL_EEH_IOC_ERROR = 1,
204 OPAL_EEH_PHB_ERROR = 2,
205 OPAL_EEH_PE_ERROR = 3,
206 OPAL_EEH_PE_MMIO_ERROR = 4,
207 OPAL_EEH_PE_DMA_ERROR = 5
210 enum OpalPciErrorSeverity {
211 OPAL_EEH_SEV_NO_ERROR = 0,
212 OPAL_EEH_SEV_IOC_DEAD = 1,
213 OPAL_EEH_SEV_PHB_DEAD = 2,
214 OPAL_EEH_SEV_PHB_FENCED = 3,
215 OPAL_EEH_SEV_PE_ER = 4,
219 enum OpalShpcAction {
220 OPAL_SHPC_GET_LINK_STATE = 0,
221 OPAL_SHPC_GET_SLOT_STATE = 1
224 enum OpalShpcLinkState {
225 OPAL_SHPC_LINK_DOWN = 0,
226 OPAL_SHPC_LINK_UP = 1
229 enum OpalMmioWindowType {
230 OPAL_M32_WINDOW_TYPE = 1,
231 OPAL_M64_WINDOW_TYPE = 2,
232 OPAL_IO_WINDOW_TYPE = 3
235 enum OpalShpcSlotState {
236 OPAL_SHPC_DEV_NOT_PRESENT = 0,
237 OPAL_SHPC_DEV_PRESENT = 1
240 enum OpalExceptionHandler {
241 OPAL_MACHINE_CHECK_HANDLER = 1,
242 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
243 OPAL_SOFTPATCH_HANDLER = 3
246 enum OpalPendingState {
247 OPAL_EVENT_OPAL_INTERNAL = 0x1,
248 OPAL_EVENT_NVRAM = 0x2,
249 OPAL_EVENT_RTC = 0x4,
250 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
251 OPAL_EVENT_CONSOLE_INPUT = 0x10,
252 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
253 OPAL_EVENT_ERROR_LOG = 0x40,
254 OPAL_EVENT_EPOW = 0x80,
255 OPAL_EVENT_LED_STATUS = 0x100,
256 OPAL_EVENT_PCI_ERROR = 0x200,
257 OPAL_EVENT_DUMP_AVAIL = 0x400,
258 OPAL_EVENT_MSG_PENDING = 0x800,
261 enum OpalMessageType {
262 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
263 * additional params function-specific
271 /* Machine check related definitions */
272 enum OpalMCE_Version {
276 enum OpalMCE_Severity {
277 OpalMCE_SEV_NO_ERROR = 0,
278 OpalMCE_SEV_WARNING = 1,
279 OpalMCE_SEV_ERROR_SYNC = 2,
280 OpalMCE_SEV_FATAL = 3,
283 enum OpalMCE_Disposition {
284 OpalMCE_DISPOSITION_RECOVERED = 0,
285 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
288 enum OpalMCE_Initiator {
289 OpalMCE_INITIATOR_UNKNOWN = 0,
290 OpalMCE_INITIATOR_CPU = 1,
293 enum OpalMCE_ErrorType {
294 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
295 OpalMCE_ERROR_TYPE_UE = 1,
296 OpalMCE_ERROR_TYPE_SLB = 2,
297 OpalMCE_ERROR_TYPE_ERAT = 3,
298 OpalMCE_ERROR_TYPE_TLB = 4,
301 enum OpalMCE_UeErrorType {
302 OpalMCE_UE_ERROR_INDETERMINATE = 0,
303 OpalMCE_UE_ERROR_IFETCH = 1,
304 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
305 OpalMCE_UE_ERROR_LOAD_STORE = 3,
306 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
309 enum OpalMCE_SlbErrorType {
310 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
311 OpalMCE_SLB_ERROR_PARITY = 1,
312 OpalMCE_SLB_ERROR_MULTIHIT = 2,
315 enum OpalMCE_EratErrorType {
316 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
317 OpalMCE_ERAT_ERROR_PARITY = 1,
318 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
321 enum OpalMCE_TlbErrorType {
322 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
323 OpalMCE_TLB_ERROR_PARITY = 1,
324 OpalMCE_TLB_ERROR_MULTIHIT = 2,
327 enum OpalThreadStatus {
328 OPAL_THREAD_INACTIVE = 0x0,
329 OPAL_THREAD_STARTED = 0x1,
330 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
333 enum OpalPciBusCompare {
334 OpalPciBusAny = 0, /* Any bus number match */
335 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
336 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
337 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
338 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
339 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
340 OpalPciBusAll = 7, /* Match bus number exactly */
343 enum OpalDeviceCompare {
344 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
345 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
348 enum OpalFuncCompare {
349 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
350 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
358 enum OpalPeltvAction {
359 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
360 OPAL_ADD_PE_TO_DOMAIN = 1
363 enum OpalMveEnableAction {
364 OPAL_DISABLE_MVE = 0,
368 enum OpalPciResetScope {
369 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
370 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
371 OPAL_PCI_IODA_TABLE_RESET = 6,
374 enum OpalPciReinitScope {
375 OPAL_REINIT_PCI_DEV = 1000
378 enum OpalPciResetState {
379 OPAL_DEASSERT_RESET = 0,
380 OPAL_ASSERT_RESET = 1
383 enum OpalPciMaskAction {
384 OPAL_UNMASK_ERROR_TYPE = 0,
385 OPAL_MASK_ERROR_TYPE = 1
388 enum OpalSlotLedType {
389 OPAL_SLOT_LED_ID_TYPE = 0,
390 OPAL_SLOT_LED_FAULT_TYPE = 1
394 OPAL_TURN_OFF_LED = 0,
395 OPAL_TURN_ON_LED = 1,
396 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
399 enum OpalEpowStatus {
402 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
403 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
407 * Address cycle types for LPC accesses. These also correspond
408 * to the content of the first cell of the "reg" property for
409 * device nodes on the LPC bus
411 enum OpalLPCAddressType {
417 /* System parameter permission */
418 enum OpalSysparamPerm {
419 OPAL_SYSPARAM_READ = 0x1,
420 OPAL_SYSPARAM_WRITE = 0x2,
421 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
430 struct opal_machine_check_event {
431 enum OpalMCE_Version version:8; /* 0x00 */
432 uint8_t in_use; /* 0x01 */
433 enum OpalMCE_Severity severity:8; /* 0x02 */
434 enum OpalMCE_Initiator initiator:8; /* 0x03 */
435 enum OpalMCE_ErrorType error_type:8; /* 0x04 */
436 enum OpalMCE_Disposition disposition:8; /* 0x05 */
437 uint8_t reserved_1[2]; /* 0x06 */
438 uint64_t gpr3; /* 0x08 */
439 uint64_t srr0; /* 0x10 */
440 uint64_t srr1; /* 0x18 */
443 enum OpalMCE_UeErrorType ue_error_type:8;
444 uint8_t effective_address_provided;
445 uint8_t physical_address_provided;
446 uint8_t reserved_1[5];
447 uint64_t effective_address;
448 uint64_t physical_address;
449 uint8_t reserved_2[8];
453 enum OpalMCE_SlbErrorType slb_error_type:8;
454 uint8_t effective_address_provided;
455 uint8_t reserved_1[6];
456 uint64_t effective_address;
457 uint8_t reserved_2[16];
461 enum OpalMCE_EratErrorType erat_error_type:8;
462 uint8_t effective_address_provided;
463 uint8_t reserved_1[6];
464 uint64_t effective_address;
465 uint8_t reserved_2[16];
469 enum OpalMCE_TlbErrorType tlb_error_type:8;
470 uint8_t effective_address_provided;
471 uint8_t reserved_1[6];
472 uint64_t effective_address;
473 uint8_t reserved_2[16];
478 /* FSP memory errors handling */
479 enum OpalMemErr_Version {
483 enum OpalMemErrType {
484 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
485 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
486 OPAL_MEM_ERR_TYPE_SCRUB,
489 /* Memory Reilience error type */
490 enum OpalMemErr_ResilErrType {
491 OPAL_MEM_RESILIENCE_CE = 0,
492 OPAL_MEM_RESILIENCE_UE,
493 OPAL_MEM_RESILIENCE_UE_SCRUB,
496 /* Dynamic Memory Deallocation type */
497 enum OpalMemErr_DynErrType {
498 OPAL_MEM_DYNAMIC_DEALLOC = 0,
501 /* OpalMemoryErrorData->flags */
502 #define OPAL_MEM_CORRECTED_ERROR 0x0001
503 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
504 #define OPAL_MEM_ACK_REQUIRED 0x8000
506 struct OpalMemoryErrorData {
507 enum OpalMemErr_Version version:8; /* 0x00 */
508 enum OpalMemErrType type:8; /* 0x01 */
509 uint16_t flags; /* 0x02 */
510 uint8_t reserved_1[4]; /* 0x04 */
513 /* Memory Resilience corrected/uncorrected error info */
515 enum OpalMemErr_ResilErrType resil_err_type:8;
516 uint8_t reserved_1[7];
517 uint64_t physical_address_start;
518 uint64_t physical_address_end;
520 /* Dynamic memory deallocation error info */
522 enum OpalMemErr_DynErrType dyn_err_type:8;
523 uint8_t reserved_1[7];
524 uint64_t physical_address_start;
525 uint64_t physical_address_end;
531 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
532 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
533 OPAL_P7IOC_DIAG_TYPE_BI = 2,
534 OPAL_P7IOC_DIAG_TYPE_CI = 3,
535 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
536 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
537 OPAL_P7IOC_DIAG_TYPE_LAST = 6
540 struct OpalIoP7IOCErrorData {
558 struct OpalIoP7IOCRgcErrorData {
559 uint64_t rgcStatus; /* 3E1C10 */
560 uint64_t rgcLdcp; /* 3E1C18 */
562 struct OpalIoP7IOCBiErrorData {
563 uint64_t biLdcp0; /* 3C0100, 3C0118 */
564 uint64_t biLdcp1; /* 3C0108, 3C0120 */
565 uint64_t biLdcp2; /* 3C0110, 3C0128 */
566 uint64_t biFenceStatus; /* 3C0130, 3C0130 */
568 uint8_t biDownbound; /* BI Downbound or Upbound */
570 struct OpalIoP7IOCCiErrorData {
571 uint64_t ciPortStatus; /* 3Dn008 */
572 uint64_t ciPortLdcp; /* 3Dn010 */
574 uint8_t ciPort; /* Index of CI port: 0/1 */
580 * This structure defines the overlay which will be used to store PHB error
584 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
588 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
589 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
593 OPAL_P7IOC_NUM_PEST_REGS = 128,
594 OPAL_PHB3_NUM_PEST_REGS = 256
597 struct OpalIoPhbErrorCommon {
603 struct OpalIoP7IOCPhbErrorData {
604 struct OpalIoPhbErrorCommon common;
609 uint32_t portStatusReg;
610 uint32_t rootCmplxStatus;
611 uint32_t busAgentStatus;
614 uint32_t deviceStatus;
617 uint32_t devCmdStatus;
618 uint32_t devSecStatus;
621 uint32_t rootErrorStatus;
622 uint32_t uncorrErrorStatus;
623 uint32_t corrErrorStatus;
632 // Record data about the call to allocate a buffer.
636 //P7IOC MMIO Error Regs
637 uint64_t p7iocPlssr; // n120
638 uint64_t p7iocCsr; // n110
639 uint64_t lemFir; // nC00
640 uint64_t lemErrorMask; // nC18
641 uint64_t lemWOF; // nC40
642 uint64_t phbErrorStatus; // nC80
643 uint64_t phbFirstErrorStatus; // nC88
644 uint64_t phbErrorLog0; // nCC0
645 uint64_t phbErrorLog1; // nCC8
646 uint64_t mmioErrorStatus; // nD00
647 uint64_t mmioFirstErrorStatus; // nD08
648 uint64_t mmioErrorLog0; // nD40
649 uint64_t mmioErrorLog1; // nD48
650 uint64_t dma0ErrorStatus; // nD80
651 uint64_t dma0FirstErrorStatus; // nD88
652 uint64_t dma0ErrorLog0; // nDC0
653 uint64_t dma0ErrorLog1; // nDC8
654 uint64_t dma1ErrorStatus; // nE00
655 uint64_t dma1FirstErrorStatus; // nE08
656 uint64_t dma1ErrorLog0; // nE40
657 uint64_t dma1ErrorLog1; // nE48
658 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
659 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
662 struct OpalIoPhb3ErrorData {
663 struct OpalIoPhbErrorCommon common;
668 uint32_t portStatusReg;
669 uint32_t rootCmplxStatus;
670 uint32_t busAgentStatus;
673 uint32_t deviceStatus;
676 uint32_t devCmdStatus;
677 uint32_t devSecStatus;
680 uint32_t rootErrorStatus;
681 uint32_t uncorrErrorStatus;
682 uint32_t corrErrorStatus;
691 /* Record data about the call to allocate a buffer */
695 uint64_t nFir; /* 000 */
696 uint64_t nFirMask; /* 003 */
697 uint64_t nFirWOF; /* 008 */
699 /* PHB3 MMIO Error Regs */
700 uint64_t phbPlssr; /* 120 */
701 uint64_t phbCsr; /* 110 */
702 uint64_t lemFir; /* C00 */
703 uint64_t lemErrorMask; /* C18 */
704 uint64_t lemWOF; /* C40 */
705 uint64_t phbErrorStatus; /* C80 */
706 uint64_t phbFirstErrorStatus; /* C88 */
707 uint64_t phbErrorLog0; /* CC0 */
708 uint64_t phbErrorLog1; /* CC8 */
709 uint64_t mmioErrorStatus; /* D00 */
710 uint64_t mmioFirstErrorStatus; /* D08 */
711 uint64_t mmioErrorLog0; /* D40 */
712 uint64_t mmioErrorLog1; /* D48 */
713 uint64_t dma0ErrorStatus; /* D80 */
714 uint64_t dma0FirstErrorStatus; /* D88 */
715 uint64_t dma0ErrorLog0; /* DC0 */
716 uint64_t dma0ErrorLog1; /* DC8 */
717 uint64_t dma1ErrorStatus; /* E00 */
718 uint64_t dma1FirstErrorStatus; /* E08 */
719 uint64_t dma1ErrorLog0; /* E40 */
720 uint64_t dma1ErrorLog1; /* E48 */
721 uint64_t pestA[OPAL_PHB3_NUM_PEST_REGS];
722 uint64_t pestB[OPAL_PHB3_NUM_PEST_REGS];
725 typedef struct oppanel_line {
730 /* /sys/firmware/opal */
731 extern struct kobject *opal_kobj;
734 int64_t opal_console_write(int64_t term_number, __be64 *length,
735 const uint8_t *buffer);
736 int64_t opal_console_read(int64_t term_number, __be64 *length,
738 int64_t opal_console_write_buffer_space(int64_t term_number,
740 int64_t opal_rtc_read(__be32 *year_month_day,
741 __be64 *hour_minute_second_millisecond);
742 int64_t opal_rtc_write(uint32_t year_month_day,
743 uint64_t hour_minute_second_millisecond);
744 int64_t opal_cec_power_down(uint64_t request);
745 int64_t opal_cec_reboot(void);
746 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
747 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
748 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
749 int64_t opal_poll_events(__be64 *outstanding_event_mask);
750 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
751 uint64_t tce_mem_size);
752 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
753 uint64_t tce_mem_size);
754 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
755 uint64_t offset, uint8_t *data);
756 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
757 uint64_t offset, __be16 *data);
758 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
759 uint64_t offset, __be32 *data);
760 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
761 uint64_t offset, uint8_t data);
762 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
763 uint64_t offset, uint16_t data);
764 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
765 uint64_t offset, uint32_t data);
766 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
767 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
768 int64_t opal_register_exception_handler(uint64_t opal_exception,
769 uint64_t handler_address,
770 uint64_t glue_cache_line);
771 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
772 uint8_t *freeze_state,
773 __be16 *pci_error_type,
775 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
776 uint64_t eeh_action_token);
777 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
781 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
782 uint16_t window_num, uint16_t enable);
783 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
785 uint64_t starting_real_address,
786 uint64_t starting_pci_address,
787 uint16_t segment_size);
788 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
789 uint16_t window_type, uint16_t window_num,
790 uint16_t segment_num);
791 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
792 uint64_t ivt_addr, uint64_t ivt_len,
793 uint64_t reject_array_addr,
794 uint64_t peltv_addr);
795 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
796 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
798 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
800 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
801 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
803 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
804 uint8_t *p_bit, uint8_t *q_bit);
805 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
806 uint8_t p_bit, uint8_t q_bit);
807 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
808 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
810 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
811 __be32 *interrupt_source_number);
812 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
813 uint8_t msi_range, __be32 *msi_address,
814 __be32 *message_data);
815 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
816 uint32_t xive_num, uint8_t msi_range,
817 __be64 *msi_address, __be32 *message_data);
818 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
819 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
820 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
821 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
822 uint16_t tce_levels, uint64_t tce_table_addr,
823 uint64_t tce_table_size, uint64_t tce_page_size);
824 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
825 uint16_t dma_window_number, uint64_t pci_start_addr,
826 uint64_t pci_mem_size);
827 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
829 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
830 uint64_t diag_buffer_len);
831 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
832 uint64_t diag_buffer_len);
833 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
834 uint64_t diag_buffer_len);
835 int64_t opal_pci_fence_phb(uint64_t phb_id);
836 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
837 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
838 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
839 int64_t opal_get_epow_status(__be64 *status);
840 int64_t opal_set_system_attention_led(uint8_t led_action);
841 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
842 uint16_t *pci_error_type, uint16_t *severity);
843 int64_t opal_pci_poll(uint64_t phb_id);
844 int64_t opal_return_cpu(void);
846 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
847 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
849 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
850 uint32_t addr, uint32_t data, uint32_t sz);
851 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
852 uint32_t addr, __be32 *data, uint32_t sz);
854 int64_t opal_read_elog(uint64_t buffer, size_t size, uint64_t log_id);
855 int64_t opal_get_elog_size(uint64_t *log_id, size_t *size, uint64_t *elog_type);
856 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
857 int64_t opal_send_ack_elog(uint64_t log_id);
858 void opal_resend_pending_logs(void);
860 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
861 int64_t opal_manage_flash(uint8_t op);
862 int64_t opal_update_flash(uint64_t blk_list);
863 int64_t opal_dump_init(uint8_t dump_type);
864 int64_t opal_dump_info(uint32_t *dump_id, uint32_t *dump_size);
865 int64_t opal_dump_info2(uint32_t *dump_id, uint32_t *dump_size, uint32_t *dump_type);
866 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
867 int64_t opal_dump_ack(uint32_t dump_id);
868 int64_t opal_dump_resend_notification(void);
870 int64_t opal_get_msg(uint64_t buffer, size_t size);
871 int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
872 int64_t opal_sync_host_reboot(void);
873 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
875 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
877 int64_t opal_sensor_read(uint32_t sensor_hndl, int token,
878 uint32_t *sensor_data);
880 /* Internal functions */
881 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
882 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
883 const char *uname, int depth, void *data);
885 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
886 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
888 extern void hvc_opal_init_early(void);
890 /* Internal functions */
891 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
892 int depth, void *data);
894 extern int opal_notifier_register(struct notifier_block *nb);
895 extern int opal_notifier_unregister(struct notifier_block *nb);
897 extern int opal_message_notifier_register(enum OpalMessageType msg_type,
898 struct notifier_block *nb);
899 extern void opal_notifier_enable(void);
900 extern void opal_notifier_disable(void);
901 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
903 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
904 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
906 extern int __opal_async_get_token(void);
907 extern int opal_async_get_token_interruptible(void);
908 extern int __opal_async_release_token(int token);
909 extern int opal_async_release_token(int token);
910 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
911 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
913 extern void hvc_opal_init_early(void);
916 extern int opal_set_rtc_time(struct rtc_time *tm);
917 extern void opal_get_rtc_time(struct rtc_time *tm);
918 extern unsigned long opal_get_boot_time(void);
919 extern void opal_nvram_init(void);
920 extern void opal_flash_init(void);
921 extern int opal_elog_init(void);
922 extern void opal_platform_dump_init(void);
923 extern void opal_sys_param_init(void);
925 extern int opal_machine_check(struct pt_regs *regs);
926 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
928 extern void opal_shutdown(void);
929 extern int opal_resync_timebase(void);
931 extern void opal_lpc_init(void);
933 #endif /* __ASSEMBLY__ */
935 #endif /* __OPAL_H */