2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
4 #ifndef _ASM_POWERPC_PPC_ASM_H
5 #define _ASM_POWERPC_PPC_ASM_H
7 #include <linux/init.h>
8 #include <linux/stringify.h>
9 #include <asm/asm-compat.h>
10 #include <asm/processor.h>
11 #include <asm/ppc-opcode.h>
12 #include <asm/firmware.h>
15 #error __FILE__ should only be used in assembler files
18 #define SZL (BITS_PER_LONG/8)
21 * Stuff for accurate CPU time accounting.
22 * These macros handle transitions between user and system state
23 * in exception entry and exit and accumulate time to the
24 * user_time and system_time fields in the paca.
27 #ifndef CONFIG_VIRT_CPU_ACCOUNTING
28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb)
29 #define ACCOUNT_CPU_USER_EXIT(ra, rb)
30 #define ACCOUNT_STOLEN_TIME
32 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \
33 beq 2f; /* if from kernel mode */ \
34 MFTB(ra); /* get timebase */ \
35 ld rb,PACA_STARTTIME_USER(r13); \
36 std ra,PACA_STARTTIME(r13); \
37 subf rb,rb,ra; /* subtract start value */ \
38 ld ra,PACA_USER_TIME(r13); \
39 add ra,ra,rb; /* add on to user time */ \
40 std ra,PACA_USER_TIME(r13); \
43 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \
44 MFTB(ra); /* get timebase */ \
45 ld rb,PACA_STARTTIME(r13); \
46 std ra,PACA_STARTTIME_USER(r13); \
47 subf rb,rb,ra; /* subtract start value */ \
48 ld ra,PACA_SYSTEM_TIME(r13); \
49 add ra,ra,rb; /* add on to system time */ \
50 std ra,PACA_SYSTEM_TIME(r13)
52 #ifdef CONFIG_PPC_SPLPAR
53 #define ACCOUNT_STOLEN_TIME \
54 BEGIN_FW_FTR_SECTION; \
56 /* from user - see if there are any DTL entries to process */ \
57 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \
58 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \
59 ld r10,LPPACA_DTLIDX(r10); /* get log write index */ \
62 bl .accumulate_stolen_time; \
64 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \
66 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
68 #else /* CONFIG_PPC_SPLPAR */
69 #define ACCOUNT_STOLEN_TIME
71 #endif /* CONFIG_PPC_SPLPAR */
73 #endif /* CONFIG_VIRT_CPU_ACCOUNTING */
76 * Macros for storing registers into and loading registers from
80 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
81 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
82 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
83 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
85 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
86 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
87 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
89 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
93 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
94 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
95 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
96 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
97 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
98 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
99 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
100 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
102 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
103 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
104 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
105 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
106 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
107 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
108 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
109 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
110 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
111 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
112 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
113 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
115 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b
116 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
117 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
118 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
119 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
120 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
121 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b
122 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
123 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
124 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
125 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
126 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
128 /* Save the lower 32 VSRs in the thread VSR region */
129 #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,base,b)
130 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
131 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
132 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
133 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
134 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
135 #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b)
136 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
137 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
138 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
139 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
140 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
141 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
142 #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,base,b)
143 #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
144 #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
145 #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
146 #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
147 #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
148 #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b)
149 #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
150 #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
151 #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
152 #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
153 #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
156 * b = base register for addressing, o = base offset from register of 1st EVR
157 * n = first EVR, s = scratch
159 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b)
160 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
161 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
162 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
163 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
164 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
165 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n
166 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
167 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
168 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
169 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
170 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
172 /* Macros to adjust thread priority for hardware multithreading */
173 #define HMT_VERY_LOW or 31,31,31 # very low priority
174 #define HMT_LOW or 1,1,1
175 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
176 #define HMT_MEDIUM or 2,2,2
177 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
178 #define HMT_HIGH or 3,3,3
179 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only
184 #define XGLUE(a,b) a##b
185 #define GLUE(a,b) XGLUE(a,b)
187 #define _GLOBAL(name) \
191 .globl GLUE(.,name); \
192 .section ".opd","aw"; \
194 .quad GLUE(.,name); \
195 .quad .TOC.@tocbase; \
198 .type GLUE(.,name),@function; \
201 #define _INIT_GLOBAL(name) \
205 .globl GLUE(.,name); \
206 .section ".opd","aw"; \
208 .quad GLUE(.,name); \
209 .quad .TOC.@tocbase; \
212 .type GLUE(.,name),@function; \
215 #define _KPROBE(name) \
216 .section ".kprobes.text","a"; \
219 .globl GLUE(.,name); \
220 .section ".opd","aw"; \
222 .quad GLUE(.,name); \
223 .quad .TOC.@tocbase; \
226 .type GLUE(.,name),@function; \
229 #define _STATIC(name) \
232 .section ".opd","aw"; \
234 .quad GLUE(.,name); \
235 .quad .TOC.@tocbase; \
238 .type GLUE(.,name),@function; \
241 #define _INIT_STATIC(name) \
244 .section ".opd","aw"; \
246 .quad GLUE(.,name); \
247 .quad .TOC.@tocbase; \
250 .type GLUE(.,name),@function; \
261 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
266 .section ".kprobes.text","a"; \
273 * LOAD_REG_IMMEDIATE(rn, expr)
274 * Loads the value of the constant expression 'expr' into register 'rn'
275 * using immediate instructions only. Use this when it's important not
276 * to reference other data (i.e. on ppc64 when the TOC pointer is not
277 * valid) and when 'expr' is a constant or absolute address.
279 * LOAD_REG_ADDR(rn, name)
280 * Loads the address of label 'name' into register 'rn'. Use this when
281 * you don't particularly need immediate instructions only, but you need
282 * the whole address in one register (e.g. it's a structure address and
283 * you want to access various offsets within it). On ppc32 this is
284 * identical to LOAD_REG_IMMEDIATE.
286 * LOAD_REG_ADDRBASE(rn, name)
288 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into
289 * register 'rn'. ADDROFF(name) returns the remainder of the address as
290 * a constant expression. ADDROFF(name) is a signed expression < 16 bits
291 * in size, so is suitable for use directly as an offset in load and store
292 * instructions. Use this when loading/storing a single word or less as:
293 * LOAD_REG_ADDRBASE(rX, name)
294 * ld rY,ADDROFF(name)(rX)
297 #define LOAD_REG_IMMEDIATE(reg,expr) \
298 lis (reg),(expr)@highest; \
299 ori (reg),(reg),(expr)@higher; \
300 rldicr (reg),(reg),32,31; \
301 oris (reg),(reg),(expr)@h; \
302 ori (reg),(reg),(expr)@l;
304 #define LOAD_REG_ADDR(reg,name) \
305 ld (reg),name@got(r2)
307 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name)
308 #define ADDROFF(name) 0
310 /* offsets for stack frame layout */
315 #define LOAD_REG_IMMEDIATE(reg,expr) \
316 lis (reg),(expr)@ha; \
317 addi (reg),(reg),(expr)@l;
319 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name)
321 #define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha
322 #define ADDROFF(name) name@l
324 /* offsets for stack frame layout */
329 /* various errata or part fixups */
330 #ifdef CONFIG_PPC601_SYNC_FIX
335 END_FTR_SECTION_IFSET(CPU_FTR_601)
339 END_FTR_SECTION_IFSET(CPU_FTR_601)
343 END_FTR_SECTION_IFSET(CPU_FTR_601)
350 #ifdef CONFIG_PPC_CELL
353 BEGIN_FTR_SECTION_NESTED(96); \
356 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
358 #define MFTB(dest) mftb dest
363 #else /* CONFIG_SMP */
364 /* tlbsync is not implemented on 601 */
369 END_FTR_SECTION_IFCLR(CPU_FTR_601)
373 #define MTOCRF(FXM, RS) \
374 BEGIN_FTR_SECTION_NESTED(848); \
376 FTR_SECTION_ELSE_NESTED(848); \
377 mtocrf (FXM), (RS); \
378 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
382 * This instruction is not implemented on the PPC 603 or 601; however, on
383 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
384 * All of these instructions exist in the 8xx, they have magical powers,
385 * and they must be used.
388 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
392 lis r4,KERNELBASE@h; \
399 #ifdef CONFIG_IBM440EP_ERR42
400 #define PPC440EP_ERR42 isync
402 #define PPC440EP_ERR42
406 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
407 * keep the address intact to be compatible with code shared with
410 * On the other hand, I find it useful to have them behave as expected
411 * by their name (ie always do the addition) on 64-bit BookE
413 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
418 * We use addis to ensure compatibility with the "classic" ppc versions of
419 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
420 * converting the address in r0, and so this version has to do that too
421 * (i.e. set register rd to 0 when rs == 0).
423 #define tophys(rd,rs) \
426 #define tovirt(rd,rs) \
429 #elif defined(CONFIG_PPC64)
430 #define toreal(rd) /* we can access c000... in real mode */
433 #define tophys(rd,rs) \
436 #define tovirt(rd,rs) \
438 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
442 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
443 * physical base address of RAM at compile time.
445 #define toreal(rd) tophys(rd,rd)
446 #define fromreal(rd) tovirt(rd,rd)
448 #define tophys(rd,rs) \
449 0: addis rd,rs,-PAGE_OFFSET@h; \
450 .section ".vtop_fixup","aw"; \
455 #define tovirt(rd,rs) \
456 0: addis rd,rs,PAGE_OFFSET@h; \
457 .section ".ptov_fixup","aw"; \
463 #ifdef CONFIG_PPC_BOOK3S_64
465 #define MTMSRD(r) mtmsrd r
467 #define FIX_SRR1(ra, rb)
471 #define RFI rfi; b . /* Prevent prefetch past rfi */
473 #define MTMSRD(r) mtmsr r
477 #endif /* __KERNEL__ */
479 /* The boring bits... */
481 /* Condition Register Bit Fields */
493 /* General Purpose Registers (GPRs) */
529 /* Floating Point Registers (FPRs) */
564 /* AltiVec Registers (VPRs) */
599 /* VSX Registers (VSRs) */
666 /* SPE Registers (EVPRs) */
701 /* some stab codes */
707 #endif /* __ASSEMBLY__ */
709 #endif /* _ASM_POWERPC_PPC_ASM_H */