2 * The file intends to implement PE based on the information from
3 * platforms. Basically, there have 3 types of PEs: PHB/Bus/Device.
4 * All the PEs should be organized as hierarchy tree. The first level
5 * of the tree will be associated to existing PHBs since the particular
6 * PE is only meaningful in one PHB domain.
8 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/delay.h>
26 #include <linux/export.h>
27 #include <linux/gfp.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/string.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/ppc-pci.h>
35 static int eeh_pe_aux_size = 0;
36 static LIST_HEAD(eeh_phb_pe);
39 * eeh_set_pe_aux_size - Set PE auxillary data size
40 * @size: PE auxillary data size
42 * Set PE auxillary data size
44 void eeh_set_pe_aux_size(int size)
49 eeh_pe_aux_size = size;
53 * eeh_pe_alloc - Allocate PE
54 * @phb: PCI controller
57 * Allocate PE instance dynamically.
59 static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type)
64 alloc_size = sizeof(struct eeh_pe);
65 if (eeh_pe_aux_size) {
66 alloc_size = ALIGN(alloc_size, cache_line_size());
67 alloc_size += eeh_pe_aux_size;
71 pe = kzalloc(alloc_size, GFP_KERNEL);
74 /* Initialize PHB PE */
77 INIT_LIST_HEAD(&pe->child_list);
78 INIT_LIST_HEAD(&pe->child);
79 INIT_LIST_HEAD(&pe->edevs);
81 pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe),
87 * eeh_phb_pe_create - Create PHB PE
88 * @phb: PCI controller
90 * The function should be called while the PHB is detected during
91 * system boot or PCI hotplug in order to create PHB PE.
93 int eeh_phb_pe_create(struct pci_controller *phb)
98 pe = eeh_pe_alloc(phb, EEH_PE_PHB);
100 pr_err("%s: out of memory!\n", __func__);
104 /* Put it into the list */
105 list_add_tail(&pe->child, &eeh_phb_pe);
107 pr_debug("EEH: Add PE for PHB#%d\n", phb->global_number);
113 * eeh_phb_pe_get - Retrieve PHB PE based on the given PHB
114 * @phb: PCI controller
116 * The overall PEs form hierarchy tree. The first layer of the
117 * hierarchy tree is composed of PHB PEs. The function is used
118 * to retrieve the corresponding PHB PE according to the given PHB.
120 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
124 list_for_each_entry(pe, &eeh_phb_pe, child) {
126 * Actually, we needn't check the type since
127 * the PE for PHB has been determined when that
130 if ((pe->type & EEH_PE_PHB) && pe->phb == phb)
138 * eeh_pe_next - Retrieve the next PE in the tree
142 * The function is used to retrieve the next PE in the
145 static struct eeh_pe *eeh_pe_next(struct eeh_pe *pe,
148 struct list_head *next = pe->child_list.next;
150 if (next == &pe->child_list) {
154 next = pe->child.next;
155 if (next != &pe->parent->child_list)
161 return list_entry(next, struct eeh_pe, child);
165 * eeh_pe_traverse - Traverse PEs in the specified PHB
168 * @flag: extra parameter to callback
170 * The function is used to traverse the specified PE and its
171 * child PEs. The traversing is to be terminated once the
172 * callback returns something other than NULL, or no more PEs
175 void *eeh_pe_traverse(struct eeh_pe *root,
176 eeh_traverse_func fn, void *flag)
181 for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
190 * eeh_pe_dev_traverse - Traverse the devices from the PE
192 * @fn: function callback
193 * @flag: extra parameter to callback
195 * The function is used to traverse the devices of the specified
196 * PE and its child PEs.
198 void *eeh_pe_dev_traverse(struct eeh_pe *root,
199 eeh_traverse_func fn, void *flag)
202 struct eeh_dev *edev, *tmp;
206 pr_warn("%s: Invalid PE %p\n",
211 /* Traverse root PE */
212 for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
213 eeh_pe_for_each_dev(pe, edev, tmp) {
214 ret = fn(edev, flag);
224 * __eeh_pe_get - Check the PE address
228 * For one particular PE, it can be identified by PE address
229 * or tranditional BDF address. BDF address is composed of
230 * Bus/Device/Function number. The extra data referred by flag
231 * indicates which type of address should be used.
233 static void *__eeh_pe_get(void *data, void *flag)
235 struct eeh_pe *pe = (struct eeh_pe *)data;
236 struct eeh_dev *edev = (struct eeh_dev *)flag;
238 /* Unexpected PHB PE */
239 if (pe->type & EEH_PE_PHB)
243 * We prefer PE address. For most cases, we should
244 * have non-zero PE address
246 if (eeh_has_flag(EEH_VALID_PE_ZERO)) {
247 if (edev->pe_config_addr == pe->addr)
250 if (edev->pe_config_addr &&
251 (edev->pe_config_addr == pe->addr))
255 /* Try BDF address */
256 if (edev->config_addr &&
257 (edev->config_addr == pe->config_addr))
264 * eeh_pe_get - Search PE based on the given address
267 * Search the corresponding PE based on the specified address which
268 * is included in the eeh device. The function is used to check if
269 * the associated PE has been created against the PE address. It's
270 * notable that the PE address has 2 format: traditional PE address
271 * which is composed of PCI bus/device/function number, or unified
274 struct eeh_pe *eeh_pe_get(struct eeh_dev *edev)
276 struct eeh_pe *root = eeh_phb_pe_get(edev->phb);
279 pe = eeh_pe_traverse(root, __eeh_pe_get, edev);
285 * eeh_pe_get_parent - Retrieve the parent PE
288 * The whole PEs existing in the system are organized as hierarchy
289 * tree. The function is used to retrieve the parent PE according
290 * to the parent EEH device.
292 static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
294 struct eeh_dev *parent;
295 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
298 * It might have the case for the indirect parent
299 * EEH device already having associated PE, but
300 * the direct parent EEH device doesn't have yet.
302 pdn = pdn ? pdn->parent : NULL;
304 /* We're poking out of PCI territory */
305 parent = pdn_to_eeh_dev(pdn);
319 * eeh_add_to_parent_pe - Add EEH device to parent PE
322 * Add EEH device to the parent PE. If the parent PE already
323 * exists, the PE type will be changed to EEH_PE_BUS. Otherwise,
324 * we have to create new PE to hold the EEH device and the new
325 * PE will be linked to its parent PE as well.
327 int eeh_add_to_parent_pe(struct eeh_dev *edev)
329 struct eeh_pe *pe, *parent;
331 /* Check if the PE number is valid */
332 if (!eeh_has_flag(EEH_VALID_PE_ZERO) && !edev->pe_config_addr) {
333 pr_err("%s: Invalid PE#0 for edev 0x%x on PHB#%d\n",
334 __func__, edev->config_addr, edev->phb->global_number);
339 * Search the PE has been existing or not according
340 * to the PE address. If that has been existing, the
341 * PE should be composed of PCI bus and its subordinate
344 pe = eeh_pe_get(edev);
345 if (pe && !(pe->type & EEH_PE_INVALID)) {
346 /* Mark the PE as type of PCI bus */
347 pe->type = EEH_PE_BUS;
350 /* Put the edev to PE */
351 list_add_tail(&edev->list, &pe->edevs);
352 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Bus PE#%x\n",
353 edev->phb->global_number,
354 edev->config_addr >> 8,
355 PCI_SLOT(edev->config_addr & 0xFF),
356 PCI_FUNC(edev->config_addr & 0xFF),
359 } else if (pe && (pe->type & EEH_PE_INVALID)) {
360 list_add_tail(&edev->list, &pe->edevs);
363 * We're running to here because of PCI hotplug caused by
364 * EEH recovery. We need clear EEH_PE_INVALID until the top.
368 if (!(parent->type & EEH_PE_INVALID))
370 parent->type &= ~(EEH_PE_INVALID | EEH_PE_KEEP);
371 parent = parent->parent;
374 pr_debug("EEH: Add %04x:%02x:%02x.%01x to Device "
375 "PE#%x, Parent PE#%x\n",
376 edev->phb->global_number,
377 edev->config_addr >> 8,
378 PCI_SLOT(edev->config_addr & 0xFF),
379 PCI_FUNC(edev->config_addr & 0xFF),
380 pe->addr, pe->parent->addr);
384 /* Create a new EEH PE */
385 pe = eeh_pe_alloc(edev->phb, EEH_PE_DEVICE);
387 pr_err("%s: out of memory!\n", __func__);
390 pe->addr = edev->pe_config_addr;
391 pe->config_addr = edev->config_addr;
394 * Put the new EEH PE into hierarchy tree. If the parent
395 * can't be found, the newly created PE will be attached
396 * to PHB directly. Otherwise, we have to associate the
397 * PE with its parent.
399 parent = eeh_pe_get_parent(edev);
401 parent = eeh_phb_pe_get(edev->phb);
403 pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
404 __func__, edev->phb->global_number);
413 * Put the newly created PE into the child list and
414 * link the EEH device accordingly.
416 list_add_tail(&pe->child, &parent->child_list);
417 list_add_tail(&edev->list, &pe->edevs);
419 pr_debug("EEH: Add %04x:%02x:%02x.%01x to "
420 "Device PE#%x, Parent PE#%x\n",
421 edev->phb->global_number,
422 edev->config_addr >> 8,
423 PCI_SLOT(edev->config_addr & 0xFF),
424 PCI_FUNC(edev->config_addr & 0xFF),
425 pe->addr, pe->parent->addr);
431 * eeh_rmv_from_parent_pe - Remove one EEH device from the associated PE
434 * The PE hierarchy tree might be changed when doing PCI hotplug.
435 * Also, the PCI devices or buses could be removed from the system
436 * during EEH recovery. So we have to call the function remove the
437 * corresponding PE accordingly if necessary.
439 int eeh_rmv_from_parent_pe(struct eeh_dev *edev)
441 struct eeh_pe *pe, *parent, *child;
445 pr_debug("%s: No PE found for device %04x:%02x:%02x.%01x\n",
446 __func__, edev->phb->global_number,
447 edev->config_addr >> 8,
448 PCI_SLOT(edev->config_addr & 0xFF),
449 PCI_FUNC(edev->config_addr & 0xFF));
453 /* Remove the EEH device */
454 pe = eeh_dev_to_pe(edev);
456 list_del(&edev->list);
459 * Check if the parent PE includes any EEH devices.
460 * If not, we should delete that. Also, we should
461 * delete the parent PE if it doesn't have associated
462 * child PEs and EEH devices.
466 if (pe->type & EEH_PE_PHB)
469 if (!(pe->state & EEH_PE_KEEP)) {
470 if (list_empty(&pe->edevs) &&
471 list_empty(&pe->child_list)) {
472 list_del(&pe->child);
478 if (list_empty(&pe->edevs)) {
480 list_for_each_entry(child, &pe->child_list, child) {
481 if (!(child->type & EEH_PE_INVALID)) {
488 pe->type |= EEH_PE_INVALID;
501 * eeh_pe_update_time_stamp - Update PE's frozen time stamp
504 * We have time stamp for each PE to trace its time of getting
505 * frozen in last hour. The function should be called to update
506 * the time stamp on first error of the specific PE. On the other
507 * handle, we needn't account for errors happened in last hour.
509 void eeh_pe_update_time_stamp(struct eeh_pe *pe)
511 struct timeval tstamp;
515 if (pe->freeze_count <= 0) {
516 pe->freeze_count = 0;
517 do_gettimeofday(&pe->tstamp);
519 do_gettimeofday(&tstamp);
520 if (tstamp.tv_sec - pe->tstamp.tv_sec > 3600) {
522 pe->freeze_count = 0;
528 * __eeh_pe_state_mark - Mark the state for the PE
532 * The function is used to mark the indicated state for the given
533 * PE. Also, the associated PCI devices will be put into IO frozen
536 static void *__eeh_pe_state_mark(void *data, void *flag)
538 struct eeh_pe *pe = (struct eeh_pe *)data;
539 int state = *((int *)flag);
540 struct eeh_dev *edev, *tmp;
541 struct pci_dev *pdev;
543 /* Keep the state of permanently removed PE intact */
544 if (pe->state & EEH_PE_REMOVED)
549 /* Offline PCI devices if applicable */
550 if (!(state & EEH_PE_ISOLATED))
553 eeh_pe_for_each_dev(pe, edev, tmp) {
554 pdev = eeh_dev_to_pci_dev(edev);
556 pdev->error_state = pci_channel_io_frozen;
559 /* Block PCI config access if required */
560 if (pe->state & EEH_PE_CFG_RESTRICTED)
561 pe->state |= EEH_PE_CFG_BLOCKED;
567 * eeh_pe_state_mark - Mark specified state for PE and its associated device
570 * EEH error affects the current PE and its child PEs. The function
571 * is used to mark appropriate state for the affected PEs and the
572 * associated devices.
574 void eeh_pe_state_mark(struct eeh_pe *pe, int state)
576 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
579 static void *__eeh_pe_dev_mode_mark(void *data, void *flag)
581 struct eeh_dev *edev = data;
582 int mode = *((int *)flag);
590 * eeh_pe_dev_state_mark - Mark state for all device under the PE
593 * Mark specific state for all child devices of the PE.
595 void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode)
597 eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode);
601 * __eeh_pe_state_clear - Clear state for the PE
605 * The function is used to clear the indicated state from the
606 * given PE. Besides, we also clear the check count of the PE
609 static void *__eeh_pe_state_clear(void *data, void *flag)
611 struct eeh_pe *pe = (struct eeh_pe *)data;
612 int state = *((int *)flag);
613 struct eeh_dev *edev, *tmp;
614 struct pci_dev *pdev;
616 /* Keep the state of permanently removed PE intact */
617 if (pe->state & EEH_PE_REMOVED)
623 * Special treatment on clearing isolated state. Clear
624 * check count since last isolation and put all affected
625 * devices to normal state.
627 if (!(state & EEH_PE_ISOLATED))
631 eeh_pe_for_each_dev(pe, edev, tmp) {
632 pdev = eeh_dev_to_pci_dev(edev);
636 pdev->error_state = pci_channel_io_normal;
639 /* Unblock PCI config access if required */
640 if (pe->state & EEH_PE_CFG_RESTRICTED)
641 pe->state &= ~EEH_PE_CFG_BLOCKED;
647 * eeh_pe_state_clear - Clear state for the PE and its children
649 * @state: state to be cleared
651 * When the PE and its children has been recovered from error,
652 * we need clear the error state for that. The function is used
655 void eeh_pe_state_clear(struct eeh_pe *pe, int state)
657 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
661 * eeh_pe_state_mark_with_cfg - Mark PE state with unblocked config space
663 * @state: PE state to be set
665 * Set specified flag to PE and its child PEs. The PCI config space
666 * of some PEs is blocked automatically when EEH_PE_ISOLATED is set,
667 * which isn't needed in some situations. The function allows to set
668 * the specified flag to indicated PEs without blocking their PCI
671 void eeh_pe_state_mark_with_cfg(struct eeh_pe *pe, int state)
673 eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
674 if (!(state & EEH_PE_ISOLATED))
677 /* Clear EEH_PE_CFG_BLOCKED, which might be set just now */
678 state = EEH_PE_CFG_BLOCKED;
679 eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
683 * Some PCI bridges (e.g. PLX bridges) have primary/secondary
684 * buses assigned explicitly by firmware, and we probably have
685 * lost that after reset. So we have to delay the check until
686 * the PCI-CFG registers have been restored for the parent
689 * Don't use normal PCI-CFG accessors, which probably has been
690 * blocked on normal path during the stage. So we need utilize
691 * eeh operations, which is always permitted.
693 static void eeh_bridge_check_link(struct eeh_dev *edev)
695 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
701 * We only check root port and downstream ports of
704 if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT)))
707 pr_debug("%s: Check PCIe link for %04x:%02x:%02x.%01x ...\n",
708 __func__, edev->phb->global_number,
709 edev->config_addr >> 8,
710 PCI_SLOT(edev->config_addr & 0xFF),
711 PCI_FUNC(edev->config_addr & 0xFF));
713 /* Check slot status */
714 cap = edev->pcie_cap;
715 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
716 if (!(val & PCI_EXP_SLTSTA_PDS)) {
717 pr_debug(" No card in the slot (0x%04x) !\n", val);
721 /* Check power status if we have the capability */
722 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
723 if (val & PCI_EXP_SLTCAP_PCP) {
724 eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
725 if (val & PCI_EXP_SLTCTL_PCC) {
726 pr_debug(" In power-off state, power it on ...\n");
727 val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
728 val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
729 eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
735 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
736 val &= ~PCI_EXP_LNKCTL_LD;
737 eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
740 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
741 if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
742 pr_debug(" No link reporting capability (0x%08x) \n", val);
747 /* Wait the link is up until timeout (5s) */
749 while (timeout < 5000) {
753 eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
754 if (val & PCI_EXP_LNKSTA_DLLLA)
758 if (val & PCI_EXP_LNKSTA_DLLLA)
759 pr_debug(" Link up (%s)\n",
760 (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
762 pr_debug(" Link not ready (0x%04x)\n", val);
765 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
766 #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
768 static void eeh_restore_bridge_bars(struct eeh_dev *edev)
770 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
774 * Device BARs: 0x10 - 0x18
775 * Bus numbers and windows: 0x18 - 0x30
777 for (i = 4; i < 13; i++)
778 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
780 eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
782 /* Cache line & Latency timer: 0xC 0xD */
783 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
784 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
785 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
786 SAVED_BYTE(PCI_LATENCY_TIMER));
787 /* Max latency, min grant, interrupt ping and line: 0x3C */
788 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
790 /* PCI Command: 0x4 */
791 eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1]);
793 /* Check the PCIe link is ready */
794 eeh_bridge_check_link(edev);
797 static void eeh_restore_device_bars(struct eeh_dev *edev)
799 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
803 for (i = 4; i < 10; i++)
804 eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
805 /* 12 == Expansion ROM Address */
806 eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
808 eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
809 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
810 eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
811 SAVED_BYTE(PCI_LATENCY_TIMER));
813 /* max latency, min grant, interrupt pin and line */
814 eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
817 * Restore PERR & SERR bits, some devices require it,
818 * don't touch the other command bits
820 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
821 if (edev->config_space[1] & PCI_COMMAND_PARITY)
822 cmd |= PCI_COMMAND_PARITY;
824 cmd &= ~PCI_COMMAND_PARITY;
825 if (edev->config_space[1] & PCI_COMMAND_SERR)
826 cmd |= PCI_COMMAND_SERR;
828 cmd &= ~PCI_COMMAND_SERR;
829 eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
833 * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
837 * Loads the PCI configuration space base address registers,
838 * the expansion ROM base address, the latency timer, and etc.
839 * from the saved values in the device node.
841 static void *eeh_restore_one_device_bars(void *data, void *flag)
843 struct eeh_dev *edev = (struct eeh_dev *)data;
844 struct pci_dn *pdn = eeh_dev_to_pdn(edev);
846 /* Do special restore for bridges */
847 if (edev->mode & EEH_DEV_BRIDGE)
848 eeh_restore_bridge_bars(edev);
850 eeh_restore_device_bars(edev);
852 if (eeh_ops->restore_config && pdn)
853 eeh_ops->restore_config(pdn);
859 * eeh_pe_restore_bars - Restore the PCI config space info
862 * This routine performs a recursive walk to the children
863 * of this device as well.
865 void eeh_pe_restore_bars(struct eeh_pe *pe)
868 * We needn't take the EEH lock since eeh_pe_dev_traverse()
871 eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL);
875 * eeh_pe_loc_get - Retrieve location code binding to the given PE
878 * Retrieve the location code of the given PE. If the primary PE bus
879 * is root bus, we will grab location code from PHB device tree node
880 * or root port. Otherwise, the upstream bridge's device tree node
881 * of the primary PE bus will be checked for the location code.
883 const char *eeh_pe_loc_get(struct eeh_pe *pe)
885 struct pci_bus *bus = eeh_pe_bus_get(pe);
886 struct device_node *dn = pci_bus_to_OF_node(bus);
887 const char *loc = NULL;
892 /* PHB PE or root PE ? */
893 if (pci_is_root_bus(bus)) {
894 loc = of_get_property(dn, "ibm,loc-code", NULL);
896 loc = of_get_property(dn, "ibm,io-base-loc-code", NULL);
900 /* Check the root port */
906 loc = of_get_property(dn, "ibm,loc-code", NULL);
908 loc = of_get_property(dn, "ibm,slot-location-code", NULL);
911 return loc ? loc : "N/A";
915 * eeh_pe_bus_get - Retrieve PCI bus according to the given PE
918 * Retrieve the PCI bus according to the given PE. Basically,
919 * there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the
920 * primary PCI bus will be retrieved. The parent bus will be
921 * returned for BUS PE. However, we don't have associated PCI
924 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
926 struct pci_bus *bus = NULL;
927 struct eeh_dev *edev;
928 struct pci_dev *pdev;
930 if (pe->type & EEH_PE_PHB) {
932 } else if (pe->type & EEH_PE_BUS ||
933 pe->type & EEH_PE_DEVICE) {
939 edev = list_first_entry(&pe->edevs, struct eeh_dev, list);
940 pdev = eeh_dev_to_pci_dev(edev);