3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
35 #include <asm/hw_irq.h>
36 #include <asm/context_tracking.h>
43 .tc sys_call_table[TC],sys_call_table
45 /* This value is used to mark exception frames on the stack. */
47 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
52 .globl system_call_common
56 addi r1,r1,-INT_FRAME_SIZE
64 beq 2f /* if from kernel mode */
65 ACCOUNT_CPU_USER_ENTRY(r10, r11)
84 * This clears CR0.SO (bit 28), which is the error indication on
85 * return from this system call.
87 rldimi r2,r11,28,(63-28)
94 addi r9,r1,STACK_FRAME_OVERHEAD
95 ld r11,exception_marker@toc(r2)
96 std r11,-16(r9) /* "regshere" marker */
97 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
100 /* if from user, see if there are any DTL entries to process */
101 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
102 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
103 addi r10,r10,LPPACA_DTLIDX
104 LDX_BE r10,0,r10 /* get log write index */
107 bl accumulate_stolen_time
111 addi r9,r1,STACK_FRAME_OVERHEAD
113 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
114 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
117 * A syscall should always be called with interrupts enabled
118 * so we just unconditionally hard-enable here. When some kind
119 * of irq tracing is used, we additionally check that condition
122 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
123 lbz r10,PACASOFTIRQEN(r13)
126 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
129 #ifdef CONFIG_PPC_BOOK3E
135 #endif /* CONFIG_PPC_BOOK3E */
137 /* We do need to set SOFTE in the stack frame or the return
138 * from interrupt will be painful
143 CURRENT_THREAD_INFO(r11, r1)
145 andi. r11,r10,_TIF_SYSCALL_DOTRACE
147 .Lsyscall_dotrace_cont:
148 cmpldi 0,r0,NR_syscalls
151 system_call: /* label this so stack traces look sane */
153 * Need to vector to 32 Bit or default sys_call_table here,
154 * based on caller's run-mode / personality.
156 ld r11,SYS_CALL_TABLE@toc(2)
157 andi. r10,r10,_TIF_32BIT
159 addi r11,r11,8 /* use 32-bit syscall entries */
168 ldx r12,r11,r0 /* Fetch system call handler [ptr] */
170 bctrl /* Call handler */
174 CURRENT_THREAD_INFO(r12, r1)
177 #ifdef CONFIG_PPC_BOOK3S
178 /* No MSR:RI on BookE */
183 * Disable interrupts so current_thread_info()->flags can't change,
184 * and so that we don't get interrupted after loading SRR0/1.
186 #ifdef CONFIG_PPC_BOOK3E
191 * For performance reasons we clear RI the same time that we
192 * clear EE. We only need to clear RI just before we restore r13
193 * below, but batching it with EE saves us one expensive mtmsrd call.
194 * We have to be careful to restore RI if we branch anywhere from
195 * here (eg syscall_exit_work).
200 #endif /* CONFIG_PPC_BOOK3E */
204 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
205 bne- syscall_exit_work
209 .Lsyscall_error_cont:
212 stdcx. r0,0,r1 /* to clear the reservation */
213 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
218 ACCOUNT_CPU_USER_EXIT(r11, r12)
219 HMT_MEDIUM_LOW_HAS_PPR
220 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
228 b . /* prevent speculative execution */
231 oris r5,r5,0x1000 /* Set SO bit in CR */
234 b .Lsyscall_error_cont
236 /* Traced system call support */
239 addi r3,r1,STACK_FRAME_OVERHEAD
240 bl do_syscall_trace_enter
242 * Restore argument registers possibly just changed.
243 * We use the return value of do_syscall_trace_enter
244 * for the call number to look up in the table (r0).
253 addi r9,r1,STACK_FRAME_OVERHEAD
254 CURRENT_THREAD_INFO(r10, r1)
256 b .Lsyscall_dotrace_cont
263 #ifdef CONFIG_PPC_BOOK3S
264 mtmsrd r10,1 /* Restore RI */
266 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
267 If TIF_NOERROR is set, just save r3 as it is. */
269 andi. r0,r9,_TIF_RESTOREALL
273 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
275 andi. r0,r9,_TIF_NOERROR
279 oris r5,r5,0x1000 /* Set SO bit in CR */
282 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
285 /* Clear per-syscall TIF flags if any are set. */
287 li r11,_TIF_PERSYSCALL_MASK
288 addi r12,r12,TI_FLAGS
293 subi r12,r12,TI_FLAGS
295 4: /* Anything else left to do? */
296 SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
297 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP)
298 beq ret_from_except_lite
300 /* Re-enable interrupts */
301 #ifdef CONFIG_PPC_BOOK3E
307 #endif /* CONFIG_PPC_BOOK3E */
310 addi r3,r1,STACK_FRAME_OVERHEAD
311 bl do_syscall_trace_leave
314 /* Save non-volatile GPRs, if not already saved. */
326 * The sigsuspend and rt_sigsuspend system calls can call do_signal
327 * and thus put the process into the stopped state where we might
328 * want to examine its user state with ptrace. Therefore we need
329 * to save all the nonvolatile registers (r14 - r31) before calling
330 * the C code. Similarly, fork, vfork and clone need the full
331 * register state on the stack so that it can be copied to the child.
349 _GLOBAL(ppc32_swapcontext)
351 bl compat_sys_swapcontext
354 _GLOBAL(ppc64_swapcontext)
359 _GLOBAL(ret_from_fork)
365 _GLOBAL(ret_from_kernel_thread)
370 #if defined(_CALL_ELF) && _CALL_ELF == 2
378 * This routine switches between two different tasks. The process
379 * state of one is saved on its kernel stack. Then the state
380 * of the other is restored from its kernel stack. The memory
381 * management hardware is updated to the second process's state.
382 * Finally, we can return to the second process, via ret_from_except.
383 * On entry, r3 points to the THREAD for the current task, r4
384 * points to the THREAD for the new task.
386 * Note: there are two ways to get to the "going out" portion
387 * of this code; either by coming in via the entry (_switch)
388 * or via "fork" which must set up an environment equivalent
389 * to the "_switch" path. If you change this you'll have to change
390 * the fork code also.
392 * The code which creates the new task context is in 'copy_thread'
393 * in arch/powerpc/kernel/process.c
399 stdu r1,-SWITCH_FRAME_SIZE(r1)
400 /* r3-r13 are caller saved -- Cort */
403 mflr r20 /* Return to switch caller */
408 oris r0,r0,MSR_VSX@h /* Disable VSX */
409 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
410 #endif /* CONFIG_VSX */
411 #ifdef CONFIG_ALTIVEC
413 oris r0,r0,MSR_VEC@h /* Disable altivec */
414 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
415 std r24,THREAD_VRSAVE(r3)
416 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
417 #endif /* CONFIG_ALTIVEC */
426 std r1,KSP(r3) /* Set old stack pointer */
428 #ifdef CONFIG_PPC_BOOK3S_64
430 /* Event based branch registers */
432 std r0, THREAD_BESCR(r3)
434 std r0, THREAD_EBBHR(r3)
436 std r0, THREAD_EBBRR(r3)
437 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
441 /* We need a sync somewhere here to make sure that if the
442 * previous task gets rescheduled on another CPU, it sees all
443 * stores it has performed on this one.
446 #endif /* CONFIG_SMP */
449 * If we optimise away the clear of the reservation in system
450 * calls because we know the CPU tracks the address of the
451 * reservation, then we need to clear it here to cover the
452 * case that the kernel context switch path has no larx
457 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
459 #ifdef CONFIG_PPC_BOOK3S
460 /* Cancel all explict user streams as they will have no use after context
461 * switch and will stop the HW from creating streams itself
463 DCBT_STOP_ALL_STREAM_IDS(r6)
466 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
467 std r6,PACACURRENT(r13) /* Set new 'current' */
469 ld r8,KSP(r4) /* new stack pointer */
470 #ifdef CONFIG_PPC_BOOK3S
472 clrrdi r6,r8,28 /* get its ESID */
473 clrrdi r9,r1,28 /* get current sp ESID */
475 clrrdi r6,r8,40 /* get its 1T ESID */
476 clrrdi r9,r1,40 /* get current sp 1T ESID */
477 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
478 clrldi. r0,r6,2 /* is new ESID c00000000? */
479 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
481 beq 2f /* if yes, don't slbie it */
483 /* Bolt in the new stack SLB entry */
484 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
485 oris r0,r6,(SLB_ESID_V)@h
486 ori r0,r0,(SLB_NUM_BOLTED-1)@l
488 li r9,MMU_SEGSIZE_1T /* insert B field */
489 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
490 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
491 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
493 /* Update the last bolted SLB. No write barriers are needed
494 * here, provided we only update the current CPU's SLB shadow
497 ld r9,PACA_SLBSHADOWPTR(r13)
499 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
500 li r12,SLBSHADOW_STACKVSID
501 STDX_BE r7,r12,r9 /* Save VSID */
502 li r12,SLBSHADOW_STACKESID
503 STDX_BE r0,r12,r9 /* Save ESID */
505 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
506 * we have 1TB segments, the only CPUs known to have the errata
507 * only support less than 1TB of system memory and we'll never
508 * actually hit this code path.
512 slbie r6 /* Workaround POWER5 < DD2.1 issue */
516 #endif /* !CONFIG_PPC_BOOK3S */
518 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
519 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
520 because we don't need to leave the 288-byte ABI gap at the
521 top of the kernel stack. */
522 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
524 mr r1,r8 /* start using new stack pointer */
525 std r7,PACAKSAVE(r13)
527 #ifdef CONFIG_PPC_BOOK3S_64
529 /* Event based branch registers */
530 ld r0, THREAD_BESCR(r4)
532 ld r0, THREAD_EBBHR(r4)
534 ld r0, THREAD_EBBRR(r4)
539 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
542 #ifdef CONFIG_ALTIVEC
544 ld r0,THREAD_VRSAVE(r4)
545 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
546 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
547 #endif /* CONFIG_ALTIVEC */
550 lwz r6,THREAD_DSCR_INHERIT(r4)
551 ld r0,THREAD_DSCR(r4)
556 BEGIN_FTR_SECTION_NESTED(70)
558 rldimi r8, r6, FSCR_DSCR_LG, (63 - FSCR_DSCR_LG)
560 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
565 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
571 /* r3-r13 are destroyed -- Cort */
575 /* convert old thread to its task_struct for return value */
577 ld r7,_NIP(r1) /* Return to _switch caller in new task */
579 addi r1,r1,SWITCH_FRAME_SIZE
583 _GLOBAL(ret_from_except)
586 bne ret_from_except_lite
589 _GLOBAL(ret_from_except_lite)
591 * Disable interrupts so that current_thread_info()->flags
592 * can't change between when we test it and when we return
593 * from the interrupt.
595 #ifdef CONFIG_PPC_BOOK3E
598 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
599 mtmsrd r10,1 /* Update machine state */
600 #endif /* CONFIG_PPC_BOOK3E */
602 CURRENT_THREAD_INFO(r9, r1)
604 #ifdef CONFIG_PPC_BOOK3E
605 ld r10,PACACURRENT(r13)
606 #endif /* CONFIG_PPC_BOOK3E */
610 #ifdef CONFIG_PPC_BOOK3E
611 lwz r3,(THREAD+THREAD_DBCR0)(r10)
612 #endif /* CONFIG_PPC_BOOK3E */
614 /* Check current_thread_info()->flags */
615 andi. r0,r4,_TIF_USER_WORK_MASK
616 #ifdef CONFIG_PPC_BOOK3E
619 * Check to see if the dbcr0 register is set up to debug.
620 * Use the internal debug mode bit to do this.
622 andis. r0,r3,DBCR0_IDM@h
625 rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */
634 1: andi. r0,r4,_TIF_NEED_RESCHED
636 bl restore_interrupts
638 b ret_from_except_lite
640 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
641 andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
642 bne 3f /* only restore TM if nothing else to do */
643 addi r3,r1,STACK_FRAME_OVERHEAD
650 * Use a non volatile GPR to save and restore our thread_info flags
651 * across the call to restore_interrupts.
654 bl restore_interrupts
656 addi r3,r1,STACK_FRAME_OVERHEAD
661 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
662 andis. r8,r4,_TIF_EMULATE_STACK_STORE@h
665 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
668 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
669 mr r4,r1 /* src: current exception frame */
670 mr r1,r3 /* Reroute the trampoline frame to r1 */
672 /* Copy from the original to the trampoline. */
673 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
674 li r6,0 /* start offset: 0 */
681 /* Do real store operation to complete stwu */
685 /* Clear _TIF_EMULATE_STACK_STORE flag */
686 lis r11,_TIF_EMULATE_STACK_STORE@h
694 #ifdef CONFIG_PREEMPT
695 /* Check if we need to preempt */
696 andi. r0,r4,_TIF_NEED_RESCHED
698 /* Check that preempt_count() == 0 and interrupts are enabled */
699 lwz r8,TI_PREEMPT(r9)
703 crandc eq,cr1*4+eq,eq
707 * Here we are preempting the current task. We want to make
708 * sure we are soft-disabled first and reconcile irq state.
710 RECONCILE_IRQ_STATE(r3,r4)
711 1: bl preempt_schedule_irq
713 /* Re-test flags and eventually loop */
714 CURRENT_THREAD_INFO(r9, r1)
716 andi. r0,r4,_TIF_NEED_RESCHED
720 * arch_local_irq_restore() from preempt_schedule_irq above may
721 * enable hard interrupt but we really should disable interrupts
722 * when we return from the interrupt, and so that we don't get
723 * interrupted after loading SRR0/1.
725 #ifdef CONFIG_PPC_BOOK3E
728 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
729 mtmsrd r10,1 /* Update machine state */
730 #endif /* CONFIG_PPC_BOOK3E */
731 #endif /* CONFIG_PREEMPT */
733 .globl fast_exc_return_irq
737 * This is the main kernel exit path. First we check if we
738 * are about to re-enable interrupts
741 lbz r6,PACASOFTIRQEN(r13)
745 /* We are enabling, were we already enabled ? Yes, just return */
750 * We are about to soft-enable interrupts (we are hard disabled
751 * at this point). We check if there's anything that needs to
754 lbz r0,PACAIRQHAPPENED(r13)
756 bne- restore_check_irq_replay
759 * Get here when nothing happened while soft-disabled, just
760 * soft-enable and move-on. We will hard-enable as a side
766 stb r0,PACASOFTIRQEN(r13);
769 * Final return path. BookE is handled in a different file
772 #ifdef CONFIG_PPC_BOOK3E
773 b exception_return_book3e
776 * Clear the reservation. If we know the CPU tracks the address of
777 * the reservation then we can potentially save some cycles and use
778 * a larx. On POWER6 and POWER7 this is significantly faster.
781 stdcx. r0,0,r1 /* to clear the reservation */
784 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
787 * Some code path such as load_up_fpu or altivec return directly
788 * here. They run entirely hard disabled and do not alter the
789 * interrupt state. They also don't use lwarx/stwcx. and thus
790 * are known not to leave dangling reservations.
792 .globl fast_exception_return
793 fast_exception_return:
807 /* Load PPR from thread struct before we clear MSR:RI */
809 ld r2,PACACURRENT(r13)
810 ld r2,TASKTHREADPPR(r2)
811 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
814 * Clear RI before restoring r13. If we are returning to
815 * userspace and we take an exception after restoring r13,
816 * we end up corrupting the userspace r13 value.
818 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
819 andc r4,r4,r0 /* r0 contains MSR_RI here */
822 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
824 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
827 * r13 is our per cpu area, only restore it if we are returning to
828 * userspace the value stored in the stack frame may belong to
834 mtspr SPRN_PPR,r2 /* Restore PPR */
835 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
836 ACCOUNT_CPU_USER_EXIT(r2, r4)
853 b . /* prevent speculative execution */
855 #endif /* CONFIG_PPC_BOOK3E */
858 * We are returning to a context with interrupts soft disabled.
860 * However, we may also about to hard enable, so we need to
861 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
862 * or that bit can get out of sync and bad things will happen
866 lbz r7,PACAIRQHAPPENED(r13)
869 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
870 stb r7,PACAIRQHAPPENED(r13)
872 stb r0,PACASOFTIRQEN(r13);
877 * Something did happen, check if a re-emit is needed
878 * (this also clears paca->irq_happened)
880 restore_check_irq_replay:
881 /* XXX: We could implement a fast path here where we check
882 * for irq_happened being just 0x01, in which case we can
883 * clear it and return. That means that we would potentially
884 * miss a decrementer having wrapped all the way around.
886 * Still, this might be useful for things like hash_page
888 bl __check_irq_replay
890 beq restore_no_replay
893 * We need to re-emit an interrupt. We do so by re-using our
894 * existing exception frame. We first change the trap value,
895 * but we need to ensure we preserve the low nibble of it
903 * Then find the right handler and call it. Interrupts are
904 * still soft-disabled and we keep them that way.
908 addi r3,r1,STACK_FRAME_OVERHEAD;
911 1: cmpwi cr0,r3,0xe60
913 addi r3,r1,STACK_FRAME_OVERHEAD;
914 bl handle_hmi_exception
916 1: cmpwi cr0,r3,0x900
918 addi r3,r1,STACK_FRAME_OVERHEAD;
921 #ifdef CONFIG_PPC_DOORBELL
923 #ifdef CONFIG_PPC_BOOK3E
930 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
931 #endif /* CONFIG_PPC_BOOK3E */
933 addi r3,r1,STACK_FRAME_OVERHEAD;
934 bl doorbell_exception
936 #endif /* CONFIG_PPC_DOORBELL */
937 1: b ret_from_except /* What else to do here ? */
940 addi r3,r1,STACK_FRAME_OVERHEAD
941 bl unrecoverable_exception
944 #ifdef CONFIG_PPC_RTAS
946 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
947 * called with the MMU off.
949 * In addition, we need to be in 32b mode, at least for now.
951 * Note: r3 is an input parameter to rtas, so don't trash it...
956 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
958 /* Because RTAS is running in 32b mode, it clobbers the high order half
959 * of all registers that it saves. We therefore save those registers
960 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
962 SAVE_GPR(2, r1) /* Save the TOC */
963 SAVE_GPR(13, r1) /* Save paca */
964 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
965 SAVE_10GPRS(22, r1) /* ditto */
978 /* Temporary workaround to clear CR until RTAS can be modified to
985 /* There is no way it is acceptable to get here with interrupts enabled,
986 * check it with the asm equivalent of WARN_ON
988 lbz r0,PACASOFTIRQEN(r13)
990 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
993 /* Hard-disable interrupts */
999 /* Unfortunately, the stack pointer and the MSR are also clobbered,
1000 * so they are saved in the PACA which allows us to restore
1001 * our original state after RTAS returns.
1004 std r6,PACASAVEDMSR(r13)
1006 /* Setup our real return addr */
1007 LOAD_REG_ADDR(r4,rtas_return_loc)
1008 clrldi r4,r4,2 /* convert to realmode address */
1012 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
1016 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1017 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1019 sync /* disable interrupts so SRR0/1 */
1020 mtmsrd r0 /* don't get trashed */
1022 LOAD_REG_ADDR(r4, rtas)
1023 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
1024 ld r4,RTASBASE(r4) /* get the rtas->base value */
1029 b . /* prevent speculative execution */
1034 /* relocation is off at this point */
1036 clrldi r4,r4,2 /* convert to realmode address */
1040 ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
1048 ld r1,PACAR1(r4) /* Restore our SP */
1049 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1054 b . /* prevent speculative execution */
1057 1: .llong rtas_restore_regs
1060 /* relocation is on at this point */
1061 REST_GPR(2, r1) /* Restore the TOC */
1062 REST_GPR(13, r1) /* Restore paca */
1063 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1064 REST_10GPRS(22, r1) /* ditto */
1079 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1080 ld r0,16(r1) /* get return address */
1083 blr /* return to caller */
1085 #endif /* CONFIG_PPC_RTAS */
1090 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1092 /* Because PROM is running in 32b mode, it clobbers the high order half
1093 * of all registers that it saves. We therefore save those registers
1094 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1105 /* Put PROM address in SRR0 */
1108 /* Setup our trampoline return addr in LR */
1111 addi r4,r4,(1f - 0b)
1114 /* Prepare a 32-bit mode big endian MSR
1116 #ifdef CONFIG_PPC_BOOK3E
1117 rlwinm r11,r11,0,1,31
1120 #else /* CONFIG_PPC_BOOK3E */
1121 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
1125 #endif /* CONFIG_PPC_BOOK3E */
1127 1: /* Return from OF */
1130 /* Just make sure that r1 top 32 bits didn't get
1135 /* Restore the MSR (back to 64 bits) */
1140 /* Restore other registers */
1148 addi r1,r1,PROM_FRAME_SIZE
1153 #ifdef CONFIG_FUNCTION_TRACER
1154 #ifdef CONFIG_DYNAMIC_FTRACE
1159 _GLOBAL_TOC(ftrace_caller)
1160 /* Taken from output of objdump from lib64/glibc */
1166 subi r3, r3, MCOUNT_INSN_SIZE
1171 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1172 .globl ftrace_graph_call
1175 _GLOBAL(ftrace_graph_stub)
1180 _GLOBAL(ftrace_stub)
1183 _GLOBAL_TOC(_mcount)
1184 /* Taken from output of objdump from lib64/glibc */
1191 subi r3, r3, MCOUNT_INSN_SIZE
1192 LOAD_REG_ADDR(r5,ftrace_trace_function)
1200 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1201 b ftrace_graph_caller
1206 _GLOBAL(ftrace_stub)
1209 #endif /* CONFIG_DYNAMIC_FTRACE */
1211 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1212 _GLOBAL(ftrace_graph_caller)
1213 /* load r4 with local address */
1215 subi r4, r4, MCOUNT_INSN_SIZE
1217 /* Grab the LR out of the caller stack frame */
1221 bl prepare_ftrace_return
1225 * prepare_ftrace_return gives us the address we divert to.
1226 * Change the LR in the callers stack frame to this.
1236 _GLOBAL(return_to_handler)
1237 /* need to save return values */
1247 * We might be called from a module.
1248 * Switch to our TOC to run inside the core kernel.
1252 bl ftrace_return_to_handler
1255 /* return value has real return address */
1264 /* Jump back to real return address */
1266 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1267 #endif /* CONFIG_FUNCTION_TRACER */