3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
35 #include <asm/hw_irq.h>
42 .tc .sys_call_table[TC],.sys_call_table
44 /* This value is used to mark exception frames on the stack. */
46 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
53 .globl system_call_common
57 addi r1,r1,-INT_FRAME_SIZE
65 beq 2f /* if from kernel mode */
66 ACCOUNT_CPU_USER_ENTRY(r10, r11)
85 * This clears CR0.SO (bit 28), which is the error indication on
86 * return from this system call.
88 rldimi r2,r11,28,(63-28)
95 addi r9,r1,STACK_FRAME_OVERHEAD
96 ld r11,exception_marker@toc(r2)
97 std r11,-16(r9) /* "regshere" marker */
98 #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
101 /* if from user, see if there are any DTL entries to process */
102 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
103 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
104 ld r10,LPPACA_DTLIDX(r10) /* get log write index */
107 bl .accumulate_stolen_time
111 addi r9,r1,STACK_FRAME_OVERHEAD
113 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
114 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
117 * A syscall should always be called with interrupts enabled
118 * so we just unconditionally hard-enable here. When some kind
119 * of irq tracing is used, we additionally check that condition
122 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
123 lbz r10,PACASOFTIRQEN(r13)
126 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
129 #ifdef CONFIG_PPC_BOOK3E
135 #endif /* CONFIG_PPC_BOOK3E */
137 /* We do need to set SOFTE in the stack frame or the return
138 * from interrupt will be painful
148 addi r9,r1,STACK_FRAME_OVERHEAD
150 CURRENT_THREAD_INFO(r11, r1)
152 andi. r11,r10,_TIF_SYSCALL_T_OR_A
154 .Lsyscall_dotrace_cont:
155 cmpldi 0,r0,NR_syscalls
158 system_call: /* label this so stack traces look sane */
160 * Need to vector to 32 Bit or default sys_call_table here,
161 * based on caller's run-mode / personality.
163 ld r11,.SYS_CALL_TABLE@toc(2)
164 andi. r10,r10,_TIF_32BIT
166 addi r11,r11,8 /* use 32-bit syscall entries */
175 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
177 bctrl /* Call handler */
182 bl .do_show_syscall_exit
185 CURRENT_THREAD_INFO(r12, r1)
188 #ifdef CONFIG_PPC_BOOK3S
189 /* No MSR:RI on BookE */
194 * Disable interrupts so current_thread_info()->flags can't change,
195 * and so that we don't get interrupted after loading SRR0/1.
197 #ifdef CONFIG_PPC_BOOK3E
202 * For performance reasons we clear RI the same time that we
203 * clear EE. We only need to clear RI just before we restore r13
204 * below, but batching it with EE saves us one expensive mtmsrd call.
205 * We have to be careful to restore RI if we branch anywhere from
206 * here (eg syscall_exit_work).
211 #endif /* CONFIG_PPC_BOOK3E */
215 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
216 bne- syscall_exit_work
220 .Lsyscall_error_cont:
223 stdcx. r0,0,r1 /* to clear the reservation */
224 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
229 ACCOUNT_CPU_USER_EXIT(r11, r12)
230 HMT_MEDIUM_LOW_HAS_PPR
231 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
239 b . /* prevent speculative execution */
242 oris r5,r5,0x1000 /* Set SO bit in CR */
245 b .Lsyscall_error_cont
247 /* Traced system call support */
250 addi r3,r1,STACK_FRAME_OVERHEAD
251 bl .do_syscall_trace_enter
253 * Restore argument registers possibly just changed.
254 * We use the return value of do_syscall_trace_enter
255 * for the call number to look up in the table (r0).
264 addi r9,r1,STACK_FRAME_OVERHEAD
265 CURRENT_THREAD_INFO(r10, r1)
267 b .Lsyscall_dotrace_cont
274 #ifdef CONFIG_PPC_BOOK3S
275 mtmsrd r10,1 /* Restore RI */
277 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
278 If TIF_NOERROR is set, just save r3 as it is. */
280 andi. r0,r9,_TIF_RESTOREALL
284 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
286 andi. r0,r9,_TIF_NOERROR
290 oris r5,r5,0x1000 /* Set SO bit in CR */
293 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
296 /* Clear per-syscall TIF flags if any are set. */
298 li r11,_TIF_PERSYSCALL_MASK
299 addi r12,r12,TI_FLAGS
304 subi r12,r12,TI_FLAGS
306 4: /* Anything else left to do? */
307 SET_DEFAULT_THREAD_PPR(r3, r9) /* Set thread.ppr = 3 */
308 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
309 beq .ret_from_except_lite
311 /* Re-enable interrupts */
312 #ifdef CONFIG_PPC_BOOK3E
318 #endif /* CONFIG_PPC_BOOK3E */
321 addi r3,r1,STACK_FRAME_OVERHEAD
322 bl .do_syscall_trace_leave
325 /* Save non-volatile GPRs, if not already saved. */
337 * The sigsuspend and rt_sigsuspend system calls can call do_signal
338 * and thus put the process into the stopped state where we might
339 * want to examine its user state with ptrace. Therefore we need
340 * to save all the nonvolatile registers (r14 - r31) before calling
341 * the C code. Similarly, fork, vfork and clone need the full
342 * register state on the stack so that it can be copied to the child.
360 _GLOBAL(ppc32_swapcontext)
362 bl .compat_sys_swapcontext
365 _GLOBAL(ppc64_swapcontext)
370 _GLOBAL(ret_from_fork)
376 _GLOBAL(ret_from_kernel_thread)
390 .tc dscr_default[TC],dscr_default
395 * This routine switches between two different tasks. The process
396 * state of one is saved on its kernel stack. Then the state
397 * of the other is restored from its kernel stack. The memory
398 * management hardware is updated to the second process's state.
399 * Finally, we can return to the second process, via ret_from_except.
400 * On entry, r3 points to the THREAD for the current task, r4
401 * points to the THREAD for the new task.
403 * Note: there are two ways to get to the "going out" portion
404 * of this code; either by coming in via the entry (_switch)
405 * or via "fork" which must set up an environment equivalent
406 * to the "_switch" path. If you change this you'll have to change
407 * the fork code also.
409 * The code which creates the new task context is in 'copy_thread'
410 * in arch/powerpc/kernel/process.c
416 stdu r1,-SWITCH_FRAME_SIZE(r1)
417 /* r3-r13 are caller saved -- Cort */
420 mflr r20 /* Return to switch caller */
425 oris r0,r0,MSR_VSX@h /* Disable VSX */
426 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
427 #endif /* CONFIG_VSX */
428 #ifdef CONFIG_ALTIVEC
430 oris r0,r0,MSR_VEC@h /* Disable altivec */
431 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
432 std r24,THREAD_VRSAVE(r3)
433 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
434 #endif /* CONFIG_ALTIVEC */
438 std r25,THREAD_DSCR(r3)
439 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
449 std r1,KSP(r3) /* Set old stack pointer */
451 #ifdef CONFIG_PPC_BOOK3S_64
454 * Back up the TAR across context switches. Note that the TAR is not
455 * available for use in the kernel. (To provide this, the TAR should
456 * be backed up/restored on exception entry/exit instead, and be in
457 * pt_regs. FIXME, this should be in pt_regs anyway (for debug).)
460 std r0,THREAD_TAR(r3)
461 END_FTR_SECTION_IFSET(CPU_FTR_BCTAR)
465 /* We need a sync somewhere here to make sure that if the
466 * previous task gets rescheduled on another CPU, it sees all
467 * stores it has performed on this one.
470 #endif /* CONFIG_SMP */
473 * If we optimise away the clear of the reservation in system
474 * calls because we know the CPU tracks the address of the
475 * reservation, then we need to clear it here to cover the
476 * case that the kernel context switch path has no larx
481 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
483 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
484 std r6,PACACURRENT(r13) /* Set new 'current' */
486 ld r8,KSP(r4) /* new stack pointer */
487 #ifdef CONFIG_PPC_BOOK3S
489 BEGIN_FTR_SECTION_NESTED(95)
490 clrrdi r6,r8,28 /* get its ESID */
491 clrrdi r9,r1,28 /* get current sp ESID */
492 FTR_SECTION_ELSE_NESTED(95)
493 clrrdi r6,r8,40 /* get its 1T ESID */
494 clrrdi r9,r1,40 /* get current sp 1T ESID */
495 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
498 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
499 clrldi. r0,r6,2 /* is new ESID c00000000? */
500 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
502 beq 2f /* if yes, don't slbie it */
504 /* Bolt in the new stack SLB entry */
505 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
506 oris r0,r6,(SLB_ESID_V)@h
507 ori r0,r0,(SLB_NUM_BOLTED-1)@l
509 li r9,MMU_SEGSIZE_1T /* insert B field */
510 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
511 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
512 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
514 /* Update the last bolted SLB. No write barriers are needed
515 * here, provided we only update the current CPU's SLB shadow
518 ld r9,PACA_SLBSHADOWPTR(r13)
520 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
521 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
522 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
524 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
525 * we have 1TB segments, the only CPUs known to have the errata
526 * only support less than 1TB of system memory and we'll never
527 * actually hit this code path.
531 slbie r6 /* Workaround POWER5 < DD2.1 issue */
535 #endif /* !CONFIG_PPC_BOOK3S */
537 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
538 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
539 because we don't need to leave the 288-byte ABI gap at the
540 top of the kernel stack. */
541 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
543 mr r1,r8 /* start using new stack pointer */
544 std r7,PACAKSAVE(r13)
546 #ifdef CONFIG_PPC_BOOK3S_64
550 END_FTR_SECTION_IFSET(CPU_FTR_BCTAR)
553 #ifdef CONFIG_ALTIVEC
555 ld r0,THREAD_VRSAVE(r4)
556 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
557 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
558 #endif /* CONFIG_ALTIVEC */
561 lwz r6,THREAD_DSCR_INHERIT(r4)
562 ld r7,DSCR_DEFAULT@toc(2)
563 ld r0,THREAD_DSCR(r4)
571 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
577 /* r3-r13 are destroyed -- Cort */
581 /* convert old thread to its task_struct for return value */
583 ld r7,_NIP(r1) /* Return to _switch caller in new task */
585 addi r1,r1,SWITCH_FRAME_SIZE
589 _GLOBAL(ret_from_except)
592 bne .ret_from_except_lite
595 _GLOBAL(ret_from_except_lite)
597 * Disable interrupts so that current_thread_info()->flags
598 * can't change between when we test it and when we return
599 * from the interrupt.
601 #ifdef CONFIG_PPC_BOOK3E
604 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
605 mtmsrd r10,1 /* Update machine state */
606 #endif /* CONFIG_PPC_BOOK3E */
608 CURRENT_THREAD_INFO(r9, r1)
614 /* Check current_thread_info()->flags */
615 andi. r0,r4,_TIF_USER_WORK_MASK
618 andi. r0,r4,_TIF_NEED_RESCHED
620 bl .restore_interrupts
622 b .ret_from_except_lite
625 bl .restore_interrupts
626 addi r3,r1,STACK_FRAME_OVERHEAD
631 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
632 CURRENT_THREAD_INFO(r9, r1)
634 andis. r8,r8,_TIF_EMULATE_STACK_STORE@h
637 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
640 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
641 mr r4,r1 /* src: current exception frame */
642 mr r1,r3 /* Reroute the trampoline frame to r1 */
644 /* Copy from the original to the trampoline. */
645 li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
646 li r6,0 /* start offset: 0 */
653 /* Do real store operation to complete stwu */
657 /* Clear _TIF_EMULATE_STACK_STORE flag */
658 lis r11,_TIF_EMULATE_STACK_STORE@h
666 #ifdef CONFIG_PREEMPT
667 /* Check if we need to preempt */
668 andi. r0,r4,_TIF_NEED_RESCHED
670 /* Check that preempt_count() == 0 and interrupts are enabled */
671 lwz r8,TI_PREEMPT(r9)
675 crandc eq,cr1*4+eq,eq
679 * Here we are preempting the current task. We want to make
680 * sure we are soft-disabled first
682 SOFT_DISABLE_INTS(r3,r4)
683 1: bl .preempt_schedule_irq
685 /* Re-test flags and eventually loop */
686 CURRENT_THREAD_INFO(r9, r1)
688 andi. r0,r4,_TIF_NEED_RESCHED
692 * arch_local_irq_restore() from preempt_schedule_irq above may
693 * enable hard interrupt but we really should disable interrupts
694 * when we return from the interrupt, and so that we don't get
695 * interrupted after loading SRR0/1.
697 #ifdef CONFIG_PPC_BOOK3E
700 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
701 mtmsrd r10,1 /* Update machine state */
702 #endif /* CONFIG_PPC_BOOK3E */
703 #endif /* CONFIG_PREEMPT */
705 .globl fast_exc_return_irq
709 * This is the main kernel exit path. First we check if we
710 * are about to re-enable interrupts
713 lbz r6,PACASOFTIRQEN(r13)
717 /* We are enabling, were we already enabled ? Yes, just return */
722 * We are about to soft-enable interrupts (we are hard disabled
723 * at this point). We check if there's anything that needs to
726 lbz r0,PACAIRQHAPPENED(r13)
728 bne- restore_check_irq_replay
731 * Get here when nothing happened while soft-disabled, just
732 * soft-enable and move-on. We will hard-enable as a side
738 stb r0,PACASOFTIRQEN(r13);
741 * Final return path. BookE is handled in a different file
744 #ifdef CONFIG_PPC_BOOK3E
745 b .exception_return_book3e
748 * Clear the reservation. If we know the CPU tracks the address of
749 * the reservation then we can potentially save some cycles and use
750 * a larx. On POWER6 and POWER7 this is significantly faster.
753 stdcx. r0,0,r1 /* to clear the reservation */
756 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
759 * Some code path such as load_up_fpu or altivec return directly
760 * here. They run entirely hard disabled and do not alter the
761 * interrupt state. They also don't use lwarx/stwcx. and thus
762 * are known not to leave dangling reservations.
764 .globl fast_exception_return
765 fast_exception_return:
780 * Clear RI before restoring r13. If we are returning to
781 * userspace and we take an exception after restoring r13,
782 * we end up corrupting the userspace r13 value.
784 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
785 andc r4,r4,r0 /* r0 contains MSR_RI here */
788 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
790 std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
793 * r13 is our per cpu area, only restore it if we are returning to
794 * userspace the value stored in the stack frame may belong to
799 ACCOUNT_CPU_USER_EXIT(r2, r4)
817 b . /* prevent speculative execution */
819 #endif /* CONFIG_PPC_BOOK3E */
822 * We are returning to a context with interrupts soft disabled.
824 * However, we may also about to hard enable, so we need to
825 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
826 * or that bit can get out of sync and bad things will happen
830 lbz r7,PACAIRQHAPPENED(r13)
833 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
834 stb r7,PACAIRQHAPPENED(r13)
836 stb r0,PACASOFTIRQEN(r13);
841 * Something did happen, check if a re-emit is needed
842 * (this also clears paca->irq_happened)
844 restore_check_irq_replay:
845 /* XXX: We could implement a fast path here where we check
846 * for irq_happened being just 0x01, in which case we can
847 * clear it and return. That means that we would potentially
848 * miss a decrementer having wrapped all the way around.
850 * Still, this might be useful for things like hash_page
852 bl .__check_irq_replay
854 beq restore_no_replay
857 * We need to re-emit an interrupt. We do so by re-using our
858 * existing exception frame. We first change the trap value,
859 * but we need to ensure we preserve the low nibble of it
867 * Then find the right handler and call it. Interrupts are
868 * still soft-disabled and we keep them that way.
872 addi r3,r1,STACK_FRAME_OVERHEAD;
875 1: cmpwi cr0,r3,0x900
877 addi r3,r1,STACK_FRAME_OVERHEAD;
880 #ifdef CONFIG_PPC_DOORBELL
882 #ifdef CONFIG_PPC_BOOK3E
889 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
890 #endif /* CONFIG_PPC_BOOK3E */
892 addi r3,r1,STACK_FRAME_OVERHEAD;
893 bl .doorbell_exception
895 #endif /* CONFIG_PPC_DOORBELL */
896 1: b .ret_from_except /* What else to do here ? */
899 addi r3,r1,STACK_FRAME_OVERHEAD
900 bl .unrecoverable_exception
903 #ifdef CONFIG_PPC_RTAS
905 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
906 * called with the MMU off.
908 * In addition, we need to be in 32b mode, at least for now.
910 * Note: r3 is an input parameter to rtas, so don't trash it...
915 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
917 /* Because RTAS is running in 32b mode, it clobbers the high order half
918 * of all registers that it saves. We therefore save those registers
919 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
921 SAVE_GPR(2, r1) /* Save the TOC */
922 SAVE_GPR(13, r1) /* Save paca */
923 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
924 SAVE_10GPRS(22, r1) /* ditto */
937 /* Temporary workaround to clear CR until RTAS can be modified to
944 /* There is no way it is acceptable to get here with interrupts enabled,
945 * check it with the asm equivalent of WARN_ON
947 lbz r0,PACASOFTIRQEN(r13)
949 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
952 /* Hard-disable interrupts */
958 /* Unfortunately, the stack pointer and the MSR are also clobbered,
959 * so they are saved in the PACA which allows us to restore
960 * our original state after RTAS returns.
963 std r6,PACASAVEDMSR(r13)
965 /* Setup our real return addr */
966 LOAD_REG_ADDR(r4,.rtas_return_loc)
967 clrldi r4,r4,2 /* convert to realmode address */
971 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
975 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
976 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI
978 sync /* disable interrupts so SRR0/1 */
979 mtmsrd r0 /* don't get trashed */
981 LOAD_REG_ADDR(r4, rtas)
982 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
983 ld r4,RTASBASE(r4) /* get the rtas->base value */
988 b . /* prevent speculative execution */
990 _STATIC(rtas_return_loc)
991 /* relocation is off at this point */
993 clrldi r4,r4,2 /* convert to realmode address */
997 ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */
1005 ld r1,PACAR1(r4) /* Restore our SP */
1006 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
1011 b . /* prevent speculative execution */
1014 1: .llong .rtas_restore_regs
1016 _STATIC(rtas_restore_regs)
1017 /* relocation is on at this point */
1018 REST_GPR(2, r1) /* Restore the TOC */
1019 REST_GPR(13, r1) /* Restore paca */
1020 REST_8GPRS(14, r1) /* Restore the non-volatiles */
1021 REST_10GPRS(22, r1) /* ditto */
1036 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
1037 ld r0,16(r1) /* get return address */
1040 blr /* return to caller */
1042 #endif /* CONFIG_PPC_RTAS */
1047 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
1049 /* Because PROM is running in 32b mode, it clobbers the high order half
1050 * of all registers that it saves. We therefore save those registers
1051 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
1062 /* Get the PROM entrypoint */
1065 /* Switch MSR to 32 bits mode
1067 #ifdef CONFIG_PPC_BOOK3E
1068 rlwinm r11,r11,0,1,31
1070 #else /* CONFIG_PPC_BOOK3E */
1073 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1076 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1079 #endif /* CONFIG_PPC_BOOK3E */
1082 /* Enter PROM here... */
1085 /* Just make sure that r1 top 32 bits didn't get
1090 /* Restore the MSR (back to 64 bits) */
1095 /* Restore other registers */
1103 addi r1,r1,PROM_FRAME_SIZE
1108 #ifdef CONFIG_FUNCTION_TRACER
1109 #ifdef CONFIG_DYNAMIC_FTRACE
1114 _GLOBAL(ftrace_caller)
1115 /* Taken from output of objdump from lib64/glibc */
1121 subi r3, r3, MCOUNT_INSN_SIZE
1126 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1127 .globl ftrace_graph_call
1130 _GLOBAL(ftrace_graph_stub)
1135 _GLOBAL(ftrace_stub)
1142 /* Taken from output of objdump from lib64/glibc */
1149 subi r3, r3, MCOUNT_INSN_SIZE
1150 LOAD_REG_ADDR(r5,ftrace_trace_function)
1158 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1159 b ftrace_graph_caller
1164 _GLOBAL(ftrace_stub)
1167 #endif /* CONFIG_DYNAMIC_FTRACE */
1169 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1170 _GLOBAL(ftrace_graph_caller)
1171 /* load r4 with local address */
1173 subi r4, r4, MCOUNT_INSN_SIZE
1175 /* get the parent address */
1179 bl .prepare_ftrace_return
1187 _GLOBAL(return_to_handler)
1188 /* need to save return values */
1195 bl .ftrace_return_to_handler
1198 /* return value has real return address */
1206 /* Jump back to real return address */
1209 _GLOBAL(mod_return_to_handler)
1210 /* need to save return values */
1220 * We are in a module using the module's TOC.
1221 * Switch to our TOC to run inside the core kernel.
1225 bl .ftrace_return_to_handler
1228 /* return value has real return address */
1237 /* Jump back to real return address */
1239 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1240 #endif /* CONFIG_FUNCTION_TRACER */