3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
35 #include <asm/hw_irq.h>
42 .tc .sys_call_table[TC],.sys_call_table
44 /* This value is used to mark exception frames on the stack. */
46 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
53 .globl system_call_common
57 addi r1,r1,-INT_FRAME_SIZE
65 ACCOUNT_CPU_USER_ENTRY(r10, r11)
84 * This clears CR0.SO (bit 28), which is the error indication on
85 * return from this system call.
87 rldimi r2,r11,28,(63-28)
94 addi r9,r1,STACK_FRAME_OVERHEAD
95 ld r11,exception_marker@toc(r2)
96 std r11,-16(r9) /* "regshere" marker */
97 #if defined(CONFIG_VIRT_CPU_ACCOUNTING) && defined(CONFIG_PPC_SPLPAR)
100 /* if from user, see if there are any DTL entries to process */
101 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
102 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
103 ld r10,LPPACA_DTLIDX(r10) /* get log write index */
106 bl .accumulate_stolen_time
110 addi r9,r1,STACK_FRAME_OVERHEAD
112 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
113 #endif /* CONFIG_VIRT_CPU_ACCOUNTING && CONFIG_PPC_SPLPAR */
116 * A syscall should always be called with interrupts enabled
117 * so we just unconditionally hard-enable here. When some kind
118 * of irq tracing is used, we additionally check that condition
121 #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
122 lbz r10,PACASOFTIRQEN(r13)
125 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
128 #ifdef CONFIG_PPC_BOOK3E
134 #endif /* CONFIG_PPC_BOOK3E */
136 /* We do need to set SOFTE in the stack frame or the return
137 * from interrupt will be painful
147 addi r9,r1,STACK_FRAME_OVERHEAD
149 CURRENT_THREAD_INFO(r11, r1)
151 andi. r11,r10,_TIF_SYSCALL_T_OR_A
153 .Lsyscall_dotrace_cont:
154 cmpldi 0,r0,NR_syscalls
157 system_call: /* label this so stack traces look sane */
159 * Need to vector to 32 Bit or default sys_call_table here,
160 * based on caller's run-mode / personality.
162 ld r11,.SYS_CALL_TABLE@toc(2)
163 andi. r10,r10,_TIF_32BIT
165 addi r11,r11,8 /* use 32-bit syscall entries */
174 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
176 bctrl /* Call handler */
181 bl .do_show_syscall_exit
184 CURRENT_THREAD_INFO(r12, r1)
187 #ifdef CONFIG_PPC_BOOK3S
188 /* No MSR:RI on BookE */
193 * Disable interrupts so current_thread_info()->flags can't change,
194 * and so that we don't get interrupted after loading SRR0/1.
196 #ifdef CONFIG_PPC_BOOK3E
201 * For performance reasons we clear RI the same time that we
202 * clear EE. We only need to clear RI just before we restore r13
203 * below, but batching it with EE saves us one expensive mtmsrd call.
204 * We have to be careful to restore RI if we branch anywhere from
205 * here (eg syscall_exit_work).
210 #endif /* CONFIG_PPC_BOOK3E */
214 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
215 bne- syscall_exit_work
219 .Lsyscall_error_cont:
222 stdcx. r0,0,r1 /* to clear the reservation */
223 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
228 ACCOUNT_CPU_USER_EXIT(r11, r12)
229 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
237 b . /* prevent speculative execution */
240 oris r5,r5,0x1000 /* Set SO bit in CR */
243 b .Lsyscall_error_cont
245 /* Traced system call support */
248 addi r3,r1,STACK_FRAME_OVERHEAD
249 bl .do_syscall_trace_enter
251 * Restore argument registers possibly just changed.
252 * We use the return value of do_syscall_trace_enter
253 * for the call number to look up in the table (r0).
262 addi r9,r1,STACK_FRAME_OVERHEAD
263 CURRENT_THREAD_INFO(r10, r1)
265 b .Lsyscall_dotrace_cont
272 #ifdef CONFIG_PPC_BOOK3S
273 mtmsrd r10,1 /* Restore RI */
275 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
276 If TIF_NOERROR is set, just save r3 as it is. */
278 andi. r0,r9,_TIF_RESTOREALL
282 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
284 andi. r0,r9,_TIF_NOERROR
288 oris r5,r5,0x1000 /* Set SO bit in CR */
291 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
294 /* Clear per-syscall TIF flags if any are set. */
296 li r11,_TIF_PERSYSCALL_MASK
297 addi r12,r12,TI_FLAGS
302 subi r12,r12,TI_FLAGS
304 4: /* Anything else left to do? */
305 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
306 beq .ret_from_except_lite
308 /* Re-enable interrupts */
309 #ifdef CONFIG_PPC_BOOK3E
315 #endif /* CONFIG_PPC_BOOK3E */
318 addi r3,r1,STACK_FRAME_OVERHEAD
319 bl .do_syscall_trace_leave
322 /* Save non-volatile GPRs, if not already saved. */
334 * The sigsuspend and rt_sigsuspend system calls can call do_signal
335 * and thus put the process into the stopped state where we might
336 * want to examine its user state with ptrace. Therefore we need
337 * to save all the nonvolatile registers (r14 - r31) before calling
338 * the C code. Similarly, fork, vfork and clone need the full
339 * register state on the stack so that it can be copied to the child.
357 _GLOBAL(ppc32_swapcontext)
359 bl .compat_sys_swapcontext
362 _GLOBAL(ppc64_swapcontext)
367 _GLOBAL(ret_from_fork)
374 * This routine switches between two different tasks. The process
375 * state of one is saved on its kernel stack. Then the state
376 * of the other is restored from its kernel stack. The memory
377 * management hardware is updated to the second process's state.
378 * Finally, we can return to the second process, via ret_from_except.
379 * On entry, r3 points to the THREAD for the current task, r4
380 * points to the THREAD for the new task.
382 * Note: there are two ways to get to the "going out" portion
383 * of this code; either by coming in via the entry (_switch)
384 * or via "fork" which must set up an environment equivalent
385 * to the "_switch" path. If you change this you'll have to change
386 * the fork code also.
388 * The code which creates the new task context is in 'copy_thread'
389 * in arch/powerpc/kernel/process.c
395 stdu r1,-SWITCH_FRAME_SIZE(r1)
396 /* r3-r13 are caller saved -- Cort */
399 mflr r20 /* Return to switch caller */
404 oris r0,r0,MSR_VSX@h /* Disable VSX */
405 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
406 #endif /* CONFIG_VSX */
407 #ifdef CONFIG_ALTIVEC
409 oris r0,r0,MSR_VEC@h /* Disable altivec */
410 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
411 std r24,THREAD_VRSAVE(r3)
412 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
413 #endif /* CONFIG_ALTIVEC */
417 std r25,THREAD_DSCR(r3)
418 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
428 std r1,KSP(r3) /* Set old stack pointer */
431 /* We need a sync somewhere here to make sure that if the
432 * previous task gets rescheduled on another CPU, it sees all
433 * stores it has performed on this one.
436 #endif /* CONFIG_SMP */
439 * If we optimise away the clear of the reservation in system
440 * calls because we know the CPU tracks the address of the
441 * reservation, then we need to clear it here to cover the
442 * case that the kernel context switch path has no larx
447 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
449 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
450 std r6,PACACURRENT(r13) /* Set new 'current' */
452 ld r8,KSP(r4) /* new stack pointer */
453 #ifdef CONFIG_PPC_BOOK3S
455 BEGIN_FTR_SECTION_NESTED(95)
456 clrrdi r6,r8,28 /* get its ESID */
457 clrrdi r9,r1,28 /* get current sp ESID */
458 FTR_SECTION_ELSE_NESTED(95)
459 clrrdi r6,r8,40 /* get its 1T ESID */
460 clrrdi r9,r1,40 /* get current sp 1T ESID */
461 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
464 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
465 clrldi. r0,r6,2 /* is new ESID c00000000? */
466 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
468 beq 2f /* if yes, don't slbie it */
470 /* Bolt in the new stack SLB entry */
471 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
472 oris r0,r6,(SLB_ESID_V)@h
473 ori r0,r0,(SLB_NUM_BOLTED-1)@l
475 li r9,MMU_SEGSIZE_1T /* insert B field */
476 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
477 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
478 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
480 /* Update the last bolted SLB. No write barriers are needed
481 * here, provided we only update the current CPU's SLB shadow
484 ld r9,PACA_SLBSHADOWPTR(r13)
486 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
487 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
488 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
490 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
491 * we have 1TB segments, the only CPUs known to have the errata
492 * only support less than 1TB of system memory and we'll never
493 * actually hit this code path.
497 slbie r6 /* Workaround POWER5 < DD2.1 issue */
501 #endif /* !CONFIG_PPC_BOOK3S */
503 CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
504 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
505 because we don't need to leave the 288-byte ABI gap at the
506 top of the kernel stack. */
507 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
509 mr r1,r8 /* start using new stack pointer */
510 std r7,PACAKSAVE(r13)
515 #ifdef CONFIG_ALTIVEC
517 ld r0,THREAD_VRSAVE(r4)
518 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
519 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
520 #endif /* CONFIG_ALTIVEC */
523 ld r0,THREAD_DSCR(r4)
528 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
531 /* r3-r13 are destroyed -- Cort */
535 /* convert old thread to its task_struct for return value */
537 ld r7,_NIP(r1) /* Return to _switch caller in new task */
539 addi r1,r1,SWITCH_FRAME_SIZE
543 _GLOBAL(ret_from_except)
546 bne .ret_from_except_lite
549 _GLOBAL(ret_from_except_lite)
551 * Disable interrupts so that current_thread_info()->flags
552 * can't change between when we test it and when we return
553 * from the interrupt.
555 #ifdef CONFIG_PPC_BOOK3E
558 ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
559 mtmsrd r10,1 /* Update machine state */
560 #endif /* CONFIG_PPC_BOOK3E */
562 CURRENT_THREAD_INFO(r9, r1)
568 /* Check current_thread_info()->flags */
569 andi. r0,r4,_TIF_USER_WORK_MASK
572 andi. r0,r4,_TIF_NEED_RESCHED
574 bl .restore_interrupts
576 b .ret_from_except_lite
579 bl .restore_interrupts
580 addi r3,r1,STACK_FRAME_OVERHEAD
585 #ifdef CONFIG_PREEMPT
586 /* Check if we need to preempt */
587 andi. r0,r4,_TIF_NEED_RESCHED
589 /* Check that preempt_count() == 0 and interrupts are enabled */
590 lwz r8,TI_PREEMPT(r9)
594 crandc eq,cr1*4+eq,eq
598 * Here we are preempting the current task. We want to make
599 * sure we are soft-disabled first
601 SOFT_DISABLE_INTS(r3,r4)
602 1: bl .preempt_schedule_irq
604 /* Re-test flags and eventually loop */
605 CURRENT_THREAD_INFO(r9, r1)
607 andi. r0,r4,_TIF_NEED_RESCHED
609 #endif /* CONFIG_PREEMPT */
611 .globl fast_exc_return_irq
615 * This is the main kernel exit path. First we check if we
616 * are about to re-enable interrupts
619 lbz r6,PACASOFTIRQEN(r13)
623 /* We are enabling, were we already enabled ? Yes, just return */
628 * We are about to soft-enable interrupts (we are hard disabled
629 * at this point). We check if there's anything that needs to
632 lbz r0,PACAIRQHAPPENED(r13)
634 bne- restore_check_irq_replay
637 * Get here when nothing happened while soft-disabled, just
638 * soft-enable and move-on. We will hard-enable as a side
644 stb r0,PACASOFTIRQEN(r13);
647 * Final return path. BookE is handled in a different file
650 #ifdef CONFIG_PPC_BOOK3E
651 b .exception_return_book3e
654 * Clear the reservation. If we know the CPU tracks the address of
655 * the reservation then we can potentially save some cycles and use
656 * a larx. On POWER6 and POWER7 this is significantly faster.
659 stdcx. r0,0,r1 /* to clear the reservation */
662 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
665 * Some code path such as load_up_fpu or altivec return directly
666 * here. They run entirely hard disabled and do not alter the
667 * interrupt state. They also don't use lwarx/stwcx. and thus
668 * are known not to leave dangling reservations.
670 .globl fast_exception_return
671 fast_exception_return:
686 * Clear RI before restoring r13. If we are returning to
687 * userspace and we take an exception after restoring r13,
688 * we end up corrupting the userspace r13 value.
690 ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
691 andc r4,r4,r0 /* r0 contains MSR_RI here */
695 * r13 is our per cpu area, only restore it if we are returning to
696 * userspace the value stored in the stack frame may belong to
701 ACCOUNT_CPU_USER_EXIT(r2, r4)
718 b . /* prevent speculative execution */
720 #endif /* CONFIG_PPC_BOOK3E */
723 * We are returning to a context with interrupts soft disabled.
725 * However, we may also about to hard enable, so we need to
726 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
727 * or that bit can get out of sync and bad things will happen
731 lbz r7,PACAIRQHAPPENED(r13)
734 rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
735 stb r7,PACAIRQHAPPENED(r13)
737 stb r0,PACASOFTIRQEN(r13);
742 * Something did happen, check if a re-emit is needed
743 * (this also clears paca->irq_happened)
745 restore_check_irq_replay:
746 /* XXX: We could implement a fast path here where we check
747 * for irq_happened being just 0x01, in which case we can
748 * clear it and return. That means that we would potentially
749 * miss a decrementer having wrapped all the way around.
751 * Still, this might be useful for things like hash_page
753 bl .__check_irq_replay
755 beq restore_no_replay
758 * We need to re-emit an interrupt. We do so by re-using our
759 * existing exception frame. We first change the trap value,
760 * but we need to ensure we preserve the low nibble of it
768 * Then find the right handler and call it. Interrupts are
769 * still soft-disabled and we keep them that way.
773 addi r3,r1,STACK_FRAME_OVERHEAD;
776 1: cmpwi cr0,r3,0x900
778 addi r3,r1,STACK_FRAME_OVERHEAD;
781 #ifdef CONFIG_PPC_BOOK3E
782 1: cmpwi cr0,r3,0x280
784 addi r3,r1,STACK_FRAME_OVERHEAD;
785 bl .doorbell_exception
787 #endif /* CONFIG_PPC_BOOK3E */
788 1: b .ret_from_except /* What else to do here ? */
791 addi r3,r1,STACK_FRAME_OVERHEAD
792 bl .unrecoverable_exception
795 #ifdef CONFIG_PPC_RTAS
797 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
798 * called with the MMU off.
800 * In addition, we need to be in 32b mode, at least for now.
802 * Note: r3 is an input parameter to rtas, so don't trash it...
807 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
809 /* Because RTAS is running in 32b mode, it clobbers the high order half
810 * of all registers that it saves. We therefore save those registers
811 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
813 SAVE_GPR(2, r1) /* Save the TOC */
814 SAVE_GPR(13, r1) /* Save paca */
815 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
816 SAVE_10GPRS(22, r1) /* ditto */
829 /* Temporary workaround to clear CR until RTAS can be modified to
836 /* There is no way it is acceptable to get here with interrupts enabled,
837 * check it with the asm equivalent of WARN_ON
839 lbz r0,PACASOFTIRQEN(r13)
841 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
844 /* Hard-disable interrupts */
850 /* Unfortunately, the stack pointer and the MSR are also clobbered,
851 * so they are saved in the PACA which allows us to restore
852 * our original state after RTAS returns.
855 std r6,PACASAVEDMSR(r13)
857 /* Setup our real return addr */
858 LOAD_REG_ADDR(r4,.rtas_return_loc)
859 clrldi r4,r4,2 /* convert to realmode address */
863 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
867 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
868 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI
870 sync /* disable interrupts so SRR0/1 */
871 mtmsrd r0 /* don't get trashed */
873 LOAD_REG_ADDR(r4, rtas)
874 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
875 ld r4,RTASBASE(r4) /* get the rtas->base value */
880 b . /* prevent speculative execution */
882 _STATIC(rtas_return_loc)
883 /* relocation is off at this point */
885 clrldi r4,r4,2 /* convert to realmode address */
889 ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */
897 ld r1,PACAR1(r4) /* Restore our SP */
898 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
903 b . /* prevent speculative execution */
906 1: .llong .rtas_restore_regs
908 _STATIC(rtas_restore_regs)
909 /* relocation is on at this point */
910 REST_GPR(2, r1) /* Restore the TOC */
911 REST_GPR(13, r1) /* Restore paca */
912 REST_8GPRS(14, r1) /* Restore the non-volatiles */
913 REST_10GPRS(22, r1) /* ditto */
928 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
929 ld r0,16(r1) /* get return address */
932 blr /* return to caller */
934 #endif /* CONFIG_PPC_RTAS */
939 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
941 /* Because PROM is running in 32b mode, it clobbers the high order half
942 * of all registers that it saves. We therefore save those registers
943 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
954 /* Get the PROM entrypoint */
957 /* Switch MSR to 32 bits mode
959 #ifdef CONFIG_PPC_BOOK3E
960 rlwinm r11,r11,0,1,31
962 #else /* CONFIG_PPC_BOOK3E */
965 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
968 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
971 #endif /* CONFIG_PPC_BOOK3E */
974 /* Enter PROM here... */
977 /* Just make sure that r1 top 32 bits didn't get
982 /* Restore the MSR (back to 64 bits) */
987 /* Restore other registers */
995 addi r1,r1,PROM_FRAME_SIZE
1000 #ifdef CONFIG_FUNCTION_TRACER
1001 #ifdef CONFIG_DYNAMIC_FTRACE
1006 _GLOBAL(ftrace_caller)
1007 /* Taken from output of objdump from lib64/glibc */
1013 subi r3, r3, MCOUNT_INSN_SIZE
1018 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1019 .globl ftrace_graph_call
1022 _GLOBAL(ftrace_graph_stub)
1027 _GLOBAL(ftrace_stub)
1034 /* Taken from output of objdump from lib64/glibc */
1041 subi r3, r3, MCOUNT_INSN_SIZE
1042 LOAD_REG_ADDR(r5,ftrace_trace_function)
1050 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1051 b ftrace_graph_caller
1056 _GLOBAL(ftrace_stub)
1059 #endif /* CONFIG_DYNAMIC_FTRACE */
1061 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1062 _GLOBAL(ftrace_graph_caller)
1063 /* load r4 with local address */
1065 subi r4, r4, MCOUNT_INSN_SIZE
1067 /* get the parent address */
1071 bl .prepare_ftrace_return
1079 _GLOBAL(return_to_handler)
1080 /* need to save return values */
1087 bl .ftrace_return_to_handler
1090 /* return value has real return address */
1098 /* Jump back to real return address */
1101 _GLOBAL(mod_return_to_handler)
1102 /* need to save return values */
1112 * We are in a module using the module's TOC.
1113 * Switch to our TOC to run inside the core kernel.
1117 bl .ftrace_return_to_handler
1120 /* return value has real return address */
1129 /* Jump back to real return address */
1131 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1132 #endif /* CONFIG_FUNCTION_TRACER */