2 * Boot code and exception vectors for Book3E processors
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/threads.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cputable.h>
18 #include <asm/setup.h>
19 #include <asm/thread_info.h>
20 #include <asm/reg_a2.h>
21 #include <asm/exception-64e.h>
23 #include <asm/irqflags.h>
24 #include <asm/ptrace.h>
25 #include <asm/ppc-opcode.h>
27 #include <asm/hw_irq.h>
28 #include <asm/kvm_asm.h>
29 #include <asm/kvm_booke_hv_asm.h>
31 /* XXX This will ultimately add space for a special exception save
32 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
33 * when taking special interrupts. For now we don't support that,
34 * special interrupts from within a non-standard level will probably
37 #define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
39 /* Exception prolog code for all exceptions */
40 #define EXCEPTION_PROLOG(n, intnum, type, addition) \
41 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
42 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
43 std r10,PACA_EX##type+EX_R10(r13); \
44 std r11,PACA_EX##type+EX_R11(r13); \
45 mfcr r10; /* save CR */ \
46 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
47 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \
48 addition; /* additional code for that exc. */ \
49 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
50 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
51 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
52 type##_SET_KSTACK; /* get special stack if necessary */\
53 andi. r10,r11,MSR_PR; /* save stack pointer */ \
54 beq 1f; /* branch around if supervisor */ \
55 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
56 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
57 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
58 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
60 /* Exception type-specific macros */
61 #define GEN_SET_KSTACK \
62 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
63 #define SPRN_GEN_SRR0 SPRN_SRR0
64 #define SPRN_GEN_SRR1 SPRN_SRR1
66 #define GDBELL_SET_KSTACK GEN_SET_KSTACK
67 #define SPRN_GDBELL_SRR0 SPRN_GSRR0
68 #define SPRN_GDBELL_SRR1 SPRN_GSRR1
70 #define CRIT_SET_KSTACK \
71 ld r1,PACA_CRIT_STACK(r13); \
72 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
73 #define SPRN_CRIT_SRR0 SPRN_CSRR0
74 #define SPRN_CRIT_SRR1 SPRN_CSRR1
76 #define DBG_SET_KSTACK \
77 ld r1,PACA_DBG_STACK(r13); \
78 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
79 #define SPRN_DBG_SRR0 SPRN_DSRR0
80 #define SPRN_DBG_SRR1 SPRN_DSRR1
82 #define MC_SET_KSTACK \
83 ld r1,PACA_MC_STACK(r13); \
84 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
85 #define SPRN_MC_SRR0 SPRN_MCSRR0
86 #define SPRN_MC_SRR1 SPRN_MCSRR1
88 #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \
89 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
91 #define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \
92 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
94 #define DBG_EXCEPTION_PROLOG(n, intnum, addition) \
95 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
97 #define MC_EXCEPTION_PROLOG(n, intnum, addition) \
98 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
100 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \
101 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
103 /* Variants of the "addition" argument for the prolog
105 #define PROLOG_ADDITION_NONE_GEN(n)
106 #define PROLOG_ADDITION_NONE_GDBELL(n)
107 #define PROLOG_ADDITION_NONE_CRIT(n)
108 #define PROLOG_ADDITION_NONE_DBG(n)
109 #define PROLOG_ADDITION_NONE_MC(n)
111 #define PROLOG_ADDITION_MASKABLE_GEN(n) \
112 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
113 cmpwi cr0,r11,0; /* yes -> go out of line */ \
114 beq masked_interrupt_book3e_##n
116 #define PROLOG_ADDITION_2REGS_GEN(n) \
117 std r14,PACA_EXGEN+EX_R14(r13); \
118 std r15,PACA_EXGEN+EX_R15(r13)
120 #define PROLOG_ADDITION_1REG_GEN(n) \
121 std r14,PACA_EXGEN+EX_R14(r13);
123 #define PROLOG_ADDITION_2REGS_CRIT(n) \
124 std r14,PACA_EXCRIT+EX_R14(r13); \
125 std r15,PACA_EXCRIT+EX_R15(r13)
127 #define PROLOG_ADDITION_2REGS_DBG(n) \
128 std r14,PACA_EXDBG+EX_R14(r13); \
129 std r15,PACA_EXDBG+EX_R15(r13)
131 #define PROLOG_ADDITION_2REGS_MC(n) \
132 std r14,PACA_EXMC+EX_R14(r13); \
133 std r15,PACA_EXMC+EX_R15(r13)
136 /* Core exception code for all exceptions except TLB misses.
137 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
139 #define EXCEPTION_COMMON(n, excf, ints) \
141 std r0,GPR0(r1); /* save r0 in stackframe */ \
142 std r2,GPR2(r1); /* save r2 in stackframe */ \
143 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
144 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
145 std r9,GPR9(r1); /* save r9 in stackframe */ \
146 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
147 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
148 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
149 ld r3,excf+EX_R10(r13); /* get back r10 */ \
150 ld r4,excf+EX_R11(r13); /* get back r11 */ \
151 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
152 std r12,GPR12(r1); /* save r12 in stackframe */ \
153 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
154 mflr r6; /* save LR in stackframe */ \
155 mfctr r7; /* save CTR in stackframe */ \
156 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
157 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
158 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
159 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
160 ld r12,exception_marker@toc(r2); \
162 std r3,GPR10(r1); /* save r10 to stackframe */ \
163 std r4,GPR11(r1); /* save r11 to stackframe */ \
164 std r5,GPR13(r1); /* save it to stackframe */ \
168 li r3,(n)+1; /* indicate partial regs in trap */ \
169 std r9,0(r1); /* store stack frame back link */ \
170 std r10,_CCR(r1); /* store orig CR in stackframe */ \
171 std r9,GPR1(r1); /* store stack frame back link */ \
172 std r11,SOFTE(r1); /* and save it to stackframe */ \
173 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
174 std r3,_TRAP(r1); /* set trap number */ \
175 std r0,RESULT(r1); /* clear regs->result */ \
178 /* Variants for the "ints" argument. This one does nothing when we want
179 * to keep interrupts in their original state
183 /* This second version is meant for exceptions that don't immediately
184 * hard-enable. We set a bit in paca->irq_happened to ensure that
185 * a subsequent call to arch_local_irq_restore() will properly
186 * hard-enable and avoid the fast-path
188 #define INTS_DISABLE SOFT_DISABLE_INTS(r3,r4)
190 /* This is called by exceptions that used INTS_KEEP (that did not touch
191 * irq indicators in the PACA). This will restore MSR:EE to it's previous
194 * XXX In the long run, we may want to open-code it in order to separate the
195 * load from the wrtee, thus limiting the latency caused by the dependency
196 * but at this point, I'll favor code clarity until we have a near to final
199 #define INTS_RESTORE_HARD \
203 /* XXX FIXME: Restore r14/r15 when necessary */
204 #define BAD_STACK_TRAMPOLINE(n) \
205 exc_##n##_bad_stack: \
206 li r1,(n); /* get exception number */ \
207 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
208 b bad_stack_book3e; /* bad stack error */
210 /* WARNING: If you change the layout of this stub, make sure you chcek
211 * the debug exception handler which handles single stepping
212 * into exceptions from userspace, and the MM code in
213 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
214 * and would need to be updated if that branch is moved
216 #define EXCEPTION_STUB(loc, label) \
217 . = interrupt_base_book3e + loc; \
218 nop; /* To make debug interrupts happy */ \
219 b exc_##label##_book3e;
229 /* Used by asynchronous interrupt that may happen in the idle loop.
231 * This check if the thread was in the idle loop, and if yes, returns
232 * to the caller rather than the PC. This is to avoid a race if
233 * interrupts happen before the wait instruction.
235 #define CHECK_NAPPING() \
236 CURRENT_THREAD_INFO(r11, r1); \
237 ld r10,TI_LOCAL_FLAGS(r11); \
238 andi. r9,r10,_TLF_NAPPING; \
241 rlwinm r7,r10,0,~_TLF_NAPPING; \
243 std r7,TI_LOCAL_FLAGS(r11); \
247 #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \
248 START_EXCEPTION(label); \
249 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
250 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE) \
253 addi r3,r1,STACK_FRAME_OVERHEAD; \
255 b .ret_from_except_lite;
257 /* This value is used to mark exception frames on the stack. */
260 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
264 * And here we have the exception vectors !
269 .globl interrupt_base_book3e
270 interrupt_base_book3e: /* fake trap */
271 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
272 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
273 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
274 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
275 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
276 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
277 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
278 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
279 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
280 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
281 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
282 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
283 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
284 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
285 EXCEPTION_STUB(0x1c0, data_tlb_miss)
286 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
287 EXCEPTION_STUB(0x260, perfmon)
288 EXCEPTION_STUB(0x280, doorbell)
289 EXCEPTION_STUB(0x2a0, doorbell_crit)
290 EXCEPTION_STUB(0x2c0, guest_doorbell)
291 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
292 EXCEPTION_STUB(0x300, hypercall)
293 EXCEPTION_STUB(0x320, ehpriv)
295 .globl interrupt_end_book3e
296 interrupt_end_book3e:
298 /* Critical Input Interrupt */
299 START_EXCEPTION(critical_input);
300 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
301 PROLOG_ADDITION_NONE)
302 // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE)
303 // bl special_reg_save_crit
305 // addi r3,r1,STACK_FRAME_OVERHEAD
306 // bl .critical_exception
307 // b ret_from_crit_except
310 /* Machine Check Interrupt */
311 START_EXCEPTION(machine_check);
312 MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK,
313 PROLOG_ADDITION_NONE)
314 // EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
315 // bl special_reg_save_mc
316 // addi r3,r1,STACK_FRAME_OVERHEAD
318 // bl .machine_check_exception
319 // b ret_from_mc_except
322 /* Data Storage Interrupt */
323 START_EXCEPTION(data_storage)
324 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
325 PROLOG_ADDITION_2REGS)
328 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE)
329 b storage_fault_common
331 /* Instruction Storage Interrupt */
332 START_EXCEPTION(instruction_storage);
333 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
334 PROLOG_ADDITION_2REGS)
337 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE)
338 b storage_fault_common
340 /* External Input Interrupt */
341 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
342 external_input, .do_IRQ, ACK_NONE)
345 START_EXCEPTION(alignment);
346 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
347 PROLOG_ADDITION_2REGS)
350 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
351 b alignment_more /* no room, go out of line */
353 /* Program Interrupt */
354 START_EXCEPTION(program);
355 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
356 PROLOG_ADDITION_1REG)
358 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE)
360 addi r3,r1,STACK_FRAME_OVERHEAD
361 ld r14,PACA_EXGEN+EX_R14(r13)
363 bl .program_check_exception
366 /* Floating Point Unavailable Interrupt */
367 START_EXCEPTION(fp_unavailable);
368 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
369 PROLOG_ADDITION_NONE)
370 /* we can probably do a shorter exception entry for that one... */
371 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
376 b fast_exception_return
379 addi r3,r1,STACK_FRAME_OVERHEAD
380 bl .kernel_fp_unavailable_exception
383 /* Decrementer Interrupt */
384 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
385 decrementer, .timer_interrupt, ACK_DEC)
387 /* Fixed Interval Timer Interrupt */
388 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
389 fixed_interval, .unknown_exception, ACK_FIT)
391 /* Watchdog Timer Interrupt */
392 START_EXCEPTION(watchdog);
393 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
394 PROLOG_ADDITION_NONE)
395 // EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE)
396 // bl special_reg_save_crit
398 // addi r3,r1,STACK_FRAME_OVERHEAD
399 // bl .unknown_exception
400 // b ret_from_crit_except
403 /* System Call Interrupt */
404 START_EXCEPTION(system_call)
405 mr r9,r13 /* keep a copy of userland r13 */
406 mfspr r11,SPRN_SRR0 /* get return address */
407 mfspr r12,SPRN_SRR1 /* get previous MSR */
408 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
411 /* Auxiliary Processor Unavailable Interrupt */
412 START_EXCEPTION(ap_unavailable);
413 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
414 PROLOG_ADDITION_NONE)
415 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE)
417 addi r3,r1,STACK_FRAME_OVERHEAD
418 bl .unknown_exception
421 /* Debug exception as a critical interrupt*/
422 START_EXCEPTION(debug_crit);
423 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
424 PROLOG_ADDITION_2REGS)
427 * If there is a single step or branch-taken exception in an
428 * exception entry sequence, it was probably meant to apply to
429 * the code where the exception occurred (since exception entry
430 * doesn't turn off DE automatically). We simulate the effect
431 * of turning off DE on entry to an exception handler by turning
432 * off DE in the CSRR1 value and clearing the debug status.
435 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
436 andis. r15,r14,DBSR_IC@h
439 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
440 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
446 /* here it looks like we got an inappropriate debug exception. */
447 lis r14,DBSR_IC@h /* clear the IC event */
448 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
451 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
452 ld r1,PACA_EXCRIT+EX_R1(r13)
453 ld r14,PACA_EXCRIT+EX_R14(r13)
454 ld r15,PACA_EXCRIT+EX_R15(r13)
456 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
457 ld r11,PACA_EXCRIT+EX_R11(r13)
458 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
461 /* Normal debug exception */
462 /* XXX We only handle coming from userspace for now since we can't
463 * quite save properly an interrupted kernel state yet
465 1: andi. r14,r11,MSR_PR; /* check for userspace again */
466 beq kernel_dbg_exc; /* if from kernel mode */
468 /* Now we mash up things to make it look like we are coming on a
471 mfspr r15,SPRN_SPRG_CRIT_SCRATCH
472 mtspr SPRN_SPRG_GEN_SCRATCH,r15
474 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE)
476 addi r3,r1,STACK_FRAME_OVERHEAD
478 ld r14,PACA_EXCRIT+EX_R14(r13)
479 ld r15,PACA_EXCRIT+EX_R15(r13)
487 /* Debug exception as a debug interrupt*/
488 START_EXCEPTION(debug_debug);
489 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
490 PROLOG_ADDITION_2REGS)
493 * If there is a single step or branch-taken exception in an
494 * exception entry sequence, it was probably meant to apply to
495 * the code where the exception occurred (since exception entry
496 * doesn't turn off DE automatically). We simulate the effect
497 * of turning off DE on entry to an exception handler by turning
498 * off DE in the DSRR1 value and clearing the debug status.
501 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
502 andis. r15,r14,DBSR_IC@h
505 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
506 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
512 /* here it looks like we got an inappropriate debug exception. */
513 lis r14,DBSR_IC@h /* clear the IC event */
514 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
517 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
518 ld r1,PACA_EXDBG+EX_R1(r13)
519 ld r14,PACA_EXDBG+EX_R14(r13)
520 ld r15,PACA_EXDBG+EX_R15(r13)
522 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
523 ld r11,PACA_EXDBG+EX_R11(r13)
524 mfspr r13,SPRN_SPRG_DBG_SCRATCH
527 /* Normal debug exception */
528 /* XXX We only handle coming from userspace for now since we can't
529 * quite save properly an interrupted kernel state yet
531 1: andi. r14,r11,MSR_PR; /* check for userspace again */
532 beq kernel_dbg_exc; /* if from kernel mode */
534 /* Now we mash up things to make it look like we are coming on a
537 mfspr r15,SPRN_SPRG_DBG_SCRATCH
538 mtspr SPRN_SPRG_GEN_SCRATCH,r15
540 EXCEPTION_COMMON(0xd08, PACA_EXDBG, INTS_DISABLE)
542 addi r3,r1,STACK_FRAME_OVERHEAD
544 ld r14,PACA_EXDBG+EX_R14(r13)
545 ld r15,PACA_EXDBG+EX_R15(r13)
550 START_EXCEPTION(perfmon);
551 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
552 PROLOG_ADDITION_NONE)
553 EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE)
554 addi r3,r1,STACK_FRAME_OVERHEAD
555 bl .performance_monitor_exception
556 b .ret_from_except_lite
558 /* Doorbell interrupt */
559 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
560 doorbell, .doorbell_exception, ACK_NONE)
562 /* Doorbell critical Interrupt */
563 START_EXCEPTION(doorbell_crit);
564 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
565 PROLOG_ADDITION_NONE)
566 // EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE)
567 // bl special_reg_save_crit
569 // addi r3,r1,STACK_FRAME_OVERHEAD
570 // bl .doorbell_critical_exception
571 // b ret_from_crit_except
575 * Guest doorbell interrupt
576 * This general exception use GSRRx save/restore registers
578 START_EXCEPTION(guest_doorbell);
579 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
580 PROLOG_ADDITION_NONE)
581 EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP)
582 addi r3,r1,STACK_FRAME_OVERHEAD
585 bl .unknown_exception
588 /* Guest Doorbell critical Interrupt */
589 START_EXCEPTION(guest_doorbell_crit);
590 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
591 PROLOG_ADDITION_NONE)
592 // EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE)
593 // bl special_reg_save_crit
595 // addi r3,r1,STACK_FRAME_OVERHEAD
596 // bl .guest_doorbell_critical_exception
597 // b ret_from_crit_except
600 /* Hypervisor call */
601 START_EXCEPTION(hypercall);
602 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
603 PROLOG_ADDITION_NONE)
604 EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP)
605 addi r3,r1,STACK_FRAME_OVERHEAD
608 bl .unknown_exception
611 /* Embedded Hypervisor priviledged */
612 START_EXCEPTION(ehpriv);
613 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
614 PROLOG_ADDITION_NONE)
615 EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP)
616 addi r3,r1,STACK_FRAME_OVERHEAD
619 bl .unknown_exception
623 * An interrupt came in while soft-disabled; We mark paca->irq_happened
624 * accordingly and if the interrupt is level sensitive, we hard disable
627 masked_interrupt_book3e_0x500:
628 /* XXX When adding support for EPR, use PACA_IRQ_EE_EDGE */
630 b masked_interrupt_book3e_full_mask
632 masked_interrupt_book3e_0x900:
635 b masked_interrupt_book3e_no_mask
636 masked_interrupt_book3e_0x980:
639 b masked_interrupt_book3e_no_mask
640 masked_interrupt_book3e_0x280:
641 masked_interrupt_book3e_0x2c0:
642 li r11,PACA_IRQ_DBELL
643 b masked_interrupt_book3e_no_mask
645 masked_interrupt_book3e_no_mask:
647 lbz r10,PACAIRQHAPPENED(r13)
649 stb r10,PACAIRQHAPPENED(r13)
651 masked_interrupt_book3e_full_mask:
653 lbz r10,PACAIRQHAPPENED(r13)
655 stb r10,PACAIRQHAPPENED(r13)
657 rldicl r11,r10,48,1 /* clear MSR_EE */
660 1: ld r10,PACA_EXGEN+EX_R10(r13);
661 ld r11,PACA_EXGEN+EX_R11(r13);
662 mfspr r13,SPRN_SPRG_GEN_SCRATCH;
666 * Called from arch_local_irq_enable when an interrupt needs
667 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280
668 * to indicate the kind of interrupt. MSR:EE is already off.
669 * We generate a stackframe like if a real interrupt had happened.
671 * Note: While MSR:EE is off, we need to make sure that _MSR
672 * in the generated frame has EE set to 1 or the exception
673 * handler will not properly re-enable them.
675 _GLOBAL(__replay_interrupt)
676 /* We are going to jump to the exception common code which
677 * will retrieve various register values from the PACA which
678 * we don't give a damn about.
683 mtspr SPRN_SPRG_GEN_SCRATCH,r13;
684 std r1,PACA_EXGEN+EX_R1(r13);
685 stw r4,PACA_EXGEN+EX_CR(r13);
687 subi r1,r1,INT_FRAME_SIZE;
698 * This is called from 0x300 and 0x400 handlers after the prologs with
699 * r14 and r15 containing the fault address and error code, with the
700 * original values stashed away in the PACA
702 storage_fault_common:
705 addi r3,r1,STACK_FRAME_OVERHEAD
708 ld r14,PACA_EXGEN+EX_R14(r13)
709 ld r15,PACA_EXGEN+EX_R15(r13)
713 b .ret_from_except_lite
716 addi r3,r1,STACK_FRAME_OVERHEAD
722 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
728 addi r3,r1,STACK_FRAME_OVERHEAD
729 ld r14,PACA_EXGEN+EX_R14(r13)
730 ld r15,PACA_EXGEN+EX_R15(r13)
733 bl .alignment_exception
737 * We branch here from entry_64.S for the last stage of the exception
738 * return code path. MSR:EE is expected to be off at that point
740 _GLOBAL(exception_return_book3e)
743 /* This is the return from load_up_fpu fast path which could do with
744 * less GPR restores in fact, but for now we have a single return path
746 .globl fast_exception_return
747 fast_exception_return:
755 ACCOUNT_CPU_USER_EXIT(r10, r11)
758 1: stdcx. r0,0,r1 /* to clear the reservation */
772 mtspr SPRN_SPRG_GEN_SCRATCH,r0
774 std r10,PACA_EXGEN+EX_R10(r13);
775 std r11,PACA_EXGEN+EX_R11(r13);
782 ld r10,PACA_EXGEN+EX_R10(r13)
783 ld r11,PACA_EXGEN+EX_R11(r13)
784 mfspr r13,SPRN_SPRG_GEN_SCRATCH
788 * Trampolines used when spotting a bad kernel stack pointer in
789 * the exception entry code.
791 * TODO: move some bits like SRR0 read to trampoline, pass PACA
792 * index around, etc... to handle crit & mcheck
794 BAD_STACK_TRAMPOLINE(0x000)
795 BAD_STACK_TRAMPOLINE(0x100)
796 BAD_STACK_TRAMPOLINE(0x200)
797 BAD_STACK_TRAMPOLINE(0x260)
798 BAD_STACK_TRAMPOLINE(0x280)
799 BAD_STACK_TRAMPOLINE(0x2a0)
800 BAD_STACK_TRAMPOLINE(0x2c0)
801 BAD_STACK_TRAMPOLINE(0x2e0)
802 BAD_STACK_TRAMPOLINE(0x300)
803 BAD_STACK_TRAMPOLINE(0x310)
804 BAD_STACK_TRAMPOLINE(0x320)
805 BAD_STACK_TRAMPOLINE(0x400)
806 BAD_STACK_TRAMPOLINE(0x500)
807 BAD_STACK_TRAMPOLINE(0x600)
808 BAD_STACK_TRAMPOLINE(0x700)
809 BAD_STACK_TRAMPOLINE(0x800)
810 BAD_STACK_TRAMPOLINE(0x900)
811 BAD_STACK_TRAMPOLINE(0x980)
812 BAD_STACK_TRAMPOLINE(0x9f0)
813 BAD_STACK_TRAMPOLINE(0xa00)
814 BAD_STACK_TRAMPOLINE(0xb00)
815 BAD_STACK_TRAMPOLINE(0xc00)
816 BAD_STACK_TRAMPOLINE(0xd00)
817 BAD_STACK_TRAMPOLINE(0xd08)
818 BAD_STACK_TRAMPOLINE(0xe00)
819 BAD_STACK_TRAMPOLINE(0xf00)
820 BAD_STACK_TRAMPOLINE(0xf20)
822 .globl bad_stack_book3e
824 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
825 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
826 ld r1,PACAEMERGSP(r13)
827 subi r1,r1,64+INT_FRAME_SIZE
830 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
831 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
838 std r0,GPR0(r1); /* save r0 in stackframe */ \
839 std r2,GPR2(r1); /* save r2 in stackframe */ \
840 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
841 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
842 std r9,GPR9(r1); /* save r9 in stackframe */ \
843 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
844 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
845 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
846 std r3,GPR10(r1); /* save r10 to stackframe */ \
847 std r4,GPR11(r1); /* save r11 to stackframe */ \
848 std r12,GPR12(r1); /* save r12 in stackframe */ \
849 std r5,GPR13(r1); /* save it to stackframe */ \
858 lhz r12,PACA_TRAP_SAVE(r13)
860 addi r11,r1,INT_FRAME_SIZE
865 1: addi r3,r1,STACK_FRAME_OVERHEAD
870 * Setup the initial TLB for a core. This current implementation
871 * assume that whatever we are running off will not conflict with
872 * the new mapping at PAGE_OFFSET.
874 _GLOBAL(initial_tlb_book3e)
876 /* Look for the first TLB with IPROT set */
877 mfspr r4,SPRN_TLB0CFG
878 andi. r3,r4,TLBnCFG_IPROT
879 lis r3,MAS0_TLBSEL(0)@h
882 mfspr r4,SPRN_TLB1CFG
883 andi. r3,r4,TLBnCFG_IPROT
884 lis r3,MAS0_TLBSEL(1)@h
887 mfspr r4,SPRN_TLB2CFG
888 andi. r3,r4,TLBnCFG_IPROT
889 lis r3,MAS0_TLBSEL(2)@h
892 lis r3,MAS0_TLBSEL(3)@h
893 mfspr r4,SPRN_TLB3CFG
897 andi. r5,r4,TLBnCFG_HES
900 mflr r8 /* save LR */
901 /* 1. Find the index of the entry we're executing in
903 * r3 = MAS0_TLBSEL (for the iprot array)
906 bl invstr /* Find our address */
907 invstr: mflr r6 /* Make it accessible */
909 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
914 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
917 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
919 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
920 oris r7,r7,MAS1_IPROT@h
924 /* 2. Invalidate all entries except the entry we're executing in
926 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
928 * r5 = ESEL of entry we are running in
930 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
931 li r6,0 /* Set Entry counter to 0 */
932 1: mr r7,r3 /* Set MAS0(TLBSEL) */
933 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
937 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
939 beq skpinv /* Dont update the current execution TLB */
943 skpinv: addi r6,r6,1 /* Increment */
944 cmpw r6,r4 /* Are we done? */
945 bne 1b /* If not, repeat */
947 /* Invalidate all TLBs */
952 /* 3. Setup a temp mapping and jump to it
954 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
955 * r5 = ESEL of entry we are running in
957 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
959 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
963 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
967 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
975 bl 1f /* Find our address */
982 /* 4. Clear out PIDs & Search info
984 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
985 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
992 /* 5. Invalidate mapping we started in
994 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
995 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1001 rlwinm r6,r6,0,2,0 /* clear IPROT */
1005 /* Invalidate TLB1 */
1006 PPC_TLBILX_ALL(0,R0)
1010 /* The mapping only needs to be cache-coherent on SMP */
1012 #define M_IF_SMP MAS2_M
1017 /* 6. Setup KERNELBASE mapping in TLB[0]
1019 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1020 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1023 rlwinm r3,r3,0,16,3 /* clear ESEL */
1025 lis r6,(MAS1_VALID|MAS1_IPROT)@h
1026 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1029 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
1033 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1040 /* 7. Jump to KERNELBASE mapping
1042 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1044 /* Now we branch the new virtual address mapped by this entry */
1045 LOAD_REG_IMMEDIATE(r6,2f)
1047 ori r7,r7,MSR_KERNEL@l
1050 rfi /* start execution out of TLB1[0] entry */
1053 /* 8. Clear out the temp mapping
1055 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1060 rlwinm r5,r5,0,2,0 /* clear IPROT */
1064 /* Invalidate TLB1 */
1065 PPC_TLBILX_ALL(0,R0)
1069 /* We translate LR and return */
1075 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1076 * kernel linear mapping. We also set MAS8 once for all here though
1077 * that will have to be made dependent on whether we are running under
1078 * a hypervisor I suppose.
1082 * This code is called as an ordinary function on the boot CPU. But to
1083 * avoid duplication, this code is also used in SCOM bringup of
1084 * secondary CPUs. We read the code between the initial_tlb_code_start
1085 * and initial_tlb_code_end labels one instruction at a time and RAM it
1086 * into the new core via SCOM. That doesn't process branches, so there
1087 * must be none between those two labels. It also means if this code
1088 * ever takes any parameters, the SCOM code must also be updated to
1091 .globl a2_tlbinit_code_start
1092 a2_tlbinit_code_start:
1094 ori r11,r3,MAS0_WQ_ALLWAYS
1095 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1097 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1098 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1100 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1102 li r3,MAS3_SR | MAS3_SW | MAS3_SX
1103 mtspr SPRN_MAS7_MAS3,r3
1107 /* Write the TLB entry */
1110 .globl a2_tlbinit_after_linear_map
1111 a2_tlbinit_after_linear_map:
1113 /* Now we branch the new virtual address mapped by this entry */
1114 LOAD_REG_IMMEDIATE(r3,1f)
1118 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1119 * else (including IPROTed things left by firmware)
1121 * r3 = current address (more or less)
1128 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1129 rlwinm r10,r4,8,0xff
1130 addi r10,r10,-1 /* Get inner loop mask */
1135 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1138 rldicr r6,r6,0,51 /* Extract EPN */
1141 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1143 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1148 rlwimi r7,r4,16,MAS0_ESEL_MASK
1159 addis r6,r6,(1<<30)@h
1164 .globl a2_tlbinit_after_iprot_flush
1165 a2_tlbinit_after_iprot_flush:
1167 #ifdef CONFIG_PPC_EARLY_DEBUG_WSP
1168 /* Now establish early debug mappings if applicable */
1169 /* Restore the MAS0 we used for linear mapping load */
1172 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1173 ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT)
1175 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G)
1177 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW)
1178 mtspr SPRN_MAS7_MAS3,r3
1179 /* re-use the MAS8 value from the linear mapping */
1181 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
1187 .globl a2_tlbinit_code_end
1188 a2_tlbinit_code_end:
1190 /* We translate LR and return */
1197 * Main entry (boot CPU, thread 0)
1199 * We enter here from head_64.S, possibly after the prom_init trampoline
1200 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1201 * mode. Anything else is as it was left by the bootloader
1203 * Initial requirements of this port:
1205 * - Kernel loaded at 0 physical
1206 * - A good lump of memory mapped 0:0 by UTLB entry 0
1207 * - MSR:IS & MSR:DS set to 0
1209 * Note that some of the above requirements will be relaxed in the future
1210 * as the kernel becomes smarter at dealing with different initial conditions
1211 * but for now you have to be careful
1213 _GLOBAL(start_initialization_book3e)
1216 /* First, we need to setup some initial TLBs to map the kernel
1217 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1218 * and always use AS 0, so we just set it up to match our link
1219 * address and never use 0 based addresses.
1221 bl .initial_tlb_book3e
1223 /* Init global core bits */
1224 bl .init_core_book3e
1226 /* Init per-thread bits */
1227 bl .init_thread_book3e
1229 /* Return to common init code */
1236 * Secondary core/processor entry
1238 * This is entered for thread 0 of a secondary core, all other threads
1239 * are expected to be stopped. It's similar to start_initialization_book3e
1240 * except that it's generally entered from the holding loop in head_64.S
1241 * after CPUs have been gathered by Open Firmware.
1243 * We assume we are in 32 bits mode running with whatever TLB entry was
1244 * set for us by the firmware or POR engine.
1246 _GLOBAL(book3e_secondary_core_init_tlb_set)
1248 b .generic_secondary_smp_init
1250 _GLOBAL(book3e_secondary_core_init)
1253 /* Do we need to setup initial TLB entry ? */
1257 /* Setup TLB for this core */
1258 bl .initial_tlb_book3e
1260 /* We can return from the above running at a different
1261 * address, so recalculate r2 (TOC)
1265 /* Init global core bits */
1266 2: bl .init_core_book3e
1268 /* Init per-thread bits */
1269 3: bl .init_thread_book3e
1271 /* Return to common init code at proper virtual address.
1273 * Due to various previous assumptions, we know we entered this
1274 * function at either the final PAGE_OFFSET mapping or using a
1275 * 1:1 mapping at 0, so we don't bother doing a complicated check
1276 * here, we just ensure the return address has the right top bits.
1278 * Note that if we ever want to be smarter about where we can be
1279 * started from, we have to be careful that by the time we reach
1280 * the code below we may already be running at a different location
1281 * than the one we were called from since initial_tlb_book3e can
1282 * have moved us already.
1286 lis r3,PAGE_OFFSET@highest
1292 _GLOBAL(book3e_secondary_thread_init)
1296 _STATIC(init_core_book3e)
1297 /* Establish the interrupt vector base */
1298 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
1303 _STATIC(init_thread_book3e)
1304 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1307 /* Make sure interrupts are off */
1310 /* disable all timers and clear out status */
1318 _GLOBAL(__setup_base_ivors)
1319 SET_IVOR(0, 0x020) /* Critical Input */
1320 SET_IVOR(1, 0x000) /* Machine Check */
1321 SET_IVOR(2, 0x060) /* Data Storage */
1322 SET_IVOR(3, 0x080) /* Instruction Storage */
1323 SET_IVOR(4, 0x0a0) /* External Input */
1324 SET_IVOR(5, 0x0c0) /* Alignment */
1325 SET_IVOR(6, 0x0e0) /* Program */
1326 SET_IVOR(7, 0x100) /* FP Unavailable */
1327 SET_IVOR(8, 0x120) /* System Call */
1328 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1329 SET_IVOR(10, 0x160) /* Decrementer */
1330 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1331 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1332 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1333 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1334 SET_IVOR(15, 0x040) /* Debug */
1340 _GLOBAL(setup_perfmon_ivor)
1341 SET_IVOR(35, 0x260) /* Performance Monitor */
1344 _GLOBAL(setup_doorbell_ivors)
1345 SET_IVOR(36, 0x280) /* Processor Doorbell */
1346 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1348 /* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
1349 mfspr r10,SPRN_MMUCFG
1350 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1353 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1354 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1357 _GLOBAL(setup_ehv_ivors)
1359 * We may be running as a guest and lack E.HV even on a chip
1360 * that normally has it.
1362 mfspr r10,SPRN_MMUCFG
1363 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1366 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1367 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */