2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 * PPC44x port. Copyright (C) 2011, IBM Corporation
12 * Author: Suzuki Poulose <suzuki@in.ibm.com>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
21 #include <linux/sys.h>
22 #include <asm/unistd.h>
23 #include <asm/errno.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/processor.h>
33 #include <asm/kexec.h>
35 #include <asm/ptrace.h>
39 _GLOBAL(call_do_softirq)
42 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
50 _GLOBAL(call_handle_irq)
54 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
63 * This returns the high 64 bits of the product of two 64-bit numbers.
75 1: beqlr cr1 /* all done if high part of A is 0 */
90 * sub_reloc_offset(x) returns x - reloc_offset().
92 _GLOBAL(sub_reloc_offset)
104 * reloc_got2 runs through the .got2 section adding an offset
109 lis r7,__got2_start@ha
110 addi r7,r7,__got2_start@l
112 addi r8,r8,__got2_end@l
132 * call_setup_cpu - call the setup_cpu function for this cpu
133 * r3 = data offset, r24 = cpu number
135 * Setup function is called with:
137 * r4 = ptr to CPU spec (relocated)
139 _GLOBAL(call_setup_cpu)
140 addis r4,r3,cur_cpu_spec@ha
141 addi r4,r4,cur_cpu_spec@l
144 lwz r5,CPU_SPEC_SETUP(r4)
151 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
153 /* This gets called by via-pmu.c to switch the PLL selection
154 * on 750fx CPU. This function should really be moved to some
155 * other place (as most of the cpufreq code in via-pmu
157 _GLOBAL(low_choose_750fx_pll)
163 /* If switching to PLL1, disable HID0:BTIC */
174 /* Calc new HID1 value */
175 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
176 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
177 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
181 /* Store new HID1 image */
182 CURRENT_THREAD_INFO(r6, r1)
185 addis r6,r6,nap_save_hid1@ha
186 stw r4,nap_save_hid1@l(r6)
188 /* If switching to PLL0, enable HID0:BTIC */
203 _GLOBAL(low_choose_7447a_dfs)
209 /* Calc new HID1 value */
211 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
221 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
224 * complement mask on the msr then "or" some values on.
225 * _nmask_and_or_msr(nmask, value_to_or)
227 _GLOBAL(_nmask_and_or_msr)
228 mfmsr r0 /* Get current msr */
229 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
230 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
231 SYNC /* Some chip revs have problems here... */
232 mtmsr r0 /* Update machine state */
239 * Do an IO access in real mode
257 * Do an IO access in real mode
274 #endif /* CONFIG_40x */
278 * Flush instruction cache.
279 * This is a no-op on the 601.
281 _GLOBAL(flush_instruction_cache)
282 #if defined(CONFIG_8xx)
285 mtspr SPRN_IC_CST, r5
286 #elif defined(CONFIG_4xx)
298 #elif CONFIG_FSL_BOOKE
301 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
302 /* msync; isync recommended here */
306 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
308 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
312 rlwinm r3,r3,16,16,31
314 beqlr /* for 601, do nothing */
315 /* 603/604 processor - use invalidate-all bit in HID0 */
319 #endif /* CONFIG_8xx/4xx */
324 * Write any modified data cache blocks out to memory
325 * and invalidate the corresponding instruction cache blocks.
326 * This is a no-op on the 601.
328 * flush_icache_range(unsigned long start, unsigned long stop)
330 _KPROBE(__flush_icache_range)
332 blr /* for 601, do nothing */
333 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
334 li r5,L1_CACHE_BYTES-1
338 srwi. r4,r4,L1_CACHE_SHIFT
343 addi r3,r3,L1_CACHE_BYTES
345 sync /* wait for dcbst's to get to ram */
349 addi r6,r6,L1_CACHE_BYTES
352 /* Flash invalidate on 44x because we are passed kmapped addresses and
353 this doesn't work for userspace pages due to the virtually tagged
357 sync /* additional sync needed on g4 */
361 * Write any modified data cache blocks out to memory.
362 * Does not invalidate the corresponding cache lines (especially for
363 * any corresponding instruction cache).
365 * clean_dcache_range(unsigned long start, unsigned long stop)
367 _GLOBAL(clean_dcache_range)
368 li r5,L1_CACHE_BYTES-1
372 srwi. r4,r4,L1_CACHE_SHIFT
377 addi r3,r3,L1_CACHE_BYTES
379 sync /* wait for dcbst's to get to ram */
383 * Write any modified data cache blocks out to memory and invalidate them.
384 * Does not invalidate the corresponding instruction cache blocks.
386 * flush_dcache_range(unsigned long start, unsigned long stop)
388 _GLOBAL(flush_dcache_range)
389 li r5,L1_CACHE_BYTES-1
393 srwi. r4,r4,L1_CACHE_SHIFT
398 addi r3,r3,L1_CACHE_BYTES
400 sync /* wait for dcbst's to get to ram */
404 * Like above, but invalidate the D-cache. This is used by the 8xx
405 * to invalidate the cache so the PPC core doesn't get stale data
406 * from the CPM (no cache snooping here :-).
408 * invalidate_dcache_range(unsigned long start, unsigned long stop)
410 _GLOBAL(invalidate_dcache_range)
411 li r5,L1_CACHE_BYTES-1
415 srwi. r4,r4,L1_CACHE_SHIFT
420 addi r3,r3,L1_CACHE_BYTES
422 sync /* wait for dcbi's to get to ram */
426 * Flush a particular page from the data cache to RAM.
427 * Note: this is necessary because the instruction cache does *not*
428 * snoop from the data cache.
429 * This is a no-op on the 601 which has a unified cache.
431 * void __flush_dcache_icache(void *page)
433 _GLOBAL(__flush_dcache_icache)
436 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
437 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
438 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
441 0: dcbst 0,r3 /* Write line to ram */
442 addi r3,r3,L1_CACHE_BYTES
446 /* We don't flush the icache on 44x. Those have a virtual icache
447 * and we don't have access to the virtual address here (it's
448 * not the page vaddr but where it's mapped in user space). The
449 * flushing of the icache on these is handled elsewhere, when
450 * a change in the address space occurs, before returning to
453 BEGIN_MMU_FTR_SECTION
455 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
456 #endif /* CONFIG_44x */
459 addi r6,r6,L1_CACHE_BYTES
467 * Flush a particular page from the data cache to RAM, identified
468 * by its physical address. We turn off the MMU so we can just use
469 * the physical address (this may be a highmem page without a kernel
472 * void __flush_dcache_icache_phys(unsigned long physaddr)
474 _GLOBAL(__flush_dcache_icache_phys)
476 blr /* for 601, do nothing */
477 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
479 rlwinm r0,r10,0,28,26 /* clear DR */
482 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
483 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
486 0: dcbst 0,r3 /* Write line to ram */
487 addi r3,r3,L1_CACHE_BYTES
492 addi r6,r6,L1_CACHE_BYTES
495 mtmsr r10 /* restore DR */
498 #endif /* CONFIG_BOOKE */
501 * Clear pages using the dcbz instruction, which doesn't cause any
502 * memory traffic (except to write out any cache lines which get
503 * displaced). This only works on cacheable memory.
505 * void clear_pages(void *page, int order) ;
508 li r0,PAGE_SIZE/L1_CACHE_BYTES
512 addi r3,r3,L1_CACHE_BYTES
517 * Copy a whole page. We use the dcbz instruction on the destination
518 * to reduce memory traffic (it eliminates the unnecessary reads of
519 * the destination into cache). This requires that the destination
522 #define COPY_16_BYTES \
538 #if MAX_COPY_PREFETCH > 1
539 li r0,MAX_COPY_PREFETCH
543 addi r11,r11,L1_CACHE_BYTES
545 #else /* MAX_COPY_PREFETCH == 1 */
547 li r11,L1_CACHE_BYTES+4
548 #endif /* MAX_COPY_PREFETCH */
549 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
557 #if L1_CACHE_BYTES >= 32
559 #if L1_CACHE_BYTES >= 64
562 #if L1_CACHE_BYTES >= 128
572 crnot 4*cr0+eq,4*cr0+eq
573 li r0,MAX_COPY_PREFETCH
578 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
579 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
581 _GLOBAL(atomic_clear_mask)
588 _GLOBAL(atomic_set_mask)
597 * Extended precision shifts.
599 * Updated to be valid for shift counts from 0 to 63 inclusive.
602 * R3/R4 has 64 bit value
606 * ashrdi3: arithmetic right shift (sign propagation)
607 * lshrdi3: logical right shift
608 * ashldi3: left shift
612 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
613 addi r7,r5,32 # could be xori, or addi with -32
614 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
615 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
616 sraw r7,r3,r7 # t2 = MSW >> (count-32)
617 or r4,r4,r6 # LSW |= t1
618 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
619 sraw r3,r3,r5 # MSW = MSW >> count
620 or r4,r4,r7 # LSW |= t2
625 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
626 addi r7,r5,32 # could be xori, or addi with -32
627 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
628 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
629 or r3,r3,r6 # MSW |= t1
630 slw r4,r4,r5 # LSW = LSW << count
631 or r3,r3,r7 # MSW |= t2
636 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
637 addi r7,r5,32 # could be xori, or addi with -32
638 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
639 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
640 or r4,r4,r6 # LSW |= t1
641 srw r3,r3,r5 # MSW = MSW >> count
642 or r4,r4,r7 # LSW |= t2
646 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
647 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
665 rlwimi r9,r4,24,16,23
666 rlwimi r10,r3,24,16,23
678 _GLOBAL(start_secondary_resume)
680 CURRENT_THREAD_INFO(r1, r1)
681 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
683 stw r3,0(r1) /* Zero the stack frame pointer */
686 #endif /* CONFIG_SMP */
689 * This routine is just here to keep GCC happy - sigh...
696 * Must be relocatable PIC code callable as a C function.
698 .globl relocate_new_kernel
701 /* r4 = reboot_code_buffer */
702 /* r5 = start_address */
704 #ifdef CONFIG_FSL_BOOKE
710 #define ENTRY_MAPPING_KEXEC_SETUP
711 #include "fsl_booke_entry_mapping.S"
712 #undef ENTRY_MAPPING_KEXEC_SETUP
719 #elif defined(CONFIG_44x)
721 /* Save our parameters */
726 #ifdef CONFIG_PPC_47x
727 /* Check for 47x cores */
730 cmplwi cr0,r3,PVR_476@h
732 cmplwi cr0,r3,PVR_476_ISS@h
734 #endif /* CONFIG_PPC_47x */
737 * Code for setting up 1:1 mapping for PPC440x for KEXEC
739 * We cannot switch off the MMU on PPC44x.
741 * 1) Invalidate all the mappings except the one we are running from.
742 * 2) Create a tmp mapping for our code in the other address space(TS) and
743 * jump to it. Invalidate the entry we started in.
744 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
745 * 4) Jump to the 1:1 mapping in original TS.
746 * 5) Invalidate the tmp mapping.
748 * - Based on the kexec support code for FSL BookE
753 * Load the PID with kernel PID (0).
754 * Also load our MSR_IS and TID to MMUCR for TLB search.
761 oris r3,r3,PPC44x_MMUCR_STS@h
767 * Invalidate all the TLB entries except the current entry
768 * where we are running from
770 bl 0f /* Find our address */
771 0: mflr r5 /* Make it accessible */
772 tlbsx r23,0,r5 /* Find entry we are in */
773 li r4,0 /* Start at TLB entry 0 */
774 li r3,0 /* Set PAGEID inval value */
775 1: cmpw r23,r4 /* Is this our entry? */
776 beq skip /* If so, skip the inval */
777 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
779 addi r4,r4,1 /* Increment */
780 cmpwi r4,64 /* Are we done? */
781 bne 1b /* If not, repeat */
784 /* Create a temp mapping and jump to it */
785 andi. r6, r23, 1 /* Find the index to use */
786 addi r24, r6, 1 /* r24 will contain 1 or 2 */
788 mfmsr r9 /* get the MSR */
789 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
790 xori r7, r5, 1 /* Use the other address space */
792 /* Read the current mapping entries */
793 tlbre r3, r23, PPC44x_TLB_PAGEID
794 tlbre r4, r23, PPC44x_TLB_XLAT
795 tlbre r5, r23, PPC44x_TLB_ATTRIB
797 /* Save our current XLAT entry */
800 /* Extract the TLB PageSize */
801 li r10, 1 /* r10 will hold PageSize */
802 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
804 /* XXX: As of now we use 256M, 4K pages */
805 cmpwi r11, PPC44x_TLB_256M
807 rotlwi r10, r10, 28 /* r10 = 256M */
810 cmpwi r11, PPC44x_TLB_4K
812 rotlwi r10, r10, 12 /* r10 = 4K */
815 rotlwi r10, r10, 10 /* r10 = 1K */
819 * Write out the tmp 1:1 mapping for this code in other address space
820 * Fixup EPN = RPN , TS=other address space
822 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
824 /* Write out the tmp mapping entries */
825 tlbwe r3, r24, PPC44x_TLB_PAGEID
826 tlbwe r4, r24, PPC44x_TLB_XLAT
827 tlbwe r5, r24, PPC44x_TLB_ATTRIB
829 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
830 not r10, r11 /* Mask for PageNum */
832 /* Switch to other address space in MSR */
833 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
837 addi r8, r8, (2f-1b) /* Find the target offset */
839 /* Jump to the tmp mapping */
845 /* Invalidate the entry we were executing from */
847 tlbwe r3, r23, PPC44x_TLB_PAGEID
849 /* attribute fields. rwx for SUPERVISOR mode */
851 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
853 /* Create 1:1 mapping in 256M pages */
854 xori r7, r7, 1 /* Revert back to Original TS */
856 li r8, 0 /* PageNumber */
857 li r6, 3 /* TLB Index, start at 3 */
860 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
861 mr r4, r3 /* RPN = EPN */
862 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
863 insrwi r3, r7, 1, 23 /* Set TS from r7 */
865 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
866 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
867 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
869 addi r8, r8, 1 /* Increment PN */
870 addi r6, r6, 1 /* Increment TLB Index */
871 cmpwi r8, 8 /* Are we done ? */
875 /* Jump to the new mapping 1:1 */
877 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
881 and r8, r8, r11 /* Get our offset within page */
884 and r5, r25, r10 /* Get our target PageNum */
885 or r8, r8, r5 /* Target jump address */
891 /* Invalidate the tmp entry we used */
893 tlbwe r3, r24, PPC44x_TLB_PAGEID
897 #ifdef CONFIG_PPC_47x
899 /* 1:1 mapping for 47x */
904 * Load the kernel pid (0) to PID and also to MMUCR[TID].
905 * Also set the MSR IS->MMUCR STS
908 mtspr SPRN_PID, r3 /* Set PID */
909 mfmsr r4 /* Get MSR */
910 andi. r4, r4, MSR_IS@l /* TS=1? */
911 beq 1f /* If not, leave STS=0 */
912 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
913 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
916 /* Find the entry we are running from */
920 tlbre r24, r23, 0 /* TLB Word 0 */
921 tlbre r25, r23, 1 /* TLB Word 1 */
922 tlbre r26, r23, 2 /* TLB Word 2 */
926 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
927 * of 4k page size in all 4 ways (0-3 in r3).
928 * This would invalidate the entire UTLB including the one we are
929 * running from. However the shadow TLB entries would help us
930 * to continue the execution, until we flush them (rfi/isync).
932 addis r3, 0, 0x8000 /* specify the way */
933 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
937 /* Align the loop to speed things up. from head_44x.S */
945 addis r3, r3, 0x2000 /* Increment the way */
949 addis r4, r4, 0x100 /* Increment the EPN */
953 /* Create the entries in the other address space */
955 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
956 xori r7, r7, 1 /* r7 = !TS */
958 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
961 * write out the TLB entries for the tmp mapping
962 * Use way '0' so that we could easily invalidate it later.
964 lis r3, 0x8000 /* Way '0' */
970 /* Update the msr to the new TS */
982 * Now we are in the tmp address space.
983 * Create a 1:1 mapping for 0-2GiB in the original TS.
987 li r4, 0 /* TLB Word 0 */
988 li r5, 0 /* TLB Word 1 */
990 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
992 li r8, 0 /* PageIndex */
994 xori r7, r7, 1 /* revert back to original TS */
997 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
998 /* ERPN = 0 as we don't use memory above 2G */
1000 mr r4, r5 /* EPN = RPN */
1001 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
1002 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
1004 tlbwe r4, r3, 0 /* Write out the entries */
1008 cmpwi r8, 8 /* Have we completed ? */
1011 /* make sure we complete the TLB write up */
1015 * Prepare to jump to the 1:1 mapping.
1016 * 1) Extract page size of the tmp mapping
1017 * DSIZ = TLB_Word0[22:27]
1018 * 2) Calculate the physical address of the address
1021 rlwinm r10, r24, 0, 22, 27
1023 cmpwi r10, PPC47x_TLB0_4K
1025 li r10, 0x1000 /* r10 = 4k */
1029 /* Defaults to 256M */
1034 addi r4, r4, (2f-1b) /* virtual address of 2f */
1036 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
1037 not r10, r11 /* Pagemask = ~(offsetmask) */
1039 and r5, r25, r10 /* Physical page */
1040 and r6, r4, r11 /* offset within the current page */
1042 or r5, r5, r6 /* Physical address for 2f */
1044 /* Switch the TS in MSR to the original one */
1046 insrwi r8, r7, 1, 26
1053 /* Invalidate the tmp mapping */
1054 lis r3, 0x8000 /* Way '0' */
1056 clrrwi r24, r24, 12 /* Clear the valid bit */
1061 /* Make sure we complete the TLB write and flush the shadow TLB */
1069 /* Restore the parameters */
1079 * Set Machine Status Register to a known status,
1080 * switch the MMU off and jump to 1: in a single step.
1084 ori r8, r8, MSR_RI|MSR_ME
1086 addi r8, r4, 1f - relocate_new_kernel
1093 /* from this point address translation is turned off */
1094 /* and interrupts are disabled */
1096 /* set a new stack at the bottom of our page... */
1097 /* (not really needed now) */
1098 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1102 li r6, 0 /* checksum */
1106 0: /* top, read another word for the indirection page */
1110 /* is it a destination page? (r8) */
1111 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
1114 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
1117 2: /* is it an indirection page? (r3) */
1118 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
1121 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1125 2: /* are we done? */
1126 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
1130 2: /* is it a source page? (r9) */
1131 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
1134 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1136 li r7, PAGE_SIZE / 4
1141 lwzu r0, 4(r9) /* do the copy */
1155 /* To be certain of avoiding problems with self-modifying code
1156 * execute a serializing instruction here.
1161 mfspr r3, SPRN_PIR /* current core we are running on */
1162 mr r4, r5 /* load physical address of chunk called */
1164 /* jump to the entry point, usually the setup routine */
1170 relocate_new_kernel_end:
1172 .globl relocate_new_kernel_size
1173 relocate_new_kernel_size:
1174 .long relocate_new_kernel_end - relocate_new_kernel