2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
44 static DEFINE_SPINLOCK(hose_spinlock);
47 /* XXX kill that some day ... */
48 static int global_phb_number; /* Global phb counter */
50 /* ISA Memory physical address */
51 resource_size_t isa_mem_base;
54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = slab_is_available();
82 int nid = of_node_to_nid(dev);
84 if (nid < 0 || !node_online(nid))
87 PHB_SET_NODE(phb, nid);
93 void pcibios_free_controller(struct pci_controller *phb)
95 spin_lock(&hose_spinlock);
96 list_del(&phb->list_node);
97 spin_unlock(&hose_spinlock);
104 * The function is used to return the minimal alignment
105 * for memory or I/O windows of the associated P2P bridge.
106 * By default, 4KiB alignment for I/O windows and 1MiB for
109 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
112 return pci_window_alignment(bus, type);
115 void pcibios_reset_secondary_bus(struct pci_dev *dev)
117 if (ppc_md.pcibios_reset_secondary_bus) {
118 ppc_md.pcibios_reset_secondary_bus(dev);
122 pci_reset_secondary_bus(dev);
125 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
128 return hose->pci_io_size;
130 return resource_size(&hose->io_resource);
134 int pcibios_vaddr_is_ioport(void __iomem *address)
137 struct pci_controller *hose;
138 resource_size_t size;
140 spin_lock(&hose_spinlock);
141 list_for_each_entry(hose, &hose_list, list_node) {
142 size = pcibios_io_size(hose);
143 if (address >= hose->io_base_virt &&
144 address < (hose->io_base_virt + size)) {
149 spin_unlock(&hose_spinlock);
153 unsigned long pci_address_to_pio(phys_addr_t address)
155 struct pci_controller *hose;
156 resource_size_t size;
157 unsigned long ret = ~0;
159 spin_lock(&hose_spinlock);
160 list_for_each_entry(hose, &hose_list, list_node) {
161 size = pcibios_io_size(hose);
162 if (address >= hose->io_base_phys &&
163 address < (hose->io_base_phys + size)) {
165 (unsigned long)hose->io_base_virt - _IO_BASE;
166 ret = base + (address - hose->io_base_phys);
170 spin_unlock(&hose_spinlock);
174 EXPORT_SYMBOL_GPL(pci_address_to_pio);
177 * Return the domain number for this bus.
179 int pci_domain_nr(struct pci_bus *bus)
181 struct pci_controller *hose = pci_bus_to_host(bus);
183 return hose->global_number;
185 EXPORT_SYMBOL(pci_domain_nr);
187 /* This routine is meant to be used early during boot, when the
188 * PCI bus numbers have not yet been assigned, and you need to
189 * issue PCI config cycles to an OF device.
190 * It could also be used to "fix" RTAS config cycles if you want
191 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
194 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
197 struct pci_controller *hose, *tmp;
198 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
199 if (hose->dn == node)
207 * Reads the interrupt pin to determine if interrupt is use by card.
208 * If the interrupt is used, then gets the interrupt line from the
209 * openfirmware and sets it in the pci_dev and pci_config line.
211 static int pci_read_irq_line(struct pci_dev *pci_dev)
213 struct of_phandle_args oirq;
216 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
219 memset(&oirq, 0xff, sizeof(oirq));
221 /* Try to get a mapping from the device-tree */
222 if (of_irq_parse_pci(pci_dev, &oirq)) {
225 /* If that fails, lets fallback to what is in the config
226 * space and map that through the default controller. We
227 * also set the type to level low since that's what PCI
228 * interrupts are. If your platform does differently, then
229 * either provide a proper interrupt tree or don't use this
232 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
236 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
237 line == 0xff || line == 0) {
240 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
243 virq = irq_create_mapping(NULL, line);
245 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
247 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
248 oirq.args_count, oirq.args[0], oirq.args[1],
249 of_node_full_name(oirq.np));
251 virq = irq_create_of_mapping(&oirq);
254 pr_debug(" Failed to map !\n");
258 pr_debug(" Mapped to linux irq %d\n", virq);
266 * Platform support for /proc/bus/pci/X/Y mmap()s,
267 * modelled on the sparc64 implementation by Dave Miller.
272 * Adjust vm_pgoff of VMA such that it is the physical page offset
273 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
275 * Basically, the user finds the base address for his device which he wishes
276 * to mmap. They read the 32-bit value from the config space base register,
277 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
278 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
280 * Returns negative error code on failure, zero on success.
282 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
283 resource_size_t *offset,
284 enum pci_mmap_state mmap_state)
286 struct pci_controller *hose = pci_bus_to_host(dev->bus);
287 unsigned long io_offset = 0;
291 return NULL; /* should never happen */
293 /* If memory, add on the PCI bridge address offset */
294 if (mmap_state == pci_mmap_mem) {
295 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
296 *offset += hose->pci_mem_offset;
298 res_bit = IORESOURCE_MEM;
300 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
301 *offset += io_offset;
302 res_bit = IORESOURCE_IO;
306 * Check that the offset requested corresponds to one of the
307 * resources of the device.
309 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
310 struct resource *rp = &dev->resource[i];
311 int flags = rp->flags;
313 /* treat ROM as memory (should be already) */
314 if (i == PCI_ROM_RESOURCE)
315 flags |= IORESOURCE_MEM;
317 /* Active and same type? */
318 if ((flags & res_bit) == 0)
321 /* In the range of this resource? */
322 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
325 /* found it! construct the final physical address */
326 if (mmap_state == pci_mmap_io)
327 *offset += hose->io_base_phys - io_offset;
335 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
338 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
340 enum pci_mmap_state mmap_state,
344 /* Write combine is always 0 on non-memory space mappings. On
345 * memory space, if the user didn't pass 1, we check for a
346 * "prefetchable" resource. This is a bit hackish, but we use
347 * this to workaround the inability of /sysfs to provide a write
350 if (mmap_state != pci_mmap_mem)
352 else if (write_combine == 0) {
353 if (rp->flags & IORESOURCE_PREFETCH)
357 /* XXX would be nice to have a way to ask for write-through */
359 return pgprot_noncached_wc(protection);
361 return pgprot_noncached(protection);
365 * This one is used by /dev/mem and fbdev who have no clue about the
366 * PCI device, it tries to find the PCI device first and calls the
369 pgprot_t pci_phys_mem_access_prot(struct file *file,
374 struct pci_dev *pdev = NULL;
375 struct resource *found = NULL;
376 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
379 if (page_is_ram(pfn))
382 prot = pgprot_noncached(prot);
383 for_each_pci_dev(pdev) {
384 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
385 struct resource *rp = &pdev->resource[i];
386 int flags = rp->flags;
388 /* Active and same type? */
389 if ((flags & IORESOURCE_MEM) == 0)
391 /* In the range of this resource? */
392 if (offset < (rp->start & PAGE_MASK) ||
402 if (found->flags & IORESOURCE_PREFETCH)
403 prot = pgprot_noncached_wc(prot);
407 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
408 (unsigned long long)offset, pgprot_val(prot));
415 * Perform the actual remap of the pages for a PCI device mapping, as
416 * appropriate for this architecture. The region in the process to map
417 * is described by vm_start and vm_end members of VMA, the base physical
418 * address is found in vm_pgoff.
419 * The pci device structure is provided so that architectures may make mapping
420 * decisions on a per-device or per-bus basis.
422 * Returns a negative error code on failure, zero on success.
424 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
425 enum pci_mmap_state mmap_state, int write_combine)
427 resource_size_t offset =
428 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
432 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
436 vma->vm_pgoff = offset >> PAGE_SHIFT;
437 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
439 mmap_state, write_combine);
441 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
442 vma->vm_end - vma->vm_start, vma->vm_page_prot);
447 /* This provides legacy IO read access on a bus */
448 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
450 unsigned long offset;
451 struct pci_controller *hose = pci_bus_to_host(bus);
452 struct resource *rp = &hose->io_resource;
455 /* Check if port can be supported by that bus. We only check
456 * the ranges of the PHB though, not the bus itself as the rules
457 * for forwarding legacy cycles down bridges are not our problem
458 * here. So if the host bridge supports it, we do it.
460 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
463 if (!(rp->flags & IORESOURCE_IO))
465 if (offset < rp->start || (offset + size) > rp->end)
467 addr = hose->io_base_virt + port;
471 *((u8 *)val) = in_8(addr);
476 *((u16 *)val) = in_le16(addr);
481 *((u32 *)val) = in_le32(addr);
487 /* This provides legacy IO write access on a bus */
488 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
490 unsigned long offset;
491 struct pci_controller *hose = pci_bus_to_host(bus);
492 struct resource *rp = &hose->io_resource;
495 /* Check if port can be supported by that bus. We only check
496 * the ranges of the PHB though, not the bus itself as the rules
497 * for forwarding legacy cycles down bridges are not our problem
498 * here. So if the host bridge supports it, we do it.
500 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
503 if (!(rp->flags & IORESOURCE_IO))
505 if (offset < rp->start || (offset + size) > rp->end)
507 addr = hose->io_base_virt + port;
509 /* WARNING: The generic code is idiotic. It gets passed a pointer
510 * to what can be a 1, 2 or 4 byte quantity and always reads that
511 * as a u32, which means that we have to correct the location of
512 * the data read within those 32 bits for size 1 and 2
516 out_8(addr, val >> 24);
521 out_le16(addr, val >> 16);
532 /* This provides legacy IO or memory mmap access on a bus */
533 int pci_mmap_legacy_page_range(struct pci_bus *bus,
534 struct vm_area_struct *vma,
535 enum pci_mmap_state mmap_state)
537 struct pci_controller *hose = pci_bus_to_host(bus);
538 resource_size_t offset =
539 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
540 resource_size_t size = vma->vm_end - vma->vm_start;
543 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
544 pci_domain_nr(bus), bus->number,
545 mmap_state == pci_mmap_mem ? "MEM" : "IO",
546 (unsigned long long)offset,
547 (unsigned long long)(offset + size - 1));
549 if (mmap_state == pci_mmap_mem) {
552 * Because X is lame and can fail starting if it gets an error trying
553 * to mmap legacy_mem (instead of just moving on without legacy memory
554 * access) we fake it here by giving it anonymous memory, effectively
555 * behaving just like /dev/zero
557 if ((offset + size) > hose->isa_mem_size) {
559 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
560 current->comm, current->pid, pci_domain_nr(bus), bus->number);
561 if (vma->vm_flags & VM_SHARED)
562 return shmem_zero_setup(vma);
565 offset += hose->isa_mem_phys;
567 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
568 unsigned long roffset = offset + io_offset;
569 rp = &hose->io_resource;
570 if (!(rp->flags & IORESOURCE_IO))
572 if (roffset < rp->start || (roffset + size) > rp->end)
574 offset += hose->io_base_phys;
576 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
578 vma->vm_pgoff = offset >> PAGE_SHIFT;
579 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
580 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
581 vma->vm_end - vma->vm_start,
585 void pci_resource_to_user(const struct pci_dev *dev, int bar,
586 const struct resource *rsrc,
587 resource_size_t *start, resource_size_t *end)
589 struct pci_controller *hose = pci_bus_to_host(dev->bus);
590 resource_size_t offset = 0;
595 if (rsrc->flags & IORESOURCE_IO)
596 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
598 /* We pass a fully fixed up address to userland for MMIO instead of
599 * a BAR value because X is lame and expects to be able to use that
600 * to pass to /dev/mem !
602 * That means that we'll have potentially 64 bits values where some
603 * userland apps only expect 32 (like X itself since it thinks only
604 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
607 * Hopefully, the sysfs insterface is immune to that gunk. Once X
608 * has been fixed (and the fix spread enough), we can re-enable the
609 * 2 lines below and pass down a BAR value to userland. In that case
610 * we'll also have to re-enable the matching code in
611 * __pci_mmap_make_offset().
616 else if (rsrc->flags & IORESOURCE_MEM)
617 offset = hose->pci_mem_offset;
620 *start = rsrc->start - offset;
621 *end = rsrc->end - offset;
625 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
626 * @hose: newly allocated pci_controller to be setup
627 * @dev: device node of the host bridge
628 * @primary: set if primary bus (32 bits only, soon to be deprecated)
630 * This function will parse the "ranges" property of a PCI host bridge device
631 * node and setup the resource mapping of a pci controller based on its
634 * Life would be boring if it wasn't for a few issues that we have to deal
637 * - We can only cope with one IO space range and up to 3 Memory space
638 * ranges. However, some machines (thanks Apple !) tend to split their
639 * space into lots of small contiguous ranges. So we have to coalesce.
641 * - Some busses have IO space not starting at 0, which causes trouble with
642 * the way we do our IO resource renumbering. The code somewhat deals with
643 * it for 64 bits but I would expect problems on 32 bits.
645 * - Some 32 bits platforms such as 4xx can have physical space larger than
646 * 32 bits so we need to use 64 bits values for the parsing
648 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
649 struct device_node *dev, int primary)
652 struct resource *res;
653 struct of_pci_range range;
654 struct of_pci_range_parser parser;
656 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
657 dev->full_name, primary ? "(primary)" : "");
659 /* Check for ranges property */
660 if (of_pci_range_parser_init(&parser, dev))
664 for_each_of_pci_range(&parser, &range) {
665 /* If we failed translation or got a zero-sized region
666 * (some FW try to feed us with non sensical zero sized regions
667 * such as power3 which look like some kind of attempt at exposing
668 * the VGA memory hole)
670 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
673 /* Act based on address space type */
675 switch (range.flags & IORESOURCE_TYPE_BITS) {
678 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
679 range.cpu_addr, range.cpu_addr + range.size - 1,
682 /* We support only one IO range */
683 if (hose->pci_io_size) {
685 " \\--> Skipped (too many) !\n");
689 /* On 32 bits, limit I/O space to 16MB */
690 if (range.size > 0x01000000)
691 range.size = 0x01000000;
693 /* 32 bits needs to map IOs here */
694 hose->io_base_virt = ioremap(range.cpu_addr,
697 /* Expect trouble if pci_addr is not 0 */
700 (unsigned long)hose->io_base_virt;
701 #endif /* CONFIG_PPC32 */
702 /* pci_io_size and io_base_phys always represent IO
703 * space starting at 0 so we factor in pci_addr
705 hose->pci_io_size = range.pci_addr + range.size;
706 hose->io_base_phys = range.cpu_addr - range.pci_addr;
709 res = &hose->io_resource;
710 range.cpu_addr = range.pci_addr;
714 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
715 range.cpu_addr, range.cpu_addr + range.size - 1,
717 (range.pci_space & 0x40000000) ?
720 /* We support only 3 memory ranges */
723 " \\--> Skipped (too many) !\n");
726 /* Handles ISA memory hole space here */
727 if (range.pci_addr == 0) {
728 if (primary || isa_mem_base == 0)
729 isa_mem_base = range.cpu_addr;
730 hose->isa_mem_phys = range.cpu_addr;
731 hose->isa_mem_size = range.size;
735 hose->mem_offset[memno] = range.cpu_addr -
737 res = &hose->mem_resources[memno++];
741 res->name = dev->full_name;
742 res->flags = range.flags;
743 res->start = range.cpu_addr;
744 res->end = range.cpu_addr + range.size - 1;
745 res->parent = res->child = res->sibling = NULL;
750 /* Decide whether to display the domain number in /proc */
751 int pci_proc_domain(struct pci_bus *bus)
753 struct pci_controller *hose = pci_bus_to_host(bus);
755 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
757 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
758 return hose->global_number != 0;
762 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
764 if (ppc_md.pcibios_root_bridge_prepare)
765 return ppc_md.pcibios_root_bridge_prepare(bridge);
770 /* This header fixup will do the resource fixup for all devices as they are
771 * probed, but not for bridge ranges
773 static void pcibios_fixup_resources(struct pci_dev *dev)
775 struct pci_controller *hose = pci_bus_to_host(dev->bus);
779 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
783 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
784 struct resource *res = dev->resource + i;
785 struct pci_bus_region reg;
789 /* If we're going to re-assign everything, we mark all resources
790 * as unset (and 0-base them). In addition, we mark BARs starting
791 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
792 * since in that case, we don't want to re-assign anything
794 pcibios_resource_to_bus(dev->bus, ®, res);
795 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
796 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
797 /* Only print message if not re-assigning */
798 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
799 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
802 (unsigned long long)res->start,
803 (unsigned long long)res->end,
804 (unsigned int)res->flags);
805 res->end -= res->start;
807 res->flags |= IORESOURCE_UNSET;
811 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
813 (unsigned long long)res->start,\
814 (unsigned long long)res->end,
815 (unsigned int)res->flags);
818 /* Call machine specific resource fixup */
819 if (ppc_md.pcibios_fixup_resources)
820 ppc_md.pcibios_fixup_resources(dev);
822 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
824 /* This function tries to figure out if a bridge resource has been initialized
825 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
826 * things go more smoothly when it gets it right. It should covers cases such
827 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
829 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
830 struct resource *res)
832 struct pci_controller *hose = pci_bus_to_host(bus);
833 struct pci_dev *dev = bus->self;
834 resource_size_t offset;
835 struct pci_bus_region region;
839 /* We don't do anything if PCI_PROBE_ONLY is set */
840 if (pci_has_flag(PCI_PROBE_ONLY))
843 /* Job is a bit different between memory and IO */
844 if (res->flags & IORESOURCE_MEM) {
845 pcibios_resource_to_bus(dev->bus, ®ion, res);
847 /* If the BAR is non-0 then it's probably been initialized */
848 if (region.start != 0)
851 /* The BAR is 0, let's check if memory decoding is enabled on
852 * the bridge. If not, we consider it unassigned
854 pci_read_config_word(dev, PCI_COMMAND, &command);
855 if ((command & PCI_COMMAND_MEMORY) == 0)
858 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
859 * resources covers that starting address (0 then it's good enough for
860 * us for memory space)
862 for (i = 0; i < 3; i++) {
863 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
864 hose->mem_resources[i].start == hose->mem_offset[i])
868 /* Well, it starts at 0 and we know it will collide so we may as
869 * well consider it as unassigned. That covers the Apple case.
873 /* If the BAR is non-0, then we consider it assigned */
874 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
875 if (((res->start - offset) & 0xfffffffful) != 0)
878 /* Here, we are a bit different than memory as typically IO space
879 * starting at low addresses -is- valid. What we do instead if that
880 * we consider as unassigned anything that doesn't have IO enabled
881 * in the PCI command register, and that's it.
883 pci_read_config_word(dev, PCI_COMMAND, &command);
884 if (command & PCI_COMMAND_IO)
887 /* It's starting at 0 and IO is disabled in the bridge, consider
894 /* Fixup resources of a PCI<->PCI bridge */
895 static void pcibios_fixup_bridge(struct pci_bus *bus)
897 struct resource *res;
900 struct pci_dev *dev = bus->self;
902 pci_bus_for_each_resource(bus, res, i) {
903 if (!res || !res->flags)
905 if (i >= 3 && bus->self->transparent)
908 /* If we're going to reassign everything, we can
909 * shrink the P2P resource to have size as being
910 * of 0 in order to save space.
912 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
913 res->flags |= IORESOURCE_UNSET;
919 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
921 (unsigned long long)res->start,\
922 (unsigned long long)res->end,
923 (unsigned int)res->flags);
925 /* Try to detect uninitialized P2P bridge resources,
926 * and clear them out so they get re-assigned later
928 if (pcibios_uninitialized_bridge_resource(bus, res)) {
930 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
935 void pcibios_setup_bus_self(struct pci_bus *bus)
937 /* Fix up the bus resources for P2P bridges */
938 if (bus->self != NULL)
939 pcibios_fixup_bridge(bus);
941 /* Platform specific bus fixups. This is currently only used
942 * by fsl_pci and I'm hoping to get rid of it at some point
944 if (ppc_md.pcibios_fixup_bus)
945 ppc_md.pcibios_fixup_bus(bus);
947 /* Setup bus DMA mappings */
948 pci_dma_bus_setup(bus);
951 static void pcibios_setup_device(struct pci_dev *dev)
953 /* Fixup NUMA node as it may not be setup yet by the generic
954 * code and is needed by the DMA init
956 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
958 /* Hook up default DMA ops */
959 set_dma_ops(&dev->dev, pci_dma_ops);
960 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
962 /* Additional platform DMA/iommu setup */
963 pci_dma_dev_setup(dev);
965 /* Read default IRQs and fixup if necessary */
966 pci_read_irq_line(dev);
967 if (ppc_md.pci_irq_fixup)
968 ppc_md.pci_irq_fixup(dev);
971 int pcibios_add_device(struct pci_dev *dev)
974 * We can only call pcibios_setup_device() after bus setup is complete,
975 * since some of the platform specific DMA setup code depends on it.
977 if (dev->bus->is_added)
978 pcibios_setup_device(dev);
982 void pcibios_setup_bus_devices(struct pci_bus *bus)
986 pr_debug("PCI: Fixup bus devices %d (%s)\n",
987 bus->number, bus->self ? pci_name(bus->self) : "PHB");
989 list_for_each_entry(dev, &bus->devices, bus_list) {
990 /* Cardbus can call us to add new devices to a bus, so ignore
991 * those who are already fully discovered
996 pcibios_setup_device(dev);
1000 void pcibios_set_master(struct pci_dev *dev)
1002 /* No special bus mastering setup handling */
1005 void pcibios_fixup_bus(struct pci_bus *bus)
1007 /* When called from the generic PCI probe, read PCI<->PCI bridge
1008 * bases. This is -not- called when generating the PCI tree from
1009 * the OF device-tree.
1011 pci_read_bridge_bases(bus);
1013 /* Now fixup the bus bus */
1014 pcibios_setup_bus_self(bus);
1016 /* Now fixup devices on that bus */
1017 pcibios_setup_bus_devices(bus);
1019 EXPORT_SYMBOL(pcibios_fixup_bus);
1021 void pci_fixup_cardbus(struct pci_bus *bus)
1023 /* Now fixup devices on that bus */
1024 pcibios_setup_bus_devices(bus);
1028 static int skip_isa_ioresource_align(struct pci_dev *dev)
1030 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1031 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1037 * We need to avoid collisions with `mirrored' VGA ports
1038 * and other strange ISA hardware, so we always want the
1039 * addresses to be allocated in the 0x000-0x0ff region
1042 * Why? Because some silly external IO cards only decode
1043 * the low 10 bits of the IO address. The 0x00-0xff region
1044 * is reserved for motherboard devices that decode all 16
1045 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1046 * but we want to try to avoid allocating at 0x2900-0x2bff
1047 * which might have be mirrored at 0x0100-0x03ff..
1049 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1050 resource_size_t size, resource_size_t align)
1052 struct pci_dev *dev = data;
1053 resource_size_t start = res->start;
1055 if (res->flags & IORESOURCE_IO) {
1056 if (skip_isa_ioresource_align(dev))
1059 start = (start + 0x3ff) & ~0x3ff;
1064 EXPORT_SYMBOL(pcibios_align_resource);
1067 * Reparent resource children of pr that conflict with res
1068 * under res, and make res replace those children.
1070 static int reparent_resources(struct resource *parent,
1071 struct resource *res)
1073 struct resource *p, **pp;
1074 struct resource **firstpp = NULL;
1076 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1077 if (p->end < res->start)
1079 if (res->end < p->start)
1081 if (p->start < res->start || p->end > res->end)
1082 return -1; /* not completely contained */
1083 if (firstpp == NULL)
1086 if (firstpp == NULL)
1087 return -1; /* didn't find any conflicting entries? */
1088 res->parent = parent;
1089 res->child = *firstpp;
1093 for (p = res->child; p != NULL; p = p->sibling) {
1095 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1097 (unsigned long long)p->start,
1098 (unsigned long long)p->end, res->name);
1104 * Handle resources of PCI devices. If the world were perfect, we could
1105 * just allocate all the resource regions and do nothing more. It isn't.
1106 * On the other hand, we cannot just re-allocate all devices, as it would
1107 * require us to know lots of host bridge internals. So we attempt to
1108 * keep as much of the original configuration as possible, but tweak it
1109 * when it's found to be wrong.
1111 * Known BIOS problems we have to work around:
1112 * - I/O or memory regions not configured
1113 * - regions configured, but not enabled in the command register
1114 * - bogus I/O addresses above 64K used
1115 * - expansion ROMs left enabled (this may sound harmless, but given
1116 * the fact the PCI specs explicitly allow address decoders to be
1117 * shared between expansion ROMs and other resource regions, it's
1118 * at least dangerous)
1121 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1122 * This gives us fixed barriers on where we can allocate.
1123 * (2) Allocate resources for all enabled devices. If there is
1124 * a collision, just mark the resource as unallocated. Also
1125 * disable expansion ROMs during this step.
1126 * (3) Try to allocate resources for disabled devices. If the
1127 * resources were assigned correctly, everything goes well,
1128 * if they weren't, they won't disturb allocation of other
1130 * (4) Assign new addresses to resources which were either
1131 * not configured at all or misconfigured. If explicitly
1132 * requested by the user, configure expansion ROM address
1136 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1140 struct resource *res, *pr;
1142 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1143 pci_domain_nr(bus), bus->number);
1145 pci_bus_for_each_resource(bus, res, i) {
1146 if (!res || !res->flags || res->start > res->end || res->parent)
1149 /* If the resource was left unset at this point, we clear it */
1150 if (res->flags & IORESOURCE_UNSET)
1151 goto clear_resource;
1153 if (bus->parent == NULL)
1154 pr = (res->flags & IORESOURCE_IO) ?
1155 &ioport_resource : &iomem_resource;
1157 pr = pci_find_parent_resource(bus->self, res);
1159 /* this happens when the generic PCI
1160 * code (wrongly) decides that this
1161 * bridge is transparent -- paulus
1167 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1168 "[0x%x], parent %p (%s)\n",
1169 bus->self ? pci_name(bus->self) : "PHB",
1171 (unsigned long long)res->start,
1172 (unsigned long long)res->end,
1173 (unsigned int)res->flags,
1174 pr, (pr && pr->name) ? pr->name : "nil");
1176 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1177 struct pci_dev *dev = bus->self;
1179 if (request_resource(pr, res) == 0)
1182 * Must be a conflict with an existing entry.
1183 * Move that entry (or entries) under the
1184 * bridge resource and try again.
1186 if (reparent_resources(pr, res) == 0)
1189 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1190 pci_claim_bridge_resource(dev,
1191 i + PCI_BRIDGE_RESOURCES) == 0)
1194 pr_warning("PCI: Cannot allocate resource region "
1195 "%d of PCI bridge %d, will remap\n", i, bus->number);
1197 /* The resource might be figured out when doing
1198 * reassignment based on the resources required
1199 * by the downstream PCI devices. Here we set
1200 * the size of the resource to be 0 in order to
1208 list_for_each_entry(b, &bus->children, node)
1209 pcibios_allocate_bus_resources(b);
1212 static inline void alloc_resource(struct pci_dev *dev, int idx)
1214 struct resource *pr, *r = &dev->resource[idx];
1216 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1218 (unsigned long long)r->start,
1219 (unsigned long long)r->end,
1220 (unsigned int)r->flags);
1222 pr = pci_find_parent_resource(dev, r);
1223 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1224 request_resource(pr, r) < 0) {
1225 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1226 " of device %s, will remap\n", idx, pci_name(dev));
1228 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1230 (unsigned long long)pr->start,
1231 (unsigned long long)pr->end,
1232 (unsigned int)pr->flags);
1233 /* We'll assign a new address later */
1234 r->flags |= IORESOURCE_UNSET;
1240 static void __init pcibios_allocate_resources(int pass)
1242 struct pci_dev *dev = NULL;
1247 for_each_pci_dev(dev) {
1248 pci_read_config_word(dev, PCI_COMMAND, &command);
1249 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1250 r = &dev->resource[idx];
1251 if (r->parent) /* Already allocated */
1253 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1254 continue; /* Not assigned at all */
1255 /* We only allocate ROMs on pass 1 just in case they
1256 * have been screwed up by firmware
1258 if (idx == PCI_ROM_RESOURCE )
1260 if (r->flags & IORESOURCE_IO)
1261 disabled = !(command & PCI_COMMAND_IO);
1263 disabled = !(command & PCI_COMMAND_MEMORY);
1264 if (pass == disabled)
1265 alloc_resource(dev, idx);
1269 r = &dev->resource[PCI_ROM_RESOURCE];
1271 /* Turn the ROM off, leave the resource region,
1272 * but keep it unregistered.
1275 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1276 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1277 pr_debug("PCI: Switching off ROM of %s\n",
1279 r->flags &= ~IORESOURCE_ROM_ENABLE;
1280 pci_write_config_dword(dev, dev->rom_base_reg,
1281 reg & ~PCI_ROM_ADDRESS_ENABLE);
1287 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1289 struct pci_controller *hose = pci_bus_to_host(bus);
1290 resource_size_t offset;
1291 struct resource *res, *pres;
1294 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1297 if (!(hose->io_resource.flags & IORESOURCE_IO))
1299 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1300 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1301 BUG_ON(res == NULL);
1302 res->name = "Legacy IO";
1303 res->flags = IORESOURCE_IO;
1304 res->start = offset;
1305 res->end = (offset + 0xfff) & 0xfffffffful;
1306 pr_debug("Candidate legacy IO: %pR\n", res);
1307 if (request_resource(&hose->io_resource, res)) {
1309 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1310 pci_domain_nr(bus), bus->number, res);
1315 /* Check for memory */
1316 for (i = 0; i < 3; i++) {
1317 pres = &hose->mem_resources[i];
1318 offset = hose->mem_offset[i];
1319 if (!(pres->flags & IORESOURCE_MEM))
1321 pr_debug("hose mem res: %pR\n", pres);
1322 if ((pres->start - offset) <= 0xa0000 &&
1323 (pres->end - offset) >= 0xbffff)
1328 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1329 BUG_ON(res == NULL);
1330 res->name = "Legacy VGA memory";
1331 res->flags = IORESOURCE_MEM;
1332 res->start = 0xa0000 + offset;
1333 res->end = 0xbffff + offset;
1334 pr_debug("Candidate VGA memory: %pR\n", res);
1335 if (request_resource(pres, res)) {
1337 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1338 pci_domain_nr(bus), bus->number, res);
1343 void __init pcibios_resource_survey(void)
1347 /* Allocate and assign resources */
1348 list_for_each_entry(b, &pci_root_buses, node)
1349 pcibios_allocate_bus_resources(b);
1350 pcibios_allocate_resources(0);
1351 pcibios_allocate_resources(1);
1353 /* Before we start assigning unassigned resource, we try to reserve
1354 * the low IO area and the VGA memory area if they intersect the
1355 * bus available resources to avoid allocating things on top of them
1357 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1358 list_for_each_entry(b, &pci_root_buses, node)
1359 pcibios_reserve_legacy_regions(b);
1362 /* Now, if the platform didn't decide to blindly trust the firmware,
1363 * we proceed to assigning things that were left unassigned
1365 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1366 pr_debug("PCI: Assigning unassigned resources...\n");
1367 pci_assign_unassigned_resources();
1370 /* Call machine dependent fixup */
1371 if (ppc_md.pcibios_fixup)
1372 ppc_md.pcibios_fixup();
1375 /* This is used by the PCI hotplug driver to allocate resource
1376 * of newly plugged busses. We can try to consolidate with the
1377 * rest of the code later, for now, keep it as-is as our main
1378 * resource allocation function doesn't deal with sub-trees yet.
1380 void pcibios_claim_one_bus(struct pci_bus *bus)
1382 struct pci_dev *dev;
1383 struct pci_bus *child_bus;
1385 list_for_each_entry(dev, &bus->devices, bus_list) {
1388 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1389 struct resource *r = &dev->resource[i];
1391 if (r->parent || !r->start || !r->flags)
1394 pr_debug("PCI: Claiming %s: "
1395 "Resource %d: %016llx..%016llx [%x]\n",
1397 (unsigned long long)r->start,
1398 (unsigned long long)r->end,
1399 (unsigned int)r->flags);
1401 if (pci_claim_resource(dev, i) == 0)
1404 pci_claim_bridge_resource(dev, i);
1408 list_for_each_entry(child_bus, &bus->children, node)
1409 pcibios_claim_one_bus(child_bus);
1413 /* pcibios_finish_adding_to_bus
1415 * This is to be called by the hotplug code after devices have been
1416 * added to a bus, this include calling it for a PHB that is just
1419 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1421 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1422 pci_domain_nr(bus), bus->number);
1424 /* Allocate bus and devices resources */
1425 pcibios_allocate_bus_resources(bus);
1426 pcibios_claim_one_bus(bus);
1427 if (!pci_has_flag(PCI_PROBE_ONLY))
1428 pci_assign_unassigned_bus_resources(bus);
1431 eeh_add_device_tree_late(bus);
1433 /* Add new devices to global lists. Register in proc, sysfs. */
1434 pci_bus_add_devices(bus);
1436 /* sysfs files should only be added after devices are added */
1437 eeh_add_sysfs_files(bus);
1439 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1441 int pcibios_enable_device(struct pci_dev *dev, int mask)
1443 if (!pcibios_enable_device_hook(dev))
1446 return pci_enable_resources(dev, mask);
1449 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1451 return (unsigned long) hose->io_base_virt - _IO_BASE;
1454 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1455 struct list_head *resources)
1457 struct resource *res;
1458 resource_size_t offset;
1461 /* Hookup PHB IO resource */
1462 res = &hose->io_resource;
1465 pr_info("PCI: I/O resource not set for host"
1466 " bridge %s (domain %d)\n",
1467 hose->dn->full_name, hose->global_number);
1469 offset = pcibios_io_space_offset(hose);
1471 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n",
1472 (unsigned long long)res->start,
1473 (unsigned long long)res->end,
1474 (unsigned long)res->flags,
1475 (unsigned long long)offset);
1476 pci_add_resource_offset(resources, res, offset);
1479 /* Hookup PHB Memory resources */
1480 for (i = 0; i < 3; ++i) {
1481 res = &hose->mem_resources[i];
1484 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1485 "host bridge %s (domain %d)\n",
1486 hose->dn->full_name, hose->global_number);
1489 offset = hose->mem_offset[i];
1492 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
1493 (unsigned long long)res->start,
1494 (unsigned long long)res->end,
1495 (unsigned long)res->flags,
1496 (unsigned long long)offset);
1498 pci_add_resource_offset(resources, res, offset);
1503 * Null PCI config access functions, for the case when we can't
1506 #define NULL_PCI_OP(rw, size, type) \
1508 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1510 return PCIBIOS_DEVICE_NOT_FOUND; \
1514 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1517 return PCIBIOS_DEVICE_NOT_FOUND;
1521 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1524 return PCIBIOS_DEVICE_NOT_FOUND;
1527 static struct pci_ops null_pci_ops =
1529 .read = null_read_config,
1530 .write = null_write_config,
1534 * These functions are used early on before PCI scanning is done
1535 * and all of the pci_dev and pci_bus structures have been created.
1537 static struct pci_bus *
1538 fake_pci_bus(struct pci_controller *hose, int busnr)
1540 static struct pci_bus bus;
1543 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1547 bus.ops = hose? hose->ops: &null_pci_ops;
1551 #define EARLY_PCI_OP(rw, size, type) \
1552 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1553 int devfn, int offset, type value) \
1555 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1556 devfn, offset, value); \
1559 EARLY_PCI_OP(read, byte, u8 *)
1560 EARLY_PCI_OP(read, word, u16 *)
1561 EARLY_PCI_OP(read, dword, u32 *)
1562 EARLY_PCI_OP(write, byte, u8)
1563 EARLY_PCI_OP(write, word, u16)
1564 EARLY_PCI_OP(write, dword, u32)
1566 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1569 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1572 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1574 struct pci_controller *hose = bus->sysdata;
1576 return of_node_get(hose->dn);
1580 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1581 * @hose: Pointer to the PCI host controller instance structure
1583 void pcibios_scan_phb(struct pci_controller *hose)
1585 LIST_HEAD(resources);
1586 struct pci_bus *bus;
1587 struct device_node *node = hose->dn;
1590 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1592 /* Get some IO space for the new PHB */
1593 pcibios_setup_phb_io_space(hose);
1595 /* Wire up PHB bus resources */
1596 pcibios_setup_phb_resources(hose, &resources);
1598 hose->busn.start = hose->first_busno;
1599 hose->busn.end = hose->last_busno;
1600 hose->busn.flags = IORESOURCE_BUS;
1601 pci_add_resource(&resources, &hose->busn);
1603 /* Create an empty bus for the toplevel */
1604 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1605 hose->ops, hose, &resources);
1607 pr_err("Failed to create bus for PCI domain %04x\n",
1608 hose->global_number);
1609 pci_free_resource_list(&resources);
1614 /* Get probe mode and perform scan */
1615 mode = PCI_PROBE_NORMAL;
1617 mode = pci_probe_mode(bus);
1618 pr_debug(" probe mode: %d\n", mode);
1619 if (mode == PCI_PROBE_DEVTREE)
1620 of_scan_bus(node, bus);
1622 if (mode == PCI_PROBE_NORMAL) {
1623 pci_bus_update_busn_res_end(bus, 255);
1624 hose->last_busno = pci_scan_child_bus(bus);
1625 pci_bus_update_busn_res_end(bus, hose->last_busno);
1628 /* Platform gets a chance to do some global fixups before
1629 * we proceed to resource allocation
1631 if (ppc_md.pcibios_fixup_phb)
1632 ppc_md.pcibios_fixup_phb(hose);
1634 /* Configure PCI Express settings */
1635 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1636 struct pci_bus *child;
1637 list_for_each_entry(child, &bus->children, node)
1638 pcie_bus_configure_settings(child);
1642 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1644 int i, class = dev->class >> 8;
1645 /* When configured as agent, programing interface = 1 */
1646 int prog_if = dev->class & 0xf;
1648 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1649 class == PCI_CLASS_BRIDGE_OTHER) &&
1650 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1652 (dev->bus->parent == NULL)) {
1653 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1654 dev->resource[i].start = 0;
1655 dev->resource[i].end = 0;
1656 dev->resource[i].flags = 0;
1660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1663 static void fixup_vga(struct pci_dev *pdev)
1667 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1668 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1669 vga_set_default_device(pdev);
1672 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1673 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);