2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
44 static DEFINE_SPINLOCK(hose_spinlock);
47 /* XXX kill that some day ... */
48 static int global_phb_number; /* Global phb counter */
50 /* ISA Memory physical address */
51 resource_size_t isa_mem_base;
54 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
56 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_map_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
69 struct pci_controller *phb;
71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
74 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
79 phb->is_dynamic = mem_init_done;
82 int nid = of_node_to_nid(dev);
84 if (nid < 0 || !node_online(nid))
87 PHB_SET_NODE(phb, nid);
93 void pcibios_free_controller(struct pci_controller *phb)
95 spin_lock(&hose_spinlock);
96 list_del(&phb->list_node);
97 spin_unlock(&hose_spinlock);
104 * The function is used to return the minimal alignment
105 * for memory or I/O windows of the associated P2P bridge.
106 * By default, 4KiB alignment for I/O windows and 1MiB for
109 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
112 if (ppc_md.pcibios_window_alignment)
113 return ppc_md.pcibios_window_alignment(bus, type);
116 * PCI core will figure out the default
117 * alignment: 4KiB for I/O and 1MiB for
123 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
126 return hose->pci_io_size;
128 return resource_size(&hose->io_resource);
132 int pcibios_vaddr_is_ioport(void __iomem *address)
135 struct pci_controller *hose;
136 resource_size_t size;
138 spin_lock(&hose_spinlock);
139 list_for_each_entry(hose, &hose_list, list_node) {
140 size = pcibios_io_size(hose);
141 if (address >= hose->io_base_virt &&
142 address < (hose->io_base_virt + size)) {
147 spin_unlock(&hose_spinlock);
151 unsigned long pci_address_to_pio(phys_addr_t address)
153 struct pci_controller *hose;
154 resource_size_t size;
155 unsigned long ret = ~0;
157 spin_lock(&hose_spinlock);
158 list_for_each_entry(hose, &hose_list, list_node) {
159 size = pcibios_io_size(hose);
160 if (address >= hose->io_base_phys &&
161 address < (hose->io_base_phys + size)) {
163 (unsigned long)hose->io_base_virt - _IO_BASE;
164 ret = base + (address - hose->io_base_phys);
168 spin_unlock(&hose_spinlock);
172 EXPORT_SYMBOL_GPL(pci_address_to_pio);
175 * Return the domain number for this bus.
177 int pci_domain_nr(struct pci_bus *bus)
179 struct pci_controller *hose = pci_bus_to_host(bus);
181 return hose->global_number;
183 EXPORT_SYMBOL(pci_domain_nr);
185 /* This routine is meant to be used early during boot, when the
186 * PCI bus numbers have not yet been assigned, and you need to
187 * issue PCI config cycles to an OF device.
188 * It could also be used to "fix" RTAS config cycles if you want
189 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
192 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
195 struct pci_controller *hose, *tmp;
196 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
197 if (hose->dn == node)
204 static ssize_t pci_show_devspec(struct device *dev,
205 struct device_attribute *attr, char *buf)
207 struct pci_dev *pdev;
208 struct device_node *np;
210 pdev = to_pci_dev (dev);
211 np = pci_device_to_OF_node(pdev);
212 if (np == NULL || np->full_name == NULL)
214 return sprintf(buf, "%s", np->full_name);
216 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
218 /* Add sysfs properties */
219 int pcibios_add_platform_entries(struct pci_dev *pdev)
221 return device_create_file(&pdev->dev, &dev_attr_devspec);
225 * Reads the interrupt pin to determine if interrupt is use by card.
226 * If the interrupt is used, then gets the interrupt line from the
227 * openfirmware and sets it in the pci_dev and pci_config line.
229 static int pci_read_irq_line(struct pci_dev *pci_dev)
234 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
237 memset(&oirq, 0xff, sizeof(oirq));
239 /* Try to get a mapping from the device-tree */
240 if (of_irq_map_pci(pci_dev, &oirq)) {
243 /* If that fails, lets fallback to what is in the config
244 * space and map that through the default controller. We
245 * also set the type to level low since that's what PCI
246 * interrupts are. If your platform does differently, then
247 * either provide a proper interrupt tree or don't use this
250 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
255 line == 0xff || line == 0) {
258 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
261 virq = irq_create_mapping(NULL, line);
263 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
265 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
266 oirq.size, oirq.specifier[0], oirq.specifier[1],
267 of_node_full_name(oirq.controller));
269 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
273 pr_debug(" Failed to map !\n");
277 pr_debug(" Mapped to linux irq %d\n", virq);
285 * Platform support for /proc/bus/pci/X/Y mmap()s,
286 * modelled on the sparc64 implementation by Dave Miller.
291 * Adjust vm_pgoff of VMA such that it is the physical page offset
292 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
294 * Basically, the user finds the base address for his device which he wishes
295 * to mmap. They read the 32-bit value from the config space base register,
296 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
297 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
299 * Returns negative error code on failure, zero on success.
301 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
302 resource_size_t *offset,
303 enum pci_mmap_state mmap_state)
305 struct pci_controller *hose = pci_bus_to_host(dev->bus);
306 unsigned long io_offset = 0;
310 return NULL; /* should never happen */
312 /* If memory, add on the PCI bridge address offset */
313 if (mmap_state == pci_mmap_mem) {
314 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
315 *offset += hose->pci_mem_offset;
317 res_bit = IORESOURCE_MEM;
319 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
320 *offset += io_offset;
321 res_bit = IORESOURCE_IO;
325 * Check that the offset requested corresponds to one of the
326 * resources of the device.
328 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
329 struct resource *rp = &dev->resource[i];
330 int flags = rp->flags;
332 /* treat ROM as memory (should be already) */
333 if (i == PCI_ROM_RESOURCE)
334 flags |= IORESOURCE_MEM;
336 /* Active and same type? */
337 if ((flags & res_bit) == 0)
340 /* In the range of this resource? */
341 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
344 /* found it! construct the final physical address */
345 if (mmap_state == pci_mmap_io)
346 *offset += hose->io_base_phys - io_offset;
354 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
357 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
359 enum pci_mmap_state mmap_state,
363 /* Write combine is always 0 on non-memory space mappings. On
364 * memory space, if the user didn't pass 1, we check for a
365 * "prefetchable" resource. This is a bit hackish, but we use
366 * this to workaround the inability of /sysfs to provide a write
369 if (mmap_state != pci_mmap_mem)
371 else if (write_combine == 0) {
372 if (rp->flags & IORESOURCE_PREFETCH)
376 /* XXX would be nice to have a way to ask for write-through */
378 return pgprot_noncached_wc(protection);
380 return pgprot_noncached(protection);
384 * This one is used by /dev/mem and fbdev who have no clue about the
385 * PCI device, it tries to find the PCI device first and calls the
388 pgprot_t pci_phys_mem_access_prot(struct file *file,
393 struct pci_dev *pdev = NULL;
394 struct resource *found = NULL;
395 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
398 if (page_is_ram(pfn))
401 prot = pgprot_noncached(prot);
402 for_each_pci_dev(pdev) {
403 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
404 struct resource *rp = &pdev->resource[i];
405 int flags = rp->flags;
407 /* Active and same type? */
408 if ((flags & IORESOURCE_MEM) == 0)
410 /* In the range of this resource? */
411 if (offset < (rp->start & PAGE_MASK) ||
421 if (found->flags & IORESOURCE_PREFETCH)
422 prot = pgprot_noncached_wc(prot);
426 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
427 (unsigned long long)offset, pgprot_val(prot));
434 * Perform the actual remap of the pages for a PCI device mapping, as
435 * appropriate for this architecture. The region in the process to map
436 * is described by vm_start and vm_end members of VMA, the base physical
437 * address is found in vm_pgoff.
438 * The pci device structure is provided so that architectures may make mapping
439 * decisions on a per-device or per-bus basis.
441 * Returns a negative error code on failure, zero on success.
443 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
444 enum pci_mmap_state mmap_state, int write_combine)
446 resource_size_t offset =
447 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
451 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
455 vma->vm_pgoff = offset >> PAGE_SHIFT;
456 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
458 mmap_state, write_combine);
460 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
461 vma->vm_end - vma->vm_start, vma->vm_page_prot);
466 /* This provides legacy IO read access on a bus */
467 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
469 unsigned long offset;
470 struct pci_controller *hose = pci_bus_to_host(bus);
471 struct resource *rp = &hose->io_resource;
474 /* Check if port can be supported by that bus. We only check
475 * the ranges of the PHB though, not the bus itself as the rules
476 * for forwarding legacy cycles down bridges are not our problem
477 * here. So if the host bridge supports it, we do it.
479 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
482 if (!(rp->flags & IORESOURCE_IO))
484 if (offset < rp->start || (offset + size) > rp->end)
486 addr = hose->io_base_virt + port;
490 *((u8 *)val) = in_8(addr);
495 *((u16 *)val) = in_le16(addr);
500 *((u32 *)val) = in_le32(addr);
506 /* This provides legacy IO write access on a bus */
507 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
509 unsigned long offset;
510 struct pci_controller *hose = pci_bus_to_host(bus);
511 struct resource *rp = &hose->io_resource;
514 /* Check if port can be supported by that bus. We only check
515 * the ranges of the PHB though, not the bus itself as the rules
516 * for forwarding legacy cycles down bridges are not our problem
517 * here. So if the host bridge supports it, we do it.
519 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
522 if (!(rp->flags & IORESOURCE_IO))
524 if (offset < rp->start || (offset + size) > rp->end)
526 addr = hose->io_base_virt + port;
528 /* WARNING: The generic code is idiotic. It gets passed a pointer
529 * to what can be a 1, 2 or 4 byte quantity and always reads that
530 * as a u32, which means that we have to correct the location of
531 * the data read within those 32 bits for size 1 and 2
535 out_8(addr, val >> 24);
540 out_le16(addr, val >> 16);
551 /* This provides legacy IO or memory mmap access on a bus */
552 int pci_mmap_legacy_page_range(struct pci_bus *bus,
553 struct vm_area_struct *vma,
554 enum pci_mmap_state mmap_state)
556 struct pci_controller *hose = pci_bus_to_host(bus);
557 resource_size_t offset =
558 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
559 resource_size_t size = vma->vm_end - vma->vm_start;
562 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
563 pci_domain_nr(bus), bus->number,
564 mmap_state == pci_mmap_mem ? "MEM" : "IO",
565 (unsigned long long)offset,
566 (unsigned long long)(offset + size - 1));
568 if (mmap_state == pci_mmap_mem) {
571 * Because X is lame and can fail starting if it gets an error trying
572 * to mmap legacy_mem (instead of just moving on without legacy memory
573 * access) we fake it here by giving it anonymous memory, effectively
574 * behaving just like /dev/zero
576 if ((offset + size) > hose->isa_mem_size) {
578 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
579 current->comm, current->pid, pci_domain_nr(bus), bus->number);
580 if (vma->vm_flags & VM_SHARED)
581 return shmem_zero_setup(vma);
584 offset += hose->isa_mem_phys;
586 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
587 unsigned long roffset = offset + io_offset;
588 rp = &hose->io_resource;
589 if (!(rp->flags & IORESOURCE_IO))
591 if (roffset < rp->start || (roffset + size) > rp->end)
593 offset += hose->io_base_phys;
595 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
597 vma->vm_pgoff = offset >> PAGE_SHIFT;
598 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
599 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
600 vma->vm_end - vma->vm_start,
604 void pci_resource_to_user(const struct pci_dev *dev, int bar,
605 const struct resource *rsrc,
606 resource_size_t *start, resource_size_t *end)
608 struct pci_controller *hose = pci_bus_to_host(dev->bus);
609 resource_size_t offset = 0;
614 if (rsrc->flags & IORESOURCE_IO)
615 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
617 /* We pass a fully fixed up address to userland for MMIO instead of
618 * a BAR value because X is lame and expects to be able to use that
619 * to pass to /dev/mem !
621 * That means that we'll have potentially 64 bits values where some
622 * userland apps only expect 32 (like X itself since it thinks only
623 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
626 * Hopefully, the sysfs insterface is immune to that gunk. Once X
627 * has been fixed (and the fix spread enough), we can re-enable the
628 * 2 lines below and pass down a BAR value to userland. In that case
629 * we'll also have to re-enable the matching code in
630 * __pci_mmap_make_offset().
635 else if (rsrc->flags & IORESOURCE_MEM)
636 offset = hose->pci_mem_offset;
639 *start = rsrc->start - offset;
640 *end = rsrc->end - offset;
644 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
645 * @hose: newly allocated pci_controller to be setup
646 * @dev: device node of the host bridge
647 * @primary: set if primary bus (32 bits only, soon to be deprecated)
649 * This function will parse the "ranges" property of a PCI host bridge device
650 * node and setup the resource mapping of a pci controller based on its
653 * Life would be boring if it wasn't for a few issues that we have to deal
656 * - We can only cope with one IO space range and up to 3 Memory space
657 * ranges. However, some machines (thanks Apple !) tend to split their
658 * space into lots of small contiguous ranges. So we have to coalesce.
660 * - Some busses have IO space not starting at 0, which causes trouble with
661 * the way we do our IO resource renumbering. The code somewhat deals with
662 * it for 64 bits but I would expect problems on 32 bits.
664 * - Some 32 bits platforms such as 4xx can have physical space larger than
665 * 32 bits so we need to use 64 bits values for the parsing
667 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
668 struct device_node *dev, int primary)
672 int pna = of_n_addr_cells(dev);
676 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
677 struct resource *res;
679 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
680 dev->full_name, primary ? "(primary)" : "");
682 /* Get ranges property */
683 ranges = of_get_property(dev, "ranges", &rlen);
688 while ((rlen -= np * 4) >= 0) {
689 /* Read next ranges element */
690 pci_space = ranges[0];
691 pci_addr = of_read_number(ranges + 1, 2);
692 cpu_addr = of_translate_address(dev, ranges + 3);
693 size = of_read_number(ranges + pna + 3, 2);
696 /* If we failed translation or got a zero-sized region
697 * (some FW try to feed us with non sensical zero sized regions
698 * such as power3 which look like some kind of attempt at exposing
699 * the VGA memory hole)
701 if (cpu_addr == OF_BAD_ADDR || size == 0)
704 /* Now consume following elements while they are contiguous */
705 for (; rlen >= np * sizeof(u32);
706 ranges += np, rlen -= np * 4) {
707 if (ranges[0] != pci_space)
709 pci_next = of_read_number(ranges + 1, 2);
710 cpu_next = of_translate_address(dev, ranges + 3);
711 if (pci_next != pci_addr + size ||
712 cpu_next != cpu_addr + size)
714 size += of_read_number(ranges + pna + 3, 2);
717 /* Act based on address space type */
719 switch ((pci_space >> 24) & 0x3) {
720 case 1: /* PCI IO space */
722 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
723 cpu_addr, cpu_addr + size - 1, pci_addr);
725 /* We support only one IO range */
726 if (hose->pci_io_size) {
728 " \\--> Skipped (too many) !\n");
732 /* On 32 bits, limit I/O space to 16MB */
733 if (size > 0x01000000)
736 /* 32 bits needs to map IOs here */
737 hose->io_base_virt = ioremap(cpu_addr, size);
739 /* Expect trouble if pci_addr is not 0 */
742 (unsigned long)hose->io_base_virt;
743 #endif /* CONFIG_PPC32 */
744 /* pci_io_size and io_base_phys always represent IO
745 * space starting at 0 so we factor in pci_addr
747 hose->pci_io_size = pci_addr + size;
748 hose->io_base_phys = cpu_addr - pci_addr;
751 res = &hose->io_resource;
752 res->flags = IORESOURCE_IO;
753 res->start = pci_addr;
755 case 2: /* PCI Memory space */
756 case 3: /* PCI 64 bits Memory space */
758 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
759 cpu_addr, cpu_addr + size - 1, pci_addr,
760 (pci_space & 0x40000000) ? "Prefetch" : "");
762 /* We support only 3 memory ranges */
765 " \\--> Skipped (too many) !\n");
768 /* Handles ISA memory hole space here */
770 if (primary || isa_mem_base == 0)
771 isa_mem_base = cpu_addr;
772 hose->isa_mem_phys = cpu_addr;
773 hose->isa_mem_size = size;
777 hose->mem_offset[memno] = cpu_addr - pci_addr;
778 res = &hose->mem_resources[memno++];
779 res->flags = IORESOURCE_MEM;
780 if (pci_space & 0x40000000)
781 res->flags |= IORESOURCE_PREFETCH;
782 res->start = cpu_addr;
786 res->name = dev->full_name;
787 res->end = res->start + size - 1;
795 /* Decide whether to display the domain number in /proc */
796 int pci_proc_domain(struct pci_bus *bus)
798 struct pci_controller *hose = pci_bus_to_host(bus);
800 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
802 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
803 return hose->global_number != 0;
807 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
809 if (ppc_md.pcibios_root_bridge_prepare)
810 return ppc_md.pcibios_root_bridge_prepare(bridge);
815 /* This header fixup will do the resource fixup for all devices as they are
816 * probed, but not for bridge ranges
818 static void pcibios_fixup_resources(struct pci_dev *dev)
820 struct pci_controller *hose = pci_bus_to_host(dev->bus);
824 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
828 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
829 struct resource *res = dev->resource + i;
833 /* If we're going to re-assign everything, we mark all resources
834 * as unset (and 0-base them). In addition, we mark BARs starting
835 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
836 * since in that case, we don't want to re-assign anything
838 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
839 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
840 /* Only print message if not re-assigning */
841 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
842 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
845 (unsigned long long)res->start,
846 (unsigned long long)res->end,
847 (unsigned int)res->flags);
848 res->end -= res->start;
850 res->flags |= IORESOURCE_UNSET;
854 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
856 (unsigned long long)res->start,\
857 (unsigned long long)res->end,
858 (unsigned int)res->flags);
861 /* Call machine specific resource fixup */
862 if (ppc_md.pcibios_fixup_resources)
863 ppc_md.pcibios_fixup_resources(dev);
865 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
867 /* This function tries to figure out if a bridge resource has been initialized
868 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
869 * things go more smoothly when it gets it right. It should covers cases such
870 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
872 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
873 struct resource *res)
875 struct pci_controller *hose = pci_bus_to_host(bus);
876 struct pci_dev *dev = bus->self;
877 resource_size_t offset;
878 struct pci_bus_region region;
882 /* We don't do anything if PCI_PROBE_ONLY is set */
883 if (pci_has_flag(PCI_PROBE_ONLY))
886 /* Job is a bit different between memory and IO */
887 if (res->flags & IORESOURCE_MEM) {
888 pcibios_resource_to_bus(dev, ®ion, res);
890 /* If the BAR is non-0 then it's probably been initialized */
891 if (region.start != 0)
894 /* The BAR is 0, let's check if memory decoding is enabled on
895 * the bridge. If not, we consider it unassigned
897 pci_read_config_word(dev, PCI_COMMAND, &command);
898 if ((command & PCI_COMMAND_MEMORY) == 0)
901 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
902 * resources covers that starting address (0 then it's good enough for
903 * us for memory space)
905 for (i = 0; i < 3; i++) {
906 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
907 hose->mem_resources[i].start == hose->mem_offset[i])
911 /* Well, it starts at 0 and we know it will collide so we may as
912 * well consider it as unassigned. That covers the Apple case.
916 /* If the BAR is non-0, then we consider it assigned */
917 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
918 if (((res->start - offset) & 0xfffffffful) != 0)
921 /* Here, we are a bit different than memory as typically IO space
922 * starting at low addresses -is- valid. What we do instead if that
923 * we consider as unassigned anything that doesn't have IO enabled
924 * in the PCI command register, and that's it.
926 pci_read_config_word(dev, PCI_COMMAND, &command);
927 if (command & PCI_COMMAND_IO)
930 /* It's starting at 0 and IO is disabled in the bridge, consider
937 /* Fixup resources of a PCI<->PCI bridge */
938 static void pcibios_fixup_bridge(struct pci_bus *bus)
940 struct resource *res;
943 struct pci_dev *dev = bus->self;
945 pci_bus_for_each_resource(bus, res, i) {
946 if (!res || !res->flags)
948 if (i >= 3 && bus->self->transparent)
951 /* If we're going to reassign everything, we can
952 * shrink the P2P resource to have size as being
953 * of 0 in order to save space.
955 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
956 res->flags |= IORESOURCE_UNSET;
962 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
964 (unsigned long long)res->start,\
965 (unsigned long long)res->end,
966 (unsigned int)res->flags);
968 /* Try to detect uninitialized P2P bridge resources,
969 * and clear them out so they get re-assigned later
971 if (pcibios_uninitialized_bridge_resource(bus, res)) {
973 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
978 void pcibios_setup_bus_self(struct pci_bus *bus)
980 /* Fix up the bus resources for P2P bridges */
981 if (bus->self != NULL)
982 pcibios_fixup_bridge(bus);
984 /* Platform specific bus fixups. This is currently only used
985 * by fsl_pci and I'm hoping to get rid of it at some point
987 if (ppc_md.pcibios_fixup_bus)
988 ppc_md.pcibios_fixup_bus(bus);
990 /* Setup bus DMA mappings */
991 if (ppc_md.pci_dma_bus_setup)
992 ppc_md.pci_dma_bus_setup(bus);
995 void pcibios_setup_device(struct pci_dev *dev)
997 /* Fixup NUMA node as it may not be setup yet by the generic
998 * code and is needed by the DMA init
1000 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1002 /* Hook up default DMA ops */
1003 set_dma_ops(&dev->dev, pci_dma_ops);
1004 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1006 /* Additional platform DMA/iommu setup */
1007 if (ppc_md.pci_dma_dev_setup)
1008 ppc_md.pci_dma_dev_setup(dev);
1010 /* Read default IRQs and fixup if necessary */
1011 pci_read_irq_line(dev);
1012 if (ppc_md.pci_irq_fixup)
1013 ppc_md.pci_irq_fixup(dev);
1016 void pcibios_setup_bus_devices(struct pci_bus *bus)
1018 struct pci_dev *dev;
1020 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1021 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1023 list_for_each_entry(dev, &bus->devices, bus_list) {
1024 /* Cardbus can call us to add new devices to a bus, so ignore
1025 * those who are already fully discovered
1030 pcibios_setup_device(dev);
1034 void pcibios_set_master(struct pci_dev *dev)
1036 /* No special bus mastering setup handling */
1039 void pcibios_fixup_bus(struct pci_bus *bus)
1041 /* When called from the generic PCI probe, read PCI<->PCI bridge
1042 * bases. This is -not- called when generating the PCI tree from
1043 * the OF device-tree.
1045 if (bus->self != NULL)
1046 pci_read_bridge_bases(bus);
1048 /* Now fixup the bus bus */
1049 pcibios_setup_bus_self(bus);
1051 /* Now fixup devices on that bus */
1052 pcibios_setup_bus_devices(bus);
1054 EXPORT_SYMBOL(pcibios_fixup_bus);
1056 void pci_fixup_cardbus(struct pci_bus *bus)
1058 /* Now fixup devices on that bus */
1059 pcibios_setup_bus_devices(bus);
1063 static int skip_isa_ioresource_align(struct pci_dev *dev)
1065 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1066 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1072 * We need to avoid collisions with `mirrored' VGA ports
1073 * and other strange ISA hardware, so we always want the
1074 * addresses to be allocated in the 0x000-0x0ff region
1077 * Why? Because some silly external IO cards only decode
1078 * the low 10 bits of the IO address. The 0x00-0xff region
1079 * is reserved for motherboard devices that decode all 16
1080 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1081 * but we want to try to avoid allocating at 0x2900-0x2bff
1082 * which might have be mirrored at 0x0100-0x03ff..
1084 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1085 resource_size_t size, resource_size_t align)
1087 struct pci_dev *dev = data;
1088 resource_size_t start = res->start;
1090 if (res->flags & IORESOURCE_IO) {
1091 if (skip_isa_ioresource_align(dev))
1094 start = (start + 0x3ff) & ~0x3ff;
1099 EXPORT_SYMBOL(pcibios_align_resource);
1102 * Reparent resource children of pr that conflict with res
1103 * under res, and make res replace those children.
1105 static int reparent_resources(struct resource *parent,
1106 struct resource *res)
1108 struct resource *p, **pp;
1109 struct resource **firstpp = NULL;
1111 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1112 if (p->end < res->start)
1114 if (res->end < p->start)
1116 if (p->start < res->start || p->end > res->end)
1117 return -1; /* not completely contained */
1118 if (firstpp == NULL)
1121 if (firstpp == NULL)
1122 return -1; /* didn't find any conflicting entries? */
1123 res->parent = parent;
1124 res->child = *firstpp;
1128 for (p = res->child; p != NULL; p = p->sibling) {
1130 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1132 (unsigned long long)p->start,
1133 (unsigned long long)p->end, res->name);
1139 * Handle resources of PCI devices. If the world were perfect, we could
1140 * just allocate all the resource regions and do nothing more. It isn't.
1141 * On the other hand, we cannot just re-allocate all devices, as it would
1142 * require us to know lots of host bridge internals. So we attempt to
1143 * keep as much of the original configuration as possible, but tweak it
1144 * when it's found to be wrong.
1146 * Known BIOS problems we have to work around:
1147 * - I/O or memory regions not configured
1148 * - regions configured, but not enabled in the command register
1149 * - bogus I/O addresses above 64K used
1150 * - expansion ROMs left enabled (this may sound harmless, but given
1151 * the fact the PCI specs explicitly allow address decoders to be
1152 * shared between expansion ROMs and other resource regions, it's
1153 * at least dangerous)
1156 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1157 * This gives us fixed barriers on where we can allocate.
1158 * (2) Allocate resources for all enabled devices. If there is
1159 * a collision, just mark the resource as unallocated. Also
1160 * disable expansion ROMs during this step.
1161 * (3) Try to allocate resources for disabled devices. If the
1162 * resources were assigned correctly, everything goes well,
1163 * if they weren't, they won't disturb allocation of other
1165 * (4) Assign new addresses to resources which were either
1166 * not configured at all or misconfigured. If explicitly
1167 * requested by the user, configure expansion ROM address
1171 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1175 struct resource *res, *pr;
1177 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1178 pci_domain_nr(bus), bus->number);
1180 pci_bus_for_each_resource(bus, res, i) {
1181 if (!res || !res->flags || res->start > res->end || res->parent)
1184 /* If the resource was left unset at this point, we clear it */
1185 if (res->flags & IORESOURCE_UNSET)
1186 goto clear_resource;
1188 if (bus->parent == NULL)
1189 pr = (res->flags & IORESOURCE_IO) ?
1190 &ioport_resource : &iomem_resource;
1192 pr = pci_find_parent_resource(bus->self, res);
1194 /* this happens when the generic PCI
1195 * code (wrongly) decides that this
1196 * bridge is transparent -- paulus
1202 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1203 "[0x%x], parent %p (%s)\n",
1204 bus->self ? pci_name(bus->self) : "PHB",
1206 (unsigned long long)res->start,
1207 (unsigned long long)res->end,
1208 (unsigned int)res->flags,
1209 pr, (pr && pr->name) ? pr->name : "nil");
1211 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1212 if (request_resource(pr, res) == 0)
1215 * Must be a conflict with an existing entry.
1216 * Move that entry (or entries) under the
1217 * bridge resource and try again.
1219 if (reparent_resources(pr, res) == 0)
1222 pr_warning("PCI: Cannot allocate resource region "
1223 "%d of PCI bridge %d, will remap\n", i, bus->number);
1225 /* The resource might be figured out when doing
1226 * reassignment based on the resources required
1227 * by the downstream PCI devices. Here we set
1228 * the size of the resource to be 0 in order to
1236 list_for_each_entry(b, &bus->children, node)
1237 pcibios_allocate_bus_resources(b);
1240 static inline void alloc_resource(struct pci_dev *dev, int idx)
1242 struct resource *pr, *r = &dev->resource[idx];
1244 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1246 (unsigned long long)r->start,
1247 (unsigned long long)r->end,
1248 (unsigned int)r->flags);
1250 pr = pci_find_parent_resource(dev, r);
1251 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1252 request_resource(pr, r) < 0) {
1253 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1254 " of device %s, will remap\n", idx, pci_name(dev));
1256 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1258 (unsigned long long)pr->start,
1259 (unsigned long long)pr->end,
1260 (unsigned int)pr->flags);
1261 /* We'll assign a new address later */
1262 r->flags |= IORESOURCE_UNSET;
1268 static void __init pcibios_allocate_resources(int pass)
1270 struct pci_dev *dev = NULL;
1275 for_each_pci_dev(dev) {
1276 pci_read_config_word(dev, PCI_COMMAND, &command);
1277 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1278 r = &dev->resource[idx];
1279 if (r->parent) /* Already allocated */
1281 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1282 continue; /* Not assigned at all */
1283 /* We only allocate ROMs on pass 1 just in case they
1284 * have been screwed up by firmware
1286 if (idx == PCI_ROM_RESOURCE )
1288 if (r->flags & IORESOURCE_IO)
1289 disabled = !(command & PCI_COMMAND_IO);
1291 disabled = !(command & PCI_COMMAND_MEMORY);
1292 if (pass == disabled)
1293 alloc_resource(dev, idx);
1297 r = &dev->resource[PCI_ROM_RESOURCE];
1299 /* Turn the ROM off, leave the resource region,
1300 * but keep it unregistered.
1303 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1304 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1305 pr_debug("PCI: Switching off ROM of %s\n",
1307 r->flags &= ~IORESOURCE_ROM_ENABLE;
1308 pci_write_config_dword(dev, dev->rom_base_reg,
1309 reg & ~PCI_ROM_ADDRESS_ENABLE);
1315 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1317 struct pci_controller *hose = pci_bus_to_host(bus);
1318 resource_size_t offset;
1319 struct resource *res, *pres;
1322 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1325 if (!(hose->io_resource.flags & IORESOURCE_IO))
1327 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1328 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1329 BUG_ON(res == NULL);
1330 res->name = "Legacy IO";
1331 res->flags = IORESOURCE_IO;
1332 res->start = offset;
1333 res->end = (offset + 0xfff) & 0xfffffffful;
1334 pr_debug("Candidate legacy IO: %pR\n", res);
1335 if (request_resource(&hose->io_resource, res)) {
1337 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1338 pci_domain_nr(bus), bus->number, res);
1343 /* Check for memory */
1344 for (i = 0; i < 3; i++) {
1345 pres = &hose->mem_resources[i];
1346 offset = hose->mem_offset[i];
1347 if (!(pres->flags & IORESOURCE_MEM))
1349 pr_debug("hose mem res: %pR\n", pres);
1350 if ((pres->start - offset) <= 0xa0000 &&
1351 (pres->end - offset) >= 0xbffff)
1356 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1357 BUG_ON(res == NULL);
1358 res->name = "Legacy VGA memory";
1359 res->flags = IORESOURCE_MEM;
1360 res->start = 0xa0000 + offset;
1361 res->end = 0xbffff + offset;
1362 pr_debug("Candidate VGA memory: %pR\n", res);
1363 if (request_resource(pres, res)) {
1365 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1366 pci_domain_nr(bus), bus->number, res);
1371 void __init pcibios_resource_survey(void)
1375 /* Allocate and assign resources */
1376 list_for_each_entry(b, &pci_root_buses, node)
1377 pcibios_allocate_bus_resources(b);
1378 pcibios_allocate_resources(0);
1379 pcibios_allocate_resources(1);
1381 /* Before we start assigning unassigned resource, we try to reserve
1382 * the low IO area and the VGA memory area if they intersect the
1383 * bus available resources to avoid allocating things on top of them
1385 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1386 list_for_each_entry(b, &pci_root_buses, node)
1387 pcibios_reserve_legacy_regions(b);
1390 /* Now, if the platform didn't decide to blindly trust the firmware,
1391 * we proceed to assigning things that were left unassigned
1393 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1394 pr_debug("PCI: Assigning unassigned resources...\n");
1395 pci_assign_unassigned_resources();
1398 /* Call machine dependent fixup */
1399 if (ppc_md.pcibios_fixup)
1400 ppc_md.pcibios_fixup();
1403 /* This is used by the PCI hotplug driver to allocate resource
1404 * of newly plugged busses. We can try to consolidate with the
1405 * rest of the code later, for now, keep it as-is as our main
1406 * resource allocation function doesn't deal with sub-trees yet.
1408 void pcibios_claim_one_bus(struct pci_bus *bus)
1410 struct pci_dev *dev;
1411 struct pci_bus *child_bus;
1413 list_for_each_entry(dev, &bus->devices, bus_list) {
1416 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1417 struct resource *r = &dev->resource[i];
1419 if (r->parent || !r->start || !r->flags)
1422 pr_debug("PCI: Claiming %s: "
1423 "Resource %d: %016llx..%016llx [%x]\n",
1425 (unsigned long long)r->start,
1426 (unsigned long long)r->end,
1427 (unsigned int)r->flags);
1429 pci_claim_resource(dev, i);
1433 list_for_each_entry(child_bus, &bus->children, node)
1434 pcibios_claim_one_bus(child_bus);
1438 /* pcibios_finish_adding_to_bus
1440 * This is to be called by the hotplug code after devices have been
1441 * added to a bus, this include calling it for a PHB that is just
1444 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1446 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1447 pci_domain_nr(bus), bus->number);
1449 /* Allocate bus and devices resources */
1450 pcibios_allocate_bus_resources(bus);
1451 pcibios_claim_one_bus(bus);
1454 eeh_add_device_tree_late(bus);
1456 /* Add new devices to global lists. Register in proc, sysfs. */
1457 pci_bus_add_devices(bus);
1459 /* sysfs files should only be added after devices are added */
1460 eeh_add_sysfs_files(bus);
1462 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1464 int pcibios_enable_device(struct pci_dev *dev, int mask)
1466 if (ppc_md.pcibios_enable_device_hook)
1467 if (ppc_md.pcibios_enable_device_hook(dev))
1470 /* avoid pcie irq fix up impact on cardbus */
1471 if (dev->hdr_type != PCI_HEADER_TYPE_CARDBUS)
1472 pcibios_setup_device(dev);
1474 return pci_enable_resources(dev, mask);
1477 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1479 return (unsigned long) hose->io_base_virt - _IO_BASE;
1482 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1483 struct list_head *resources)
1485 struct resource *res;
1486 resource_size_t offset;
1489 /* Hookup PHB IO resource */
1490 res = &hose->io_resource;
1493 printk(KERN_WARNING "PCI: I/O resource not set for host"
1494 " bridge %s (domain %d)\n",
1495 hose->dn->full_name, hose->global_number);
1497 offset = pcibios_io_space_offset(hose);
1499 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n",
1500 (unsigned long long)res->start,
1501 (unsigned long long)res->end,
1502 (unsigned long)res->flags,
1503 (unsigned long long)offset);
1504 pci_add_resource_offset(resources, res, offset);
1507 /* Hookup PHB Memory resources */
1508 for (i = 0; i < 3; ++i) {
1509 res = &hose->mem_resources[i];
1512 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1513 "host bridge %s (domain %d)\n",
1514 hose->dn->full_name, hose->global_number);
1517 offset = hose->mem_offset[i];
1520 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
1521 (unsigned long long)res->start,
1522 (unsigned long long)res->end,
1523 (unsigned long)res->flags,
1524 (unsigned long long)offset);
1526 pci_add_resource_offset(resources, res, offset);
1531 * Null PCI config access functions, for the case when we can't
1534 #define NULL_PCI_OP(rw, size, type) \
1536 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1538 return PCIBIOS_DEVICE_NOT_FOUND; \
1542 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1545 return PCIBIOS_DEVICE_NOT_FOUND;
1549 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1552 return PCIBIOS_DEVICE_NOT_FOUND;
1555 static struct pci_ops null_pci_ops =
1557 .read = null_read_config,
1558 .write = null_write_config,
1562 * These functions are used early on before PCI scanning is done
1563 * and all of the pci_dev and pci_bus structures have been created.
1565 static struct pci_bus *
1566 fake_pci_bus(struct pci_controller *hose, int busnr)
1568 static struct pci_bus bus;
1571 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1575 bus.ops = hose? hose->ops: &null_pci_ops;
1579 #define EARLY_PCI_OP(rw, size, type) \
1580 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1581 int devfn, int offset, type value) \
1583 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1584 devfn, offset, value); \
1587 EARLY_PCI_OP(read, byte, u8 *)
1588 EARLY_PCI_OP(read, word, u16 *)
1589 EARLY_PCI_OP(read, dword, u32 *)
1590 EARLY_PCI_OP(write, byte, u8)
1591 EARLY_PCI_OP(write, word, u16)
1592 EARLY_PCI_OP(write, dword, u32)
1594 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1595 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1598 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1601 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1603 struct pci_controller *hose = bus->sysdata;
1605 return of_node_get(hose->dn);
1609 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1610 * @hose: Pointer to the PCI host controller instance structure
1612 void pcibios_scan_phb(struct pci_controller *hose)
1614 LIST_HEAD(resources);
1615 struct pci_bus *bus;
1616 struct device_node *node = hose->dn;
1619 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1621 /* Get some IO space for the new PHB */
1622 pcibios_setup_phb_io_space(hose);
1624 /* Wire up PHB bus resources */
1625 pcibios_setup_phb_resources(hose, &resources);
1627 hose->busn.start = hose->first_busno;
1628 hose->busn.end = hose->last_busno;
1629 hose->busn.flags = IORESOURCE_BUS;
1630 pci_add_resource(&resources, &hose->busn);
1632 /* Create an empty bus for the toplevel */
1633 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1634 hose->ops, hose, &resources);
1636 pr_err("Failed to create bus for PCI domain %04x\n",
1637 hose->global_number);
1638 pci_free_resource_list(&resources);
1643 /* Get probe mode and perform scan */
1644 mode = PCI_PROBE_NORMAL;
1645 if (node && ppc_md.pci_probe_mode)
1646 mode = ppc_md.pci_probe_mode(bus);
1647 pr_debug(" probe mode: %d\n", mode);
1648 if (mode == PCI_PROBE_DEVTREE)
1649 of_scan_bus(node, bus);
1651 if (mode == PCI_PROBE_NORMAL) {
1652 pci_bus_update_busn_res_end(bus, 255);
1653 hose->last_busno = pci_scan_child_bus(bus);
1654 pci_bus_update_busn_res_end(bus, hose->last_busno);
1657 /* Platform gets a chance to do some global fixups before
1658 * we proceed to resource allocation
1660 if (ppc_md.pcibios_fixup_phb)
1661 ppc_md.pcibios_fixup_phb(hose);
1663 /* Configure PCI Express settings */
1664 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1665 struct pci_bus *child;
1666 list_for_each_entry(child, &bus->children, node) {
1667 struct pci_dev *self = child->self;
1670 pcie_bus_configure_settings(child, self->pcie_mpss);
1675 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1677 int i, class = dev->class >> 8;
1678 /* When configured as agent, programing interface = 1 */
1679 int prog_if = dev->class & 0xf;
1681 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1682 class == PCI_CLASS_BRIDGE_OTHER) &&
1683 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1685 (dev->bus->parent == NULL)) {
1686 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1687 dev->resource[i].start = 0;
1688 dev->resource[i].end = 0;
1689 dev->resource[i].flags = 0;
1693 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1694 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1696 static void fixup_vga(struct pci_dev *pdev)
1700 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1701 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1702 vga_set_default_device(pdev);
1705 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1706 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);