2 * Transactional memory support routines to reclaim and recheckpoint
3 * transactional process state.
5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
8 #include <asm/asm-offsets.h>
9 #include <asm/ppc_asm.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/ptrace.h>
15 /* See fpu.S, this is very similar but to save/restore checkpointed FPRs/VSRs */
16 #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \
19 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
20 SAVE_32FPRS_TRANSACT(n,base); \
22 2: SAVE_32VSRS_TRANSACT(n,c,base); \
24 /* ...and this is just plain borrowed from there. */
25 #define __REST_32FPRS_VSRS(n,c,base) \
28 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
29 REST_32FPRS(n,base); \
31 2: REST_32VSRS(n,c,base); \
34 #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) SAVE_32FPRS_TRANSACT(n, base)
35 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
37 #define SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \
38 __SAVE_32FPRS_VSRS_TRANSACT(n,__REG_##c,__REG_##base)
39 #define REST_32FPRS_VSRS(n,c,base) \
40 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42 /* Stack frame offsets for local variables. */
43 #define TM_FRAME_L0 TM_FRAME_SIZE-16
44 #define TM_FRAME_L1 TM_FRAME_SIZE-8
45 #define STACK_PARAM(x) (48+((x)*8))
48 /* In order to access the TM SPRs, TM must be enabled. So, do so: */
61 std r0, THREAD_TM_TFHAR(r3)
63 std r0, THREAD_TM_TEXASR(r3)
65 std r0, THREAD_TM_TFIAR(r3)
68 _GLOBAL(tm_restore_sprs)
69 ld r0, THREAD_TM_TFHAR(r3)
71 ld r0, THREAD_TM_TEXASR(r3)
73 ld r0, THREAD_TM_TFIAR(r3)
77 /* Passed an 8-bit failure cause as first argument. */
83 /* void tm_reclaim(struct thread_struct *thread,
84 * unsigned long orig_msr,
87 * - Performs a full reclaim. This destroys outstanding
88 * transactions and updates thread->regs.tm_ckpt_* with the
89 * original checkpointed state. Note that thread->regs is
91 * - FP regs are written back to thread->transact_fpr before
92 * reclaiming. These are the transactional (current) versions.
94 * Purpose is to both abort transactions of, and preserve the state of,
95 * a transactions at a context switch. We preserve/restore both sets of process
96 * state to restore them when the thread's scheduled again. We continue in
97 * userland as though nothing happened, but when the transaction is resumed
98 * they will abort back to the checkpointed state we save out here.
100 * Call with IRQs off, stacks get all out of sync for some periods in here!
108 stdu r1, -TM_FRAME_SIZE(r1)
110 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
112 std r3, STACK_PARAM(0)(r1)
118 oris r15, r15, MSR_VEC@h
121 oris r15,r15, MSR_VSX@h
122 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
125 std r14, TM_FRAME_L0(r1)
127 /* Stash the stack pointer away for use after reclaim */
130 /* ******************** FPR/VR/VSRs ************
131 * Before reclaiming, capture the current/transactional FPR/VR
132 * versions /if used/.
134 * (If VSX used, FP and VMX are implied. Or, we don't need to look
135 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
137 * We're passed the thread's MSR as parameter 2.
139 * We enabled VEC/FP/VSX in the msr above, so we can execute these
142 andis. r0, r4, MSR_VEC@h
145 SAVE_32VRS_TRANSACT(0, r6, r3) /* r6 scratch, r3 thread */
147 li r6, THREAD_TRANSACT_VSCR
149 mfspr r0, SPRN_VRSAVE
150 std r0, THREAD_TRANSACT_VRSAVE(r3)
156 SAVE_32FPRS_VSRS_TRANSACT(0, R6, R3) /* r6 scratch, r3 thread */
159 stfd fr0,THREAD_TRANSACT_FPSCR(r3)
162 /* The moment we treclaim, ALL of our GPRs will switch
163 * to user register state. (FPRs, CCR etc. also!)
164 * Use an sprg and a tm_scratch in the PACA to shuffle.
166 TRECLAIM(R5) /* Cause in r5 */
168 /* ******************** GPRs ******************** */
169 /* Stash the checkpointed r13 away in the scratch SPR and get the real
175 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
178 std r1, PACATMSCRATCH(r13)
181 /* Now get some more GPRS free */
182 std r7, GPR7(r1) /* Temporary stash */
183 std r12, GPR12(r1) /* '' '' '' */
184 ld r12, STACK_PARAM(0)(r1) /* Param 0, thread_struct * */
186 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
188 /* Make r7 look like an exception frame so that we
189 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
191 subi r7, r7, STACK_FRAME_OVERHEAD
193 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
194 SAVE_GPR(0, r7) /* user r0 */
195 SAVE_GPR(2, r7) /* user r2 */
196 SAVE_4GPRS(3, r7) /* user r3-r6 */
197 SAVE_4GPRS(8, r7) /* user r8-r11 */
198 ld r3, PACATMSCRATCH(r13) /* user r1 */
199 ld r4, GPR7(r1) /* user r7 */
200 ld r5, GPR12(r1) /* user r12 */
201 GET_SCRATCH0(6) /* user r13 */
207 SAVE_NVGPRS(r7) /* user r14-r31 */
209 /* ******************** NIP ******************** */
211 std r3, _NIP(r7) /* Returns to failhandler */
212 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
213 * but is used in signal return to 'wind back' to the abort handler.
216 /* ******************** CR,LR,CCR,MSR ********** */
228 /* ******************** TAR, PPR, DSCR ********** */
233 std r3, THREAD_TM_TAR(r12)
234 std r4, THREAD_TM_PPR(r12)
235 std r5, THREAD_TM_DSCR(r12)
237 /* MSR and flags: We don't change CRs, and we don't need to alter
241 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
242 * been updated by the treclaim, to explain to userland the failure
245 mfspr r0, SPRN_TEXASR
248 std r0, THREAD_TM_TEXASR(r12)
249 std r3, THREAD_TM_TFHAR(r12)
250 std r4, THREAD_TM_TFIAR(r12)
252 /* AMR and PPR are checkpointed too, but are unsupported by Linux. */
254 /* Restore original MSR/IRQ state & clear TM mode */
255 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
257 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
262 addi r1, r1, TM_FRAME_SIZE
271 /* void tm_recheckpoint(struct thread_struct *thread,
272 * unsigned long orig_msr)
273 * - Restore the checkpointed register state saved by tm_reclaim
274 * when we switch_to a process.
276 * Call with IRQs off, stacks get all out of sync for
277 * some periods in here!
279 _GLOBAL(tm_recheckpoint)
285 stdu r1, -TM_FRAME_SIZE(r1)
287 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
288 * This is used for backing up the NVGPRs:
294 /* Load complete register state from ts_ckpt* registers */
296 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
298 /* Make r7 look like an exception frame so that we
299 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
301 subi r7, r7, STACK_FRAME_OVERHEAD
306 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
308 /* Enable FP/vec in MSR if necessary! */
312 beq restore_gprs /* if neither, skip both */
316 oris r5, r5, MSR_VSX@h
317 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
319 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
322 #ifdef CONFIG_ALTIVEC
323 /* FP and VEC registers: These are recheckpointed from thread.fpr[]
324 * and thread.vr[] respectively. The thread.transact_fpr[] version
325 * is more modern, and will be loaded subsequently by any FPUnavailable
328 andis. r0, r4, MSR_VEC@h
334 REST_32VRS(0, r5, r3) /* r5 scratch, r3 THREAD ptr */
335 ld r5, THREAD_VRSAVE(r3)
336 mtspr SPRN_VRSAVE, r5
343 lfd fr0, THREAD_FPSCR(r3)
345 REST_32FPRS_VSRS(0, R4, R3)
348 mtmsr r6 /* FP/Vec off again! */
352 /* ******************** TAR, PPR, DSCR ********** */
353 ld r4, THREAD_TM_TAR(r3)
354 ld r5, THREAD_TM_PPR(r3)
355 ld r6, THREAD_TM_DSCR(r3)
361 /* ******************** CR,LR,CCR,MSR ********** */
372 /* MSR and flags: We don't change CRs, and we don't need to alter
376 REST_4GPRS(0, r7) /* GPR0-3 */
377 REST_GPR(4, r7) /* GPR4-6 */
380 REST_4GPRS(8, r7) /* GPR8-11 */
381 REST_2GPRS(12, r7) /* GPR12-13 */
383 REST_NVGPRS(r7) /* GPR14-31 */
385 ld r7, GPR7(r7) /* GPR7 */
387 /* Commit register state as checkpointed state: */
390 /* Our transactional state has now changed.
392 * Now just get out of here. Transactional (current) state will be
393 * updated once restore is called on the return path in the _switch-ed
402 addi r1, r1, TM_FRAME_SIZE
410 /* ****************************************************************** */