2 * Transactional memory support routines to reclaim and recheckpoint
3 * transactional process state.
5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
8 #include <asm/asm-offsets.h>
9 #include <asm/ppc_asm.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/ptrace.h>
15 /* See fpu.S, this is very similar but to save/restore checkpointed FPRs/VSRs */
16 #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \
19 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
20 SAVE_32FPRS_TRANSACT(n,base); \
22 2: SAVE_32VSRS_TRANSACT(n,c,base); \
24 /* ...and this is just plain borrowed from there. */
25 #define __REST_32FPRS_VSRS(n,c,base) \
28 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
29 REST_32FPRS(n,base); \
31 2: REST_32VSRS(n,c,base); \
34 #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) SAVE_32FPRS_TRANSACT(n, base)
35 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
37 #define SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \
38 __SAVE_32FPRS_VSRS_TRANSACT(n,__REG_##c,__REG_##base)
39 #define REST_32FPRS_VSRS(n,c,base) \
40 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42 /* Stack frame offsets for local variables. */
43 #define TM_FRAME_L0 TM_FRAME_SIZE-16
44 #define TM_FRAME_L1 TM_FRAME_SIZE-8
45 #define STACK_PARAM(x) (48+((x)*8))
48 /* In order to access the TM SPRs, TM must be enabled. So, do so: */
61 std r0, THREAD_TM_TFHAR(r3)
63 std r0, THREAD_TM_TEXASR(r3)
65 std r0, THREAD_TM_TFIAR(r3)
68 _GLOBAL(tm_restore_sprs)
69 ld r0, THREAD_TM_TFHAR(r3)
71 ld r0, THREAD_TM_TEXASR(r3)
73 ld r0, THREAD_TM_TFIAR(r3)
77 /* Passed an 8-bit failure cause as first argument. */
84 .tc dscr_default[TC],dscr_default
88 /* void tm_reclaim(struct thread_struct *thread,
89 * unsigned long orig_msr,
92 * - Performs a full reclaim. This destroys outstanding
93 * transactions and updates thread->regs.tm_ckpt_* with the
94 * original checkpointed state. Note that thread->regs is
96 * - FP regs are written back to thread->transact_fpr before
97 * reclaiming. These are the transactional (current) versions.
99 * Purpose is to both abort transactions of, and preserve the state of,
100 * a transactions at a context switch. We preserve/restore both sets of process
101 * state to restore them when the thread's scheduled again. We continue in
102 * userland as though nothing happened, but when the transaction is resumed
103 * they will abort back to the checkpointed state we save out here.
105 * Call with IRQs off, stacks get all out of sync for some periods in here!
113 stdu r1, -TM_FRAME_SIZE(r1)
115 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
117 std r3, STACK_PARAM(0)(r1)
123 oris r15, r15, MSR_VEC@h
126 oris r15,r15, MSR_VSX@h
127 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
130 std r14, TM_FRAME_L0(r1)
132 /* Stash the stack pointer away for use after reclaim */
135 /* ******************** FPR/VR/VSRs ************
136 * Before reclaiming, capture the current/transactional FPR/VR
137 * versions /if used/.
139 * (If VSX used, FP and VMX are implied. Or, we don't need to look
140 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
142 * We're passed the thread's MSR as parameter 2.
144 * We enabled VEC/FP/VSX in the msr above, so we can execute these
147 andis. r0, r4, MSR_VEC@h
150 SAVE_32VRS_TRANSACT(0, r6, r3) /* r6 scratch, r3 thread */
152 li r6, THREAD_TRANSACT_VSCR
154 mfspr r0, SPRN_VRSAVE
155 std r0, THREAD_TRANSACT_VRSAVE(r3)
161 SAVE_32FPRS_VSRS_TRANSACT(0, R6, R3) /* r6 scratch, r3 thread */
164 stfd fr0,THREAD_TRANSACT_FPSCR(r3)
167 /* The moment we treclaim, ALL of our GPRs will switch
168 * to user register state. (FPRs, CCR etc. also!)
169 * Use an sprg and a tm_scratch in the PACA to shuffle.
171 TRECLAIM(R5) /* Cause in r5 */
173 /* ******************** GPRs ******************** */
174 /* Stash the checkpointed r13 away in the scratch SPR and get the real
180 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
183 std r1, PACATMSCRATCH(r13)
186 /* Store the PPR in r11 and reset to decent value */
187 std r11, GPR11(r1) /* Temporary stash */
191 /* Now get some more GPRS free */
192 std r7, GPR7(r1) /* Temporary stash */
193 std r12, GPR12(r1) /* '' '' '' */
194 ld r12, STACK_PARAM(0)(r1) /* Param 0, thread_struct * */
196 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
198 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
200 /* Make r7 look like an exception frame so that we
201 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
203 subi r7, r7, STACK_FRAME_OVERHEAD
205 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
206 SAVE_GPR(0, r7) /* user r0 */
207 SAVE_GPR(2, r7) /* user r2 */
208 SAVE_4GPRS(3, r7) /* user r3-r6 */
209 SAVE_GPR(8, r7) /* user r8 */
210 SAVE_GPR(9, r7) /* user r9 */
211 SAVE_GPR(10, r7) /* user r10 */
212 ld r3, PACATMSCRATCH(r13) /* user r1 */
213 ld r4, GPR7(r1) /* user r7 */
214 ld r5, GPR11(r1) /* user r11 */
215 ld r6, GPR12(r1) /* user r12 */
216 GET_SCRATCH0(8) /* user r13 */
223 SAVE_NVGPRS(r7) /* user r14-r31 */
225 /* ******************** NIP ******************** */
227 std r3, _NIP(r7) /* Returns to failhandler */
228 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
229 * but is used in signal return to 'wind back' to the abort handler.
232 /* ******************** CR,LR,CCR,MSR ********** */
244 /* ******************** TAR, DSCR ********** */
248 std r3, THREAD_TM_TAR(r12)
249 std r4, THREAD_TM_DSCR(r12)
251 /* MSR and flags: We don't change CRs, and we don't need to alter
255 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
256 * been updated by the treclaim, to explain to userland the failure
259 mfspr r0, SPRN_TEXASR
262 std r0, THREAD_TM_TEXASR(r12)
263 std r3, THREAD_TM_TFHAR(r12)
264 std r4, THREAD_TM_TFIAR(r12)
266 /* AMR is checkpointed too, but is unsupported by Linux. */
268 /* Restore original MSR/IRQ state & clear TM mode */
269 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
271 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
276 addi r1, r1, TM_FRAME_SIZE
283 /* Load system default DSCR */
284 ld r4, DSCR_DEFAULT@toc(r2)
291 /* void tm_recheckpoint(struct thread_struct *thread,
292 * unsigned long orig_msr)
293 * - Restore the checkpointed register state saved by tm_reclaim
294 * when we switch_to a process.
296 * Call with IRQs off, stacks get all out of sync for
297 * some periods in here!
299 _GLOBAL(tm_recheckpoint)
305 stdu r1, -TM_FRAME_SIZE(r1)
307 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
308 * This is used for backing up the NVGPRs:
314 /* Load complete register state from ts_ckpt* registers */
316 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
318 /* Make r7 look like an exception frame so that we
319 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
321 subi r7, r7, STACK_FRAME_OVERHEAD
326 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
328 /* Enable FP/vec in MSR if necessary! */
332 beq restore_gprs /* if neither, skip both */
336 oris r5, r5, MSR_VSX@h
337 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
339 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
342 #ifdef CONFIG_ALTIVEC
343 /* FP and VEC registers: These are recheckpointed from thread.fpr[]
344 * and thread.vr[] respectively. The thread.transact_fpr[] version
345 * is more modern, and will be loaded subsequently by any FPUnavailable
348 andis. r0, r4, MSR_VEC@h
354 REST_32VRS(0, r5, r3) /* r5 scratch, r3 THREAD ptr */
355 ld r5, THREAD_VRSAVE(r3)
356 mtspr SPRN_VRSAVE, r5
363 lfd fr0, THREAD_FPSCR(r3)
365 REST_32FPRS_VSRS(0, R4, R3)
368 mtmsr r6 /* FP/Vec off again! */
372 /* ******************** CR,LR,CCR,MSR ********** */
383 /* ******************** TAR ******************** */
384 ld r4, THREAD_TM_TAR(r3)
387 /* Load up the PPR and DSCR in GPRs only at this stage */
388 ld r5, THREAD_TM_DSCR(r3)
389 ld r6, THREAD_TM_PPR(r3)
391 /* MSR and flags: We don't change CRs, and we don't need to alter
395 REST_4GPRS(0, r7) /* GPR0-3 */
396 REST_GPR(4, r7) /* GPR4 */
397 REST_4GPRS(8, r7) /* GPR8-11 */
398 REST_2GPRS(12, r7) /* GPR12-13 */
400 REST_NVGPRS(r7) /* GPR14-31 */
402 /* Load up PPR and DSCR here so we don't run with user values for long
407 REST_GPR(5, r7) /* GPR5-7 */
411 /* Commit register state as checkpointed state: */
416 /* Our transactional state has now changed.
418 * Now just get out of here. Transactional (current) state will be
419 * updated once restore is called on the return path in the _switch-ed
428 addi r1, r1, TM_FRAME_SIZE
435 /* Load system default DSCR */
436 ld r4, DSCR_DEFAULT@toc(r2)
442 /* ****************************************************************** */