2 * Memory copy functions for 32-bit PowerPC.
4 * Copyright (C) 1996-2005 Paul Mackerras.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/errno.h>
14 #include <asm/ppc_asm.h>
16 #define COPY_16_BYTES \
26 #define COPY_16_BYTES_WITHEX(n) \
44 #define COPY_16_BYTES_EXCODE(n) \
46 addi r5,r5,-(16 * n); \
49 addi r5,r5,-(16 * n); \
51 .section __ex_table,"a"; \
53 .long 8 ## n ## 0b,9 ## n ## 0b; \
54 .long 8 ## n ## 1b,9 ## n ## 0b; \
55 .long 8 ## n ## 2b,9 ## n ## 0b; \
56 .long 8 ## n ## 3b,9 ## n ## 0b; \
57 .long 8 ## n ## 4b,9 ## n ## 1b; \
58 .long 8 ## n ## 5b,9 ## n ## 1b; \
59 .long 8 ## n ## 6b,9 ## n ## 1b; \
60 .long 8 ## n ## 7b,9 ## n ## 1b; \
64 .stabs "arch/powerpc/lib/",N_SO,0,0,0f
65 .stabs "copy_32.S",N_SO,0,0,0f
68 CACHELINE_BYTES = L1_CACHE_BYTES
69 LG_CACHELINE_BYTES = L1_CACHE_SHIFT
70 CACHELINE_MASK = (L1_CACHE_BYTES-1)
73 * Use dcbz on the complete cache lines in the destination
74 * to set them to zero. This requires that the destination
75 * area is cacheable. -- paulus
90 bne 2f /* Use normal procedure if r4 is not zero */
92 clrlwi r7,r6,32-LG_CACHELINE_BYTES
94 srwi r9,r8,LG_CACHELINE_BYTES
95 addic. r9,r9,-1 /* total number of complete cachelines */
97 xori r0,r7,CACHELINE_MASK & ~3
106 addi r6,r6,CACHELINE_BYTES
108 clrlwi r5,r8,32-LG_CACHELINE_BYTES
126 * This version uses dcbz on the complete cache lines in the
127 * destination area to reduce memory traffic. This requires that
128 * the destination area is cacheable.
129 * We only use this version if the source and dest don't overlap.
132 * During early init, cache might not be active yet, so dcbz cannot be used.
133 * We therefore jump to generic_memcpy which doesn't use dcbz. This jump is
134 * replaced by a nop once cache is active. This is done in machine_init()
143 add r7,r3,r5 /* test if the src & dst overlap */
147 crand 0,0,4 /* cr0.lt &= cr1.lt */
148 blt generic_memcpy /* if regions overlap */
153 andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
156 cmplw 0,r5,r0 /* is this more than total to do? */
157 blt 63f /* if not much to do */
158 andi. r8,r0,3 /* get it word-aligned first */
162 70: lbz r9,4(r4) /* do some bytes */
170 72: lwzu r9,4(r4) /* do some words */
174 58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
175 clrlwi r5,r5,32-LG_CACHELINE_BYTES
182 #if L1_CACHE_BYTES >= 32
184 #if L1_CACHE_BYTES >= 64
187 #if L1_CACHE_BYTES >= 128
214 _GLOBAL(generic_memcpy)
218 beq 2f /* if less than 8 bytes to do */
219 andi. r0,r6,3 /* get dest word aligned */
250 rlwinm. r7,r5,32-3,3,31
255 _GLOBAL(backwards_memcpy)
256 rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
286 rlwinm. r7,r5,32-3,3,31
291 _GLOBAL(__copy_tofrom_user)
295 andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
298 cmplw 0,r5,r0 /* is this more than total to do? */
299 blt 63f /* if not much to do */
300 andi. r8,r0,3 /* get it word-aligned first */
303 70: lbz r9,4(r4) /* do some bytes */
312 72: lwzu r9,4(r4) /* do some words */
316 .section __ex_table,"a"
324 58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
325 clrlwi r5,r5,32-LG_CACHELINE_BYTES
329 /* Here we decide how far ahead to prefetch the source */
335 #if MAX_COPY_PREFETCH > 1
336 /* Heuristically, for large transfers we prefetch
337 MAX_COPY_PREFETCH cachelines ahead. For small transfers
338 we prefetch 1 cacheline ahead. */
339 cmpwi r0,MAX_COPY_PREFETCH
341 li r7,MAX_COPY_PREFETCH
344 addi r3,r3,CACHELINE_BYTES
348 addi r3,r3,CACHELINE_BYTES
349 #endif /* MAX_COPY_PREFETCH > 1 */
357 .section __ex_table,"a"
361 /* the main body of the cacheline loop */
362 COPY_16_BYTES_WITHEX(0)
363 #if L1_CACHE_BYTES >= 32
364 COPY_16_BYTES_WITHEX(1)
365 #if L1_CACHE_BYTES >= 64
366 COPY_16_BYTES_WITHEX(2)
367 COPY_16_BYTES_WITHEX(3)
368 #if L1_CACHE_BYTES >= 128
369 COPY_16_BYTES_WITHEX(4)
370 COPY_16_BYTES_WITHEX(5)
371 COPY_16_BYTES_WITHEX(6)
372 COPY_16_BYTES_WITHEX(7)
400 /* read fault, initial single-byte copy */
403 /* write fault, initial single-byte copy */
408 /* read fault, initial word copy */
411 /* write fault, initial word copy */
417 * this stuff handles faults in the cacheline loop and branches to either
418 * 104f (if in read part) or 105f (if in write part), after updating r5
420 COPY_16_BYTES_EXCODE(0)
421 #if L1_CACHE_BYTES >= 32
422 COPY_16_BYTES_EXCODE(1)
423 #if L1_CACHE_BYTES >= 64
424 COPY_16_BYTES_EXCODE(2)
425 COPY_16_BYTES_EXCODE(3)
426 #if L1_CACHE_BYTES >= 128
427 COPY_16_BYTES_EXCODE(4)
428 COPY_16_BYTES_EXCODE(5)
429 COPY_16_BYTES_EXCODE(6)
430 COPY_16_BYTES_EXCODE(7)
435 /* read fault in cacheline loop */
438 /* fault on dcbz (effectively a write fault) */
439 /* or write fault in cacheline loop */
441 92: li r3,LG_CACHELINE_BYTES
445 /* read fault in final word loop */
448 /* write fault in final word loop */
453 /* read fault in final byte loop */
456 /* write fault in final byte loop */
461 * At this stage the number of bytes not copied is
462 * r5 + (ctr << r3), and r9 is 0 for read or 1 for write.
467 beq 120f /* shouldn't happen */
470 /* for a read fault, first try to continue the copy one byte at a time */
477 /* then clear out the destination: r3 bytes starting at 4(r6) */
493 .section __ex_table,"a"