2 * arch/powerpc/math-emu/math_efp.c
4 * Copyright (C) 2006-2008, 2010 Freescale Semiconductor, Inc.
6 * Author: Ebony Zhu, <ebony.zhu@freescale.com>
7 * Yu Liu, <yu.liu@freescale.com>
9 * Derived from arch/alpha/math-emu/math.c
10 * arch/powerpc/math-emu/math.c
13 * This file is the exception handler to make E500 SPE instructions
14 * fully comply with IEEE-754 floating point standard.
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * as published by the Free Software Foundation; either version
19 * 2 of the License, or (at your option) any later version.
22 #include <linux/types.h>
24 #include <asm/uaccess.h>
27 #define FP_EX_BOOKE_E500_SPE
28 #include <asm/sfp-machine.h>
30 #include <math-emu/soft-fp.h>
31 #include <math-emu/single.h>
32 #include <math-emu/double.h>
47 #define EFSCMPGT 0x2cc
48 #define EFSCMPLT 0x2cd
49 #define EFSCMPEQ 0x2ce
56 #define EFSCTUIZ 0x2d8
57 #define EFSCTSIZ 0x2da
62 #define EVFSNABS 0x285
66 #define EVFSCMPGT 0x28c
67 #define EVFSCMPLT 0x28d
68 #define EVFSCMPEQ 0x28e
69 #define EVFSCTUI 0x294
70 #define EVFSCTSI 0x295
71 #define EVFSCTUF 0x296
72 #define EVFSCTSF 0x297
73 #define EVFSCTUIZ 0x298
74 #define EVFSCTSIZ 0x29a
83 #define EFDCTUIDZ 0x2ea
84 #define EFDCTSIDZ 0x2eb
85 #define EFDCMPGT 0x2ec
86 #define EFDCMPLT 0x2ed
87 #define EFDCMPEQ 0x2ee
93 #define EFDCTUIZ 0x2f8
94 #define EFDCTSIZ 0x2fa
102 #define SIGN_BIT_S (1UL << 31)
103 #define SIGN_BIT_D (1ULL << 63)
104 #define FP_EX_MASK (FP_EX_INEXACT | FP_EX_INVALID | FP_EX_DIVZERO | \
105 FP_EX_UNDERFLOW | FP_EX_OVERFLOW)
107 static int have_e500_cpu_a005_erratum;
114 static unsigned long insn_type(unsigned long speinsn)
116 unsigned long ret = NOTYPE;
118 switch (speinsn & 0x7ff) {
119 case EFSABS: ret = XA; break;
120 case EFSADD: ret = AB; break;
121 case EFSCFD: ret = XB; break;
122 case EFSCMPEQ: ret = XCR; break;
123 case EFSCMPGT: ret = XCR; break;
124 case EFSCMPLT: ret = XCR; break;
125 case EFSCTSF: ret = XB; break;
126 case EFSCTSI: ret = XB; break;
127 case EFSCTSIZ: ret = XB; break;
128 case EFSCTUF: ret = XB; break;
129 case EFSCTUI: ret = XB; break;
130 case EFSCTUIZ: ret = XB; break;
131 case EFSDIV: ret = AB; break;
132 case EFSMUL: ret = AB; break;
133 case EFSNABS: ret = XA; break;
134 case EFSNEG: ret = XA; break;
135 case EFSSUB: ret = AB; break;
136 case EFSCFSI: ret = XB; break;
138 case EVFSABS: ret = XA; break;
139 case EVFSADD: ret = AB; break;
140 case EVFSCMPEQ: ret = XCR; break;
141 case EVFSCMPGT: ret = XCR; break;
142 case EVFSCMPLT: ret = XCR; break;
143 case EVFSCTSF: ret = XB; break;
144 case EVFSCTSI: ret = XB; break;
145 case EVFSCTSIZ: ret = XB; break;
146 case EVFSCTUF: ret = XB; break;
147 case EVFSCTUI: ret = XB; break;
148 case EVFSCTUIZ: ret = XB; break;
149 case EVFSDIV: ret = AB; break;
150 case EVFSMUL: ret = AB; break;
151 case EVFSNABS: ret = XA; break;
152 case EVFSNEG: ret = XA; break;
153 case EVFSSUB: ret = AB; break;
155 case EFDABS: ret = XA; break;
156 case EFDADD: ret = AB; break;
157 case EFDCFS: ret = XB; break;
158 case EFDCMPEQ: ret = XCR; break;
159 case EFDCMPGT: ret = XCR; break;
160 case EFDCMPLT: ret = XCR; break;
161 case EFDCTSF: ret = XB; break;
162 case EFDCTSI: ret = XB; break;
163 case EFDCTSIDZ: ret = XB; break;
164 case EFDCTSIZ: ret = XB; break;
165 case EFDCTUF: ret = XB; break;
166 case EFDCTUI: ret = XB; break;
167 case EFDCTUIDZ: ret = XB; break;
168 case EFDCTUIZ: ret = XB; break;
169 case EFDDIV: ret = AB; break;
170 case EFDMUL: ret = AB; break;
171 case EFDNABS: ret = XA; break;
172 case EFDNEG: ret = XA; break;
173 case EFDSUB: ret = AB; break;
176 printk(KERN_ERR "\nOoops! SPE instruction no type found.");
177 printk(KERN_ERR "\ninst code: %08lx\n", speinsn);
183 int do_spe_mathemu(struct pt_regs *regs)
188 unsigned long type, func, fc, fa, fb, src, speinsn;
189 union dw_union vc, va, vb;
191 if (get_user(speinsn, (unsigned int __user *) regs->nip))
193 if ((speinsn >> 26) != EFAPU)
194 return -EINVAL; /* not an spe instruction */
196 type = insn_type(speinsn);
200 func = speinsn & 0x7ff;
201 fc = (speinsn >> 21) & 0x1f;
202 fa = (speinsn >> 16) & 0x1f;
203 fb = (speinsn >> 11) & 0x1f;
204 src = (speinsn >> 5) & 0x7;
206 vc.wp[0] = current->thread.evr[fc];
207 vc.wp[1] = regs->gpr[fc];
208 va.wp[0] = current->thread.evr[fa];
209 va.wp[1] = regs->gpr[fa];
210 vb.wp[0] = current->thread.evr[fb];
211 vb.wp[1] = regs->gpr[fb];
213 __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
216 printk("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
217 printk("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
218 printk("va: %08x %08x\n", va.wp[0], va.wp[1]);
219 printk("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
224 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
229 FP_UNPACK_SP(SA, va.wp + 1);
231 FP_UNPACK_SP(SB, vb.wp + 1);
234 FP_UNPACK_SP(SA, va.wp + 1);
239 printk("SA: %ld %08lx %ld (%ld)\n", SA_s, SA_f, SA_e, SA_c);
240 printk("SB: %ld %08lx %ld (%ld)\n", SB_s, SB_f, SB_e, SB_c);
245 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;
249 vc.wp[1] = va.wp[1] | SIGN_BIT_S;
253 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;
257 FP_ADD_S(SR, SA, SB);
261 FP_SUB_S(SR, SA, SB);
265 FP_MUL_S(SR, SA, SB);
269 FP_DIV_S(SR, SA, SB);
286 if (!((vb.wp[1] >> 23) == 0xff && ((vb.wp[1] & 0x7fffff) > 0))) {
288 if (((vb.wp[1] >> 23) & 0xff) == 0) {
291 } else if ((vb.wp[1] >> 31) == 0) {
292 /* positive normal */
293 vc.wp[1] = (func == EFSCTSF) ?
294 0x7fffffff : 0xffffffff;
295 } else { /* negative normal */
296 vc.wp[1] = (func == EFSCTSF) ?
299 } else { /* rB is NaN */
307 FP_UNPACK_DP(DB, vb.dp);
309 printk("DB: %ld %08lx %08lx %ld (%ld)\n",
310 DB_s, DB_f1, DB_f0, DB_e, DB_c);
312 FP_CONV(S, D, 1, 2, SR, DB);
323 _FP_ROUND_ZERO(1, SB);
325 FP_TO_INT_S(vc.wp[1], SB, 32,
326 (((func & 0x3) != 0) || SB_s));
336 printk("SR: %ld %08lx %ld (%ld)\n", SR_s, SR_f, SR_e, SR_c);
338 FP_PACK_SP(vc.wp + 1, SR);
342 FP_CMP_S(IR, SA, SB, 3);
343 if (IR == 3 && (FP_ISSIGNAN_S(SA) || FP_ISSIGNAN_S(SB)))
344 FP_SET_EXCEPTION(FP_EX_INVALID);
354 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
359 FP_UNPACK_DP(DA, va.dp);
361 FP_UNPACK_DP(DB, vb.dp);
364 FP_UNPACK_DP(DA, va.dp);
369 printk("DA: %ld %08lx %08lx %ld (%ld)\n",
370 DA_s, DA_f1, DA_f0, DA_e, DA_c);
371 printk("DB: %ld %08lx %08lx %ld (%ld)\n",
372 DB_s, DB_f1, DB_f0, DB_e, DB_c);
377 vc.dp[0] = va.dp[0] & ~SIGN_BIT_D;
381 vc.dp[0] = va.dp[0] | SIGN_BIT_D;
385 vc.dp[0] = va.dp[0] ^ SIGN_BIT_D;
389 FP_ADD_D(DR, DA, DB);
393 FP_SUB_D(DR, DA, DB);
397 FP_MUL_D(DR, DA, DB);
401 FP_DIV_D(DR, DA, DB);
418 if (!((vb.wp[0] >> 20) == 0x7ff &&
419 ((vb.wp[0] & 0xfffff) > 0 || (vb.wp[1] > 0)))) {
421 if (((vb.wp[0] >> 20) & 0x7ff) == 0) {
424 } else if ((vb.wp[0] >> 31) == 0) {
425 /* positive normal */
426 vc.wp[1] = (func == EFDCTSF) ?
427 0x7fffffff : 0xffffffff;
428 } else { /* negative normal */
429 vc.wp[1] = (func == EFDCTSF) ?
440 FP_UNPACK_SP(SB, vb.wp + 1);
442 printk("SB: %ld %08lx %ld (%ld)\n",
443 SB_s, SB_f, SB_e, SB_c);
445 FP_CONV(D, S, 2, 1, DR, SB);
451 _FP_ROUND_ZERO(2, DB);
452 FP_TO_INT_D(vc.dp[0], DB, 64, ((func & 0x1) == 0));
462 _FP_ROUND_ZERO(2, DB);
464 FP_TO_INT_D(vc.wp[1], DB, 32,
465 (((func & 0x3) != 0) || DB_s));
475 printk("DR: %ld %08lx %08lx %ld (%ld)\n",
476 DR_s, DR_f1, DR_f0, DR_e, DR_c);
478 FP_PACK_DP(vc.dp, DR);
482 FP_CMP_D(IR, DA, DB, 3);
483 if (IR == 3 && (FP_ISSIGNAN_D(DA) || FP_ISSIGNAN_D(DB)))
484 FP_SET_EXCEPTION(FP_EX_INVALID);
495 FP_DECL_S(SA0); FP_DECL_S(SB0); FP_DECL_S(SR0);
496 FP_DECL_S(SA1); FP_DECL_S(SB1); FP_DECL_S(SR1);
502 FP_UNPACK_SP(SA0, va.wp);
503 FP_UNPACK_SP(SA1, va.wp + 1);
505 FP_UNPACK_SP(SB0, vb.wp);
506 FP_UNPACK_SP(SB1, vb.wp + 1);
509 FP_UNPACK_SP(SA0, va.wp);
510 FP_UNPACK_SP(SA1, va.wp + 1);
515 printk("SA0: %ld %08lx %ld (%ld)\n", SA0_s, SA0_f, SA0_e, SA0_c);
516 printk("SA1: %ld %08lx %ld (%ld)\n", SA1_s, SA1_f, SA1_e, SA1_c);
517 printk("SB0: %ld %08lx %ld (%ld)\n", SB0_s, SB0_f, SB0_e, SB0_c);
518 printk("SB1: %ld %08lx %ld (%ld)\n", SB1_s, SB1_f, SB1_e, SB1_c);
523 vc.wp[0] = va.wp[0] & ~SIGN_BIT_S;
524 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;
528 vc.wp[0] = va.wp[0] | SIGN_BIT_S;
529 vc.wp[1] = va.wp[1] | SIGN_BIT_S;
533 vc.wp[0] = va.wp[0] ^ SIGN_BIT_S;
534 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;
538 FP_ADD_S(SR0, SA0, SB0);
539 FP_ADD_S(SR1, SA1, SB1);
543 FP_SUB_S(SR0, SA0, SB0);
544 FP_SUB_S(SR1, SA1, SB1);
548 FP_MUL_S(SR0, SA0, SB0);
549 FP_MUL_S(SR1, SA1, SB1);
553 FP_DIV_S(SR0, SA0, SB0);
554 FP_DIV_S(SR1, SA1, SB1);
570 __asm__ __volatile__ ("mtspr 512, %4\n"
573 : "=r" (vc.wp[0]), "=r" (vc.wp[1])
574 : "r" (vb.wp[0]), "r" (vb.wp[1]), "r" (0));
578 __asm__ __volatile__ ("mtspr 512, %4\n"
581 : "=r" (vc.wp[0]), "=r" (vc.wp[1])
582 : "r" (vb.wp[0]), "r" (vb.wp[1]), "r" (0));
593 _FP_ROUND_ZERO(1, SB0);
594 _FP_ROUND_ZERO(1, SB1);
596 FP_TO_INT_S(vc.wp[0], SB0, 32,
597 (((func & 0x3) != 0) || SB0_s));
598 FP_TO_INT_S(vc.wp[1], SB1, 32,
599 (((func & 0x3) != 0) || SB1_s));
609 printk("SR0: %ld %08lx %ld (%ld)\n", SR0_s, SR0_f, SR0_e, SR0_c);
610 printk("SR1: %ld %08lx %ld (%ld)\n", SR1_s, SR1_f, SR1_e, SR1_c);
612 FP_PACK_SP(vc.wp, SR0);
613 FP_PACK_SP(vc.wp + 1, SR1);
620 FP_CMP_S(IR0, SA0, SB0, 3);
621 FP_CMP_S(IR1, SA1, SB1, 3);
622 if (IR0 == 3 && (FP_ISSIGNAN_S(SA0) || FP_ISSIGNAN_S(SB0)))
623 FP_SET_EXCEPTION(FP_EX_INVALID);
624 if (IR1 == 3 && (FP_ISSIGNAN_S(SA1) || FP_ISSIGNAN_S(SB1)))
625 FP_SET_EXCEPTION(FP_EX_INVALID);
626 ch = (IR0 == cmp) ? 1 : 0;
627 cl = (IR1 == cmp) ? 1 : 0;
628 IR = (ch << 3) | (cl << 2) | ((ch | cl) << 1) |
638 regs->ccr &= ~(15 << ((7 - ((speinsn >> 23) & 0x7)) << 2));
639 regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2));
642 __FPU_FPSCR &= ~FP_EX_MASK;
643 __FPU_FPSCR |= (FP_CUR_EXCEPTIONS & FP_EX_MASK);
644 mtspr(SPRN_SPEFSCR, __FPU_FPSCR);
646 current->thread.evr[fc] = vc.wp[0];
647 regs->gpr[fc] = vc.wp[1];
650 printk("ccr = %08lx\n", regs->ccr);
651 printk("cur exceptions = %08x spefscr = %08lx\n",
652 FP_CUR_EXCEPTIONS, __FPU_FPSCR);
653 printk("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
654 printk("va: %08x %08x\n", va.wp[0], va.wp[1]);
655 printk("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
661 if (have_e500_cpu_a005_erratum) {
662 /* according to e500 cpu a005 erratum, reissue efp inst */
665 printk(KERN_DEBUG "re-issue efp inst: %08lx\n", speinsn);
670 printk(KERN_ERR "\nOoops! IEEE-754 compliance handler encountered un-supported instruction.\ninst code: %08lx\n", speinsn);
674 int speround_handler(struct pt_regs *regs)
678 unsigned long speinsn, type, fc;
680 if (get_user(speinsn, (unsigned int __user *) regs->nip))
682 if ((speinsn >> 26) != 4)
683 return -EINVAL; /* not an spe instruction */
685 type = insn_type(speinsn & 0x7ff);
686 if (type == XCR) return -ENOSYS;
688 fc = (speinsn >> 21) & 0x1f;
689 s_lo = regs->gpr[fc] & SIGN_BIT_S;
690 s_hi = current->thread.evr[fc] & SIGN_BIT_S;
691 fgpr.wp[0] = current->thread.evr[fc];
692 fgpr.wp[1] = regs->gpr[fc];
694 __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
696 switch ((speinsn >> 5) & 0x7) {
697 /* Since SPE instructions on E500 core can handle round to nearest
698 * and round toward zero with IEEE-754 complied, we just need
699 * to handle round toward +Inf and round toward -Inf by software.
702 if ((FP_ROUNDMODE) == FP_RND_PINF) {
703 if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */
704 } else { /* round to -Inf */
705 if (s_lo) fgpr.wp[1]++; /* Z < 0, choose Z2 */
710 if (FP_ROUNDMODE == FP_RND_PINF) {
711 if (!s_hi) fgpr.dp[0]++; /* Z > 0, choose Z1 */
712 } else { /* round to -Inf */
713 if (s_hi) fgpr.dp[0]++; /* Z < 0, choose Z2 */
718 if (FP_ROUNDMODE == FP_RND_PINF) {
719 if (!s_lo) fgpr.wp[1]++; /* Z_low > 0, choose Z1 */
720 if (!s_hi) fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */
721 } else { /* round to -Inf */
722 if (s_lo) fgpr.wp[1]++; /* Z_low < 0, choose Z2 */
723 if (s_hi) fgpr.wp[0]++; /* Z_high < 0, choose Z2 */
731 current->thread.evr[fc] = fgpr.wp[0];
732 regs->gpr[fc] = fgpr.wp[1];
737 int __init spe_mathemu_init(void)
741 pvr = mfspr(SPRN_PVR);
743 if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
744 (PVR_VER(pvr) == PVR_VER_E500V2)) {
749 * E500 revision below 1.1, 2.3, 3.1, 4.1, 5.1
750 * need cpu a005 errata workaround
755 have_e500_cpu_a005_erratum = 1;
759 have_e500_cpu_a005_erratum = 1;
765 have_e500_cpu_a005_erratum = 1;
775 module_init(spe_mathemu_init);