2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
38 #include <asm/processor.h>
39 #include <asm/pgtable.h>
41 #include <asm/mmu_context.h>
43 #include <asm/types.h>
44 #include <asm/uaccess.h>
45 #include <asm/machdep.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
56 #include <asm/code-patching.h>
57 #include <asm/fadump.h>
58 #include <asm/firmware.h>
62 #define DBG(fmt...) udbg_printf(fmt)
68 #define DBG_LOW(fmt...) udbg_printf(fmt)
70 #define DBG_LOW(fmt...)
78 * Note: pte --> Linux PTE
79 * HPTE --> PowerPC Hashed Page Table Entry
82 * htab_initialize is called with the MMU off (of course), but
83 * the kernel has been copied down to zero so it can directly
84 * reference global data. At this point it is very difficult
85 * to print debug info.
90 extern unsigned long dart_tablebase;
91 #endif /* CONFIG_U3_DART */
93 static unsigned long _SDR1;
94 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
95 EXPORT_SYMBOL_GPL(mmu_psize_defs);
97 struct hash_pte *htab_address;
98 unsigned long htab_size_bytes;
99 unsigned long htab_hash_mask;
100 EXPORT_SYMBOL_GPL(htab_hash_mask);
101 int mmu_linear_psize = MMU_PAGE_4K;
102 int mmu_virtual_psize = MMU_PAGE_4K;
103 int mmu_vmalloc_psize = MMU_PAGE_4K;
104 #ifdef CONFIG_SPARSEMEM_VMEMMAP
105 int mmu_vmemmap_psize = MMU_PAGE_4K;
107 int mmu_io_psize = MMU_PAGE_4K;
108 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
109 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
110 u16 mmu_slb_size = 64;
111 EXPORT_SYMBOL_GPL(mmu_slb_size);
112 #ifdef CONFIG_PPC_64K_PAGES
113 int mmu_ci_restrictions;
115 #ifdef CONFIG_DEBUG_PAGEALLOC
116 static u8 *linear_map_hash_slots;
117 static unsigned long linear_map_hash_count;
118 static DEFINE_SPINLOCK(linear_map_hash_lock);
119 #endif /* CONFIG_DEBUG_PAGEALLOC */
121 /* There are definitions of page sizes arrays to be used when none
122 * is provided by the firmware.
125 /* Pre-POWER4 CPUs (4k pages only)
127 static struct mmu_psize_def mmu_psize_defaults_old[] = {
131 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
137 /* POWER4, GPUL, POWER5
139 * Support for 16Mb large pages
141 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
145 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
152 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
153 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
159 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
161 unsigned long rflags = pteflags & 0x1fa;
163 /* _PAGE_EXEC -> NOEXEC */
164 if ((pteflags & _PAGE_EXEC) == 0)
167 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
168 * need to add in 0x1 if it's a read-only user page
170 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
171 (pteflags & _PAGE_DIRTY)))
174 * Always add "C" bit for perf. Memory coherence is always enabled
176 return rflags | HPTE_R_C | HPTE_R_M;
179 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
180 unsigned long pstart, unsigned long prot,
181 int psize, int ssize)
183 unsigned long vaddr, paddr;
184 unsigned int step, shift;
187 shift = mmu_psize_defs[psize].shift;
190 prot = htab_convert_pte_flags(prot);
192 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
193 vstart, vend, pstart, prot, psize, ssize);
195 for (vaddr = vstart, paddr = pstart; vaddr < vend;
196 vaddr += step, paddr += step) {
197 unsigned long hash, hpteg;
198 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
199 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
200 unsigned long tprot = prot;
203 * If we hit a bad address return error.
207 /* Make kernel text executable */
208 if (overlaps_kernel_text(vaddr, vaddr + step))
211 /* Make kvm guest trampolines executable */
212 if (overlaps_kvm_tmp(vaddr, vaddr + step))
216 * If relocatable, check if it overlaps interrupt vectors that
217 * are copied down to real 0. For relocatable kernel
218 * (e.g. kdump case) we copy interrupt vectors down to real
219 * address 0. Mark that region as executable. This is
220 * because on p8 system with relocation on exception feature
221 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
222 * in order to execute the interrupt handlers in virtual
223 * mode the vector region need to be marked as executable.
225 if ((PHYSICAL_START > MEMORY_START) &&
226 overlaps_interrupt_vector_text(vaddr, vaddr + step))
229 hash = hpt_hash(vpn, shift, ssize);
230 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
232 BUG_ON(!ppc_md.hpte_insert);
233 ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot,
234 HPTE_V_BOLTED, psize, psize, ssize);
238 #ifdef CONFIG_DEBUG_PAGEALLOC
239 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
240 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
241 #endif /* CONFIG_DEBUG_PAGEALLOC */
243 return ret < 0 ? ret : 0;
246 #ifdef CONFIG_MEMORY_HOTPLUG
247 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
248 int psize, int ssize)
251 unsigned int step, shift;
253 shift = mmu_psize_defs[psize].shift;
256 if (!ppc_md.hpte_removebolted) {
257 printk(KERN_WARNING "Platform doesn't implement "
258 "hpte_removebolted\n");
262 for (vaddr = vstart; vaddr < vend; vaddr += step)
263 ppc_md.hpte_removebolted(vaddr, psize, ssize);
267 #endif /* CONFIG_MEMORY_HOTPLUG */
269 static int __init htab_dt_scan_seg_sizes(unsigned long node,
270 const char *uname, int depth,
273 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
277 /* We are scanning "cpu" nodes only */
278 if (type == NULL || strcmp(type, "cpu") != 0)
281 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
284 for (; size >= 4; size -= 4, ++prop) {
285 if (be32_to_cpu(prop[0]) == 40) {
286 DBG("1T segment support detected\n");
287 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
291 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
295 static void __init htab_init_seg_sizes(void)
297 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
300 static int __init get_idx_from_shift(unsigned int shift)
324 static int __init htab_dt_scan_page_sizes(unsigned long node,
325 const char *uname, int depth,
328 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
332 /* We are scanning "cpu" nodes only */
333 if (type == NULL || strcmp(type, "cpu") != 0)
336 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
338 pr_info("Page sizes from device-tree:\n");
340 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
342 unsigned int base_shift = be32_to_cpu(prop[0]);
343 unsigned int slbenc = be32_to_cpu(prop[1]);
344 unsigned int lpnum = be32_to_cpu(prop[2]);
345 struct mmu_psize_def *def;
348 size -= 3; prop += 3;
349 base_idx = get_idx_from_shift(base_shift);
352 * skip the pte encoding also
354 prop += lpnum * 2; size -= lpnum * 2;
357 def = &mmu_psize_defs[base_idx];
358 if (base_idx == MMU_PAGE_16M)
359 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
361 def->shift = base_shift;
362 if (base_shift <= 23)
365 def->avpnm = (1 << (base_shift - 23)) - 1;
368 * We don't know for sure what's up with tlbiel, so
369 * for now we only set it for 4K and 64K pages
371 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
376 while (size > 0 && lpnum) {
377 unsigned int shift = be32_to_cpu(prop[0]);
378 int penc = be32_to_cpu(prop[1]);
380 prop += 2; size -= 2;
383 idx = get_idx_from_shift(shift);
388 pr_err("Invalid penc for base_shift=%d "
389 "shift=%d\n", base_shift, shift);
391 def->penc[idx] = penc;
392 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
393 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
394 base_shift, shift, def->sllp,
395 def->avpnm, def->tlbiel, def->penc[idx]);
403 #ifdef CONFIG_HUGETLB_PAGE
404 /* Scan for 16G memory blocks that have been set aside for huge pages
405 * and reserve those blocks for 16G huge pages.
407 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
408 const char *uname, int depth,
410 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
411 const __be64 *addr_prop;
412 const __be32 *page_count_prop;
413 unsigned int expected_pages;
414 long unsigned int phys_addr;
415 long unsigned int block_size;
417 /* We are scanning "memory" nodes only */
418 if (type == NULL || strcmp(type, "memory") != 0)
421 /* This property is the log base 2 of the number of virtual pages that
422 * will represent this memory block. */
423 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
424 if (page_count_prop == NULL)
426 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
427 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
428 if (addr_prop == NULL)
430 phys_addr = be64_to_cpu(addr_prop[0]);
431 block_size = be64_to_cpu(addr_prop[1]);
432 if (block_size != (16 * GB))
434 printk(KERN_INFO "Huge page(16GB) memory: "
435 "addr = 0x%lX size = 0x%lX pages = %d\n",
436 phys_addr, block_size, expected_pages);
437 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
438 memblock_reserve(phys_addr, block_size * expected_pages);
439 add_gpage(phys_addr, block_size, expected_pages);
443 #endif /* CONFIG_HUGETLB_PAGE */
445 static void mmu_psize_set_default_penc(void)
448 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
449 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
450 mmu_psize_defs[bpsize].penc[apsize] = -1;
453 #ifdef CONFIG_PPC_64K_PAGES
455 static bool might_have_hea(void)
458 * The HEA ethernet adapter requires awareness of the
459 * GX bus. Without that awareness we can easily assume
460 * we will never see an HEA ethernet device.
462 #ifdef CONFIG_IBMEBUS
463 return !cpu_has_feature(CPU_FTR_ARCH_207S);
469 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
471 static void __init htab_init_page_sizes(void)
475 /* se the invalid penc to -1 */
476 mmu_psize_set_default_penc();
478 /* Default to 4K pages only */
479 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
480 sizeof(mmu_psize_defaults_old));
483 * Try to find the available page sizes in the device-tree
485 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
486 if (rc != 0) /* Found */
490 * Not in the device-tree, let's fallback on known size
491 * list for 16M capable GP & GR
493 if (mmu_has_feature(MMU_FTR_16M_PAGE))
494 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
495 sizeof(mmu_psize_defaults_gp));
497 #ifndef CONFIG_DEBUG_PAGEALLOC
499 * Pick a size for the linear mapping. Currently, we only support
500 * 16M, 1M and 4K which is the default
502 if (mmu_psize_defs[MMU_PAGE_16M].shift)
503 mmu_linear_psize = MMU_PAGE_16M;
504 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
505 mmu_linear_psize = MMU_PAGE_1M;
506 #endif /* CONFIG_DEBUG_PAGEALLOC */
508 #ifdef CONFIG_PPC_64K_PAGES
510 * Pick a size for the ordinary pages. Default is 4K, we support
511 * 64K for user mappings and vmalloc if supported by the processor.
512 * We only use 64k for ioremap if the processor
513 * (and firmware) support cache-inhibited large pages.
514 * If not, we use 4k and set mmu_ci_restrictions so that
515 * hash_page knows to switch processes that use cache-inhibited
516 * mappings to 4k pages.
518 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
519 mmu_virtual_psize = MMU_PAGE_64K;
520 mmu_vmalloc_psize = MMU_PAGE_64K;
521 if (mmu_linear_psize == MMU_PAGE_4K)
522 mmu_linear_psize = MMU_PAGE_64K;
523 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
525 * When running on pSeries using 64k pages for ioremap
526 * would stop us accessing the HEA ethernet. So if we
527 * have the chance of ever seeing one, stay at 4k.
529 if (!might_have_hea() || !machine_is(pseries))
530 mmu_io_psize = MMU_PAGE_64K;
532 mmu_ci_restrictions = 1;
534 #endif /* CONFIG_PPC_64K_PAGES */
536 #ifdef CONFIG_SPARSEMEM_VMEMMAP
537 /* We try to use 16M pages for vmemmap if that is supported
538 * and we have at least 1G of RAM at boot
540 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
541 memblock_phys_mem_size() >= 0x40000000)
542 mmu_vmemmap_psize = MMU_PAGE_16M;
543 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
544 mmu_vmemmap_psize = MMU_PAGE_64K;
546 mmu_vmemmap_psize = MMU_PAGE_4K;
547 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
549 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
550 "virtual = %d, io = %d"
551 #ifdef CONFIG_SPARSEMEM_VMEMMAP
555 mmu_psize_defs[mmu_linear_psize].shift,
556 mmu_psize_defs[mmu_virtual_psize].shift,
557 mmu_psize_defs[mmu_io_psize].shift
558 #ifdef CONFIG_SPARSEMEM_VMEMMAP
559 ,mmu_psize_defs[mmu_vmemmap_psize].shift
563 #ifdef CONFIG_HUGETLB_PAGE
564 /* Reserve 16G huge page memory sections for huge pages */
565 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
566 #endif /* CONFIG_HUGETLB_PAGE */
569 static int __init htab_dt_scan_pftsize(unsigned long node,
570 const char *uname, int depth,
573 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
576 /* We are scanning "cpu" nodes only */
577 if (type == NULL || strcmp(type, "cpu") != 0)
580 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
582 /* pft_size[0] is the NUMA CEC cookie */
583 ppc64_pft_size = be32_to_cpu(prop[1]);
589 static unsigned long __init htab_get_table_size(void)
591 unsigned long mem_size, rnd_mem_size, pteg_count, psize;
593 /* If hash size isn't already provided by the platform, we try to
594 * retrieve it from the device-tree. If it's not there neither, we
595 * calculate it now based on the total RAM size
597 if (ppc64_pft_size == 0)
598 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
600 return 1UL << ppc64_pft_size;
602 /* round mem_size up to next power of 2 */
603 mem_size = memblock_phys_mem_size();
604 rnd_mem_size = 1UL << __ilog2(mem_size);
605 if (rnd_mem_size < mem_size)
609 psize = mmu_psize_defs[mmu_virtual_psize].shift;
610 pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
612 return pteg_count << 7;
615 #ifdef CONFIG_MEMORY_HOTPLUG
616 int create_section_mapping(unsigned long start, unsigned long end)
618 return htab_bolt_mapping(start, end, __pa(start),
619 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
623 int remove_section_mapping(unsigned long start, unsigned long end)
625 return htab_remove_mapping(start, end, mmu_linear_psize,
628 #endif /* CONFIG_MEMORY_HOTPLUG */
630 extern u32 htab_call_hpte_insert1[];
631 extern u32 htab_call_hpte_insert2[];
632 extern u32 htab_call_hpte_remove[];
633 extern u32 htab_call_hpte_updatepp[];
634 extern u32 ht64_call_hpte_insert1[];
635 extern u32 ht64_call_hpte_insert2[];
636 extern u32 ht64_call_hpte_remove[];
637 extern u32 ht64_call_hpte_updatepp[];
639 static void __init htab_finish_init(void)
641 #ifdef CONFIG_PPC_HAS_HASH_64K
642 patch_branch(ht64_call_hpte_insert1,
643 ppc_function_entry(ppc_md.hpte_insert),
645 patch_branch(ht64_call_hpte_insert2,
646 ppc_function_entry(ppc_md.hpte_insert),
648 patch_branch(ht64_call_hpte_remove,
649 ppc_function_entry(ppc_md.hpte_remove),
651 patch_branch(ht64_call_hpte_updatepp,
652 ppc_function_entry(ppc_md.hpte_updatepp),
654 #endif /* CONFIG_PPC_HAS_HASH_64K */
656 patch_branch(htab_call_hpte_insert1,
657 ppc_function_entry(ppc_md.hpte_insert),
659 patch_branch(htab_call_hpte_insert2,
660 ppc_function_entry(ppc_md.hpte_insert),
662 patch_branch(htab_call_hpte_remove,
663 ppc_function_entry(ppc_md.hpte_remove),
665 patch_branch(htab_call_hpte_updatepp,
666 ppc_function_entry(ppc_md.hpte_updatepp),
670 static void __init htab_initialize(void)
673 unsigned long pteg_count;
675 unsigned long base = 0, size = 0, limit;
676 struct memblock_region *reg;
678 DBG(" -> htab_initialize()\n");
680 /* Initialize segment sizes */
681 htab_init_seg_sizes();
683 /* Initialize page sizes */
684 htab_init_page_sizes();
686 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
687 mmu_kernel_ssize = MMU_SEGSIZE_1T;
688 mmu_highuser_ssize = MMU_SEGSIZE_1T;
689 printk(KERN_INFO "Using 1TB segments\n");
693 * Calculate the required size of the htab. We want the number of
694 * PTEGs to equal one half the number of real pages.
696 htab_size_bytes = htab_get_table_size();
697 pteg_count = htab_size_bytes >> 7;
699 htab_hash_mask = pteg_count - 1;
701 if (firmware_has_feature(FW_FEATURE_LPAR)) {
702 /* Using a hypervisor which owns the htab */
705 #ifdef CONFIG_FA_DUMP
707 * If firmware assisted dump is active firmware preserves
708 * the contents of htab along with entire partition memory.
709 * Clear the htab if firmware assisted dump is active so
710 * that we dont end up using old mappings.
712 if (is_fadump_active() && ppc_md.hpte_clear_all)
713 ppc_md.hpte_clear_all();
716 /* Find storage for the HPT. Must be contiguous in
717 * the absolute address space. On cell we want it to be
718 * in the first 2 Gig so we can use it for IOMMU hacks.
720 if (machine_is(cell))
723 limit = MEMBLOCK_ALLOC_ANYWHERE;
725 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
727 DBG("Hash table allocated at %lx, size: %lx\n", table,
730 htab_address = __va(table);
732 /* htab absolute addr + encoded htabsize */
733 _SDR1 = table + __ilog2(pteg_count) - 11;
735 /* Initialize the HPT with no entries */
736 memset((void *)table, 0, htab_size_bytes);
739 mtspr(SPRN_SDR1, _SDR1);
742 prot = pgprot_val(PAGE_KERNEL);
744 #ifdef CONFIG_DEBUG_PAGEALLOC
745 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
746 linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
748 memset(linear_map_hash_slots, 0, linear_map_hash_count);
749 #endif /* CONFIG_DEBUG_PAGEALLOC */
751 /* On U3 based machines, we need to reserve the DART area and
752 * _NOT_ map it to avoid cache paradoxes as it's remapped non
756 /* create bolted the linear mapping in the hash table */
757 for_each_memblock(memory, reg) {
758 base = (unsigned long)__va(reg->base);
761 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
764 #ifdef CONFIG_U3_DART
765 /* Do not map the DART space. Fortunately, it will be aligned
766 * in such a way that it will not cross two memblock regions and
767 * will fit within a single 16Mb page.
768 * The DART space is assumed to be a full 16Mb region even if
769 * we only use 2Mb of that space. We will use more of it later
770 * for AGP GART. We have to use a full 16Mb large page.
772 DBG("DART base: %lx\n", dart_tablebase);
774 if (dart_tablebase != 0 && dart_tablebase >= base
775 && dart_tablebase < (base + size)) {
776 unsigned long dart_table_end = dart_tablebase + 16 * MB;
777 if (base != dart_tablebase)
778 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
782 if ((base + size) > dart_table_end)
783 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
785 __pa(dart_table_end),
791 #endif /* CONFIG_U3_DART */
792 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
793 prot, mmu_linear_psize, mmu_kernel_ssize));
795 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
798 * If we have a memory_limit and we've allocated TCEs then we need to
799 * explicitly map the TCE area at the top of RAM. We also cope with the
800 * case that the TCEs start below memory_limit.
801 * tce_alloc_start/end are 16MB aligned so the mapping should work
802 * for either 4K or 16MB pages.
804 if (tce_alloc_start) {
805 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
806 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
808 if (base + size >= tce_alloc_start)
809 tce_alloc_start = base + size + 1;
811 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
812 __pa(tce_alloc_start), prot,
813 mmu_linear_psize, mmu_kernel_ssize));
818 DBG(" <- htab_initialize()\n");
823 void __init early_init_mmu(void)
825 /* Initialize the MMU Hash table and create the linear mapping
826 * of memory. Has to be done before SLB initialization as this is
827 * currently where the page size encoding is obtained.
831 /* Initialize SLB management */
836 void early_init_mmu_secondary(void)
838 /* Initialize hash table for that CPU */
839 if (!firmware_has_feature(FW_FEATURE_LPAR))
840 mtspr(SPRN_SDR1, _SDR1);
845 #endif /* CONFIG_SMP */
848 * Called by asm hashtable.S for doing lazy icache flush
850 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
854 if (!pfn_valid(pte_pfn(pte)))
857 page = pte_page(pte);
860 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
862 flush_dcache_icache_page(page);
863 set_bit(PG_arch_1, &page->flags);
870 #ifdef CONFIG_PPC_MM_SLICES
871 static unsigned int get_paca_psize(unsigned long addr)
874 unsigned char *hpsizes;
875 unsigned long index, mask_index;
877 if (addr < SLICE_LOW_TOP) {
878 lpsizes = get_paca()->context.low_slices_psize;
879 index = GET_LOW_SLICE_INDEX(addr);
880 return (lpsizes >> (index * 4)) & 0xF;
882 hpsizes = get_paca()->context.high_slices_psize;
883 index = GET_HIGH_SLICE_INDEX(addr);
884 mask_index = index & 0x1;
885 return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
889 unsigned int get_paca_psize(unsigned long addr)
891 return get_paca()->context.user_psize;
896 * Demote a segment to using 4k pages.
897 * For now this makes the whole process use 4k pages.
899 #ifdef CONFIG_PPC_64K_PAGES
900 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
902 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
904 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
905 #ifdef CONFIG_SPU_BASE
906 spu_flush_all_slbs(mm);
908 if (get_paca_psize(addr) != MMU_PAGE_4K) {
909 get_paca()->context = mm->context;
910 slb_flush_and_rebolt();
913 #endif /* CONFIG_PPC_64K_PAGES */
915 #ifdef CONFIG_PPC_SUBPAGE_PROT
917 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
918 * Userspace sets the subpage permissions using the subpage_prot system call.
920 * Result is 0: full permissions, _PAGE_RW: read-only,
921 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
923 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
925 struct subpage_prot_table *spt = &mm->context.spt;
929 if (ea >= spt->maxaddr)
931 if (ea < 0x100000000UL) {
932 /* addresses below 4GB use spt->low_prot */
933 sbpm = spt->low_prot;
935 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
939 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
942 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
944 /* extract 2-bit bitfield for this 4k subpage */
945 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
947 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
948 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
952 #else /* CONFIG_PPC_SUBPAGE_PROT */
953 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
959 void hash_failure_debug(unsigned long ea, unsigned long access,
960 unsigned long vsid, unsigned long trap,
961 int ssize, int psize, int lpsize, unsigned long pte)
963 if (!printk_ratelimit())
965 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
966 ea, access, current->comm);
967 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
968 trap, vsid, ssize, psize, lpsize, pte);
971 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
972 int psize, bool user_region)
975 if (psize != get_paca_psize(ea)) {
976 get_paca()->context = mm->context;
977 slb_flush_and_rebolt();
979 } else if (get_paca()->vmalloc_sllp !=
980 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
981 get_paca()->vmalloc_sllp =
982 mmu_psize_defs[mmu_vmalloc_psize].sllp;
983 slb_vmalloc_update();
989 * 1 - normal page fault
990 * -1 - critical hash insertion error
991 * -2 - access not permitted by subpage protection mechanism
993 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
995 enum ctx_state prev_state = exception_enter();
998 struct mm_struct *mm;
1001 const struct cpumask *tmp;
1002 int rc, user_region = 0, local = 0;
1005 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1008 /* Get region & vsid */
1009 switch (REGION_ID(ea)) {
1010 case USER_REGION_ID:
1014 DBG_LOW(" user region with no mm !\n");
1018 psize = get_slice_psize(mm, ea);
1019 ssize = user_segment_size(ea);
1020 vsid = get_vsid(mm->context.id, ea, ssize);
1022 case VMALLOC_REGION_ID:
1024 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1025 if (ea < VMALLOC_END)
1026 psize = mmu_vmalloc_psize;
1028 psize = mmu_io_psize;
1029 ssize = mmu_kernel_ssize;
1032 /* Not a valid range
1033 * Send the problem up to do_page_fault
1038 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1042 DBG_LOW("Bad address!\n");
1048 if (pgdir == NULL) {
1053 /* Check CPU locality */
1054 tmp = cpumask_of(smp_processor_id());
1055 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1058 #ifndef CONFIG_PPC_64K_PAGES
1059 /* If we use 4K pages and our psize is not 4K, then we might
1060 * be hitting a special driver mapping, and need to align the
1061 * address before we fetch the PTE.
1063 * It could also be a hugepage mapping, in which case this is
1064 * not necessary, but it's not harmful, either.
1066 if (psize != MMU_PAGE_4K)
1067 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1068 #endif /* CONFIG_PPC_64K_PAGES */
1070 /* Get PTE and page size from page tables */
1071 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
1072 if (ptep == NULL || !pte_present(*ptep)) {
1073 DBG_LOW(" no PTE !\n");
1078 /* Add _PAGE_PRESENT to the required access perm */
1079 access |= _PAGE_PRESENT;
1081 /* Pre-check access permissions (will be re-checked atomically
1082 * in __hash_page_XX but this pre-check is a fast path
1084 if (access & ~pte_val(*ptep)) {
1085 DBG_LOW(" no access !\n");
1091 if (pmd_trans_huge(*(pmd_t *)ptep))
1092 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1093 trap, local, ssize, psize);
1094 #ifdef CONFIG_HUGETLB_PAGE
1096 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1097 local, ssize, hugeshift, psize);
1101 * if we have hugeshift, and is not transhuge with
1102 * hugetlb disabled, something is really wrong.
1108 check_paca_psize(ea, mm, psize, user_region);
1113 #ifndef CONFIG_PPC_64K_PAGES
1114 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1116 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1117 pte_val(*(ptep + PTRS_PER_PTE)));
1119 /* Do actual hashing */
1120 #ifdef CONFIG_PPC_64K_PAGES
1121 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1122 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1123 demote_segment_4k(mm, ea);
1124 psize = MMU_PAGE_4K;
1127 /* If this PTE is non-cacheable and we have restrictions on
1128 * using non cacheable large pages, then we switch to 4k
1130 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1131 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1133 demote_segment_4k(mm, ea);
1134 psize = MMU_PAGE_4K;
1135 } else if (ea < VMALLOC_END) {
1137 * some driver did a non-cacheable mapping
1138 * in vmalloc space, so switch vmalloc
1141 printk(KERN_ALERT "Reducing vmalloc segment "
1142 "to 4kB pages because of "
1143 "non-cacheable mapping\n");
1144 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1145 #ifdef CONFIG_SPU_BASE
1146 spu_flush_all_slbs(mm);
1151 check_paca_psize(ea, mm, psize, user_region);
1152 #endif /* CONFIG_PPC_64K_PAGES */
1154 #ifdef CONFIG_PPC_HAS_HASH_64K
1155 if (psize == MMU_PAGE_64K)
1156 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1158 #endif /* CONFIG_PPC_HAS_HASH_64K */
1160 int spp = subpage_protection(mm, ea);
1164 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1168 /* Dump some info in case of hash insertion failure, they should
1169 * never happen so it is really useful to know if/when they do
1172 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1173 psize, pte_val(*ptep));
1174 #ifndef CONFIG_PPC_64K_PAGES
1175 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1177 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1178 pte_val(*(ptep + PTRS_PER_PTE)));
1180 DBG_LOW(" -> rc=%d\n", rc);
1183 exception_exit(prev_state);
1186 EXPORT_SYMBOL_GPL(hash_page);
1188 void hash_preload(struct mm_struct *mm, unsigned long ea,
1189 unsigned long access, unsigned long trap)
1195 unsigned long flags;
1196 int rc, ssize, local = 0;
1198 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1200 #ifdef CONFIG_PPC_MM_SLICES
1201 /* We only prefault standard pages for now */
1202 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1206 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1207 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1209 /* Get Linux PTE if available */
1215 ssize = user_segment_size(ea);
1216 vsid = get_vsid(mm->context.id, ea, ssize);
1220 * Hash doesn't like irqs. Walking linux page table with irq disabled
1221 * saves us from holding multiple locks.
1223 local_irq_save(flags);
1226 * THP pages use update_mmu_cache_pmd. We don't do
1227 * hash preload there. Hence can ignore THP here
1229 ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugepage_shift);
1233 WARN_ON(hugepage_shift);
1234 #ifdef CONFIG_PPC_64K_PAGES
1235 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1236 * a 64K kernel), then we don't preload, hash_page() will take
1237 * care of it once we actually try to access the page.
1238 * That way we don't have to duplicate all of the logic for segment
1239 * page size demotion here
1241 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1243 #endif /* CONFIG_PPC_64K_PAGES */
1245 /* Is that local to this CPU ? */
1246 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1250 #ifdef CONFIG_PPC_HAS_HASH_64K
1251 if (mm->context.user_psize == MMU_PAGE_64K)
1252 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1254 #endif /* CONFIG_PPC_HAS_HASH_64K */
1255 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1256 subpage_protection(mm, ea));
1258 /* Dump some info in case of hash insertion failure, they should
1259 * never happen so it is really useful to know if/when they do
1262 hash_failure_debug(ea, access, vsid, trap, ssize,
1263 mm->context.user_psize,
1264 mm->context.user_psize,
1267 local_irq_restore(flags);
1270 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1271 * do not forget to update the assembly call site !
1273 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1276 unsigned long hash, index, shift, hidx, slot;
1278 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1279 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1280 hash = hpt_hash(vpn, shift, ssize);
1281 hidx = __rpte_to_hidx(pte, index);
1282 if (hidx & _PTEIDX_SECONDARY)
1284 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1285 slot += hidx & _PTEIDX_GROUP_IX;
1286 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1288 * We use same base page size and actual psize, because we don't
1289 * use these functions for hugepage
1291 ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local);
1292 } pte_iterate_hashed_end();
1294 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1295 /* Transactions are not aborted by tlbiel, only tlbie.
1296 * Without, syncing a page back to a block device w/ PIO could pick up
1297 * transactional data (bad!) so we force an abort here. Before the
1298 * sync the page will be made read-only, which will flush_hash_page.
1299 * BIG ISSUE here: if the kernel uses a page from userspace without
1300 * unmapping it first, it may see the speculated version.
1302 if (local && cpu_has_feature(CPU_FTR_TM) &&
1303 current->thread.regs &&
1304 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1306 tm_abort(TM_CAUSE_TLBI);
1311 void flush_hash_range(unsigned long number, int local)
1313 if (ppc_md.flush_hash_range)
1314 ppc_md.flush_hash_range(number, local);
1317 struct ppc64_tlb_batch *batch =
1318 &__get_cpu_var(ppc64_tlb_batch);
1320 for (i = 0; i < number; i++)
1321 flush_hash_page(batch->vpn[i], batch->pte[i],
1322 batch->psize, batch->ssize, local);
1327 * low_hash_fault is called when we the low level hash code failed
1328 * to instert a PTE due to an hypervisor error
1330 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1332 enum ctx_state prev_state = exception_enter();
1334 if (user_mode(regs)) {
1335 #ifdef CONFIG_PPC_SUBPAGE_PROT
1337 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1340 _exception(SIGBUS, regs, BUS_ADRERR, address);
1342 bad_page_fault(regs, address, SIGBUS);
1344 exception_exit(prev_state);
1347 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1348 unsigned long pa, unsigned long rflags,
1349 unsigned long vflags, int psize, int ssize)
1351 unsigned long hpte_group;
1355 hpte_group = ((hash & htab_hash_mask) *
1356 HPTES_PER_GROUP) & ~0x7UL;
1358 /* Insert into the hash table, primary slot */
1359 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1360 psize, psize, ssize);
1362 /* Primary is full, try the secondary */
1363 if (unlikely(slot == -1)) {
1364 hpte_group = ((~hash & htab_hash_mask) *
1365 HPTES_PER_GROUP) & ~0x7UL;
1366 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags,
1367 vflags | HPTE_V_SECONDARY,
1368 psize, psize, ssize);
1371 hpte_group = ((hash & htab_hash_mask) *
1372 HPTES_PER_GROUP)&~0x7UL;
1374 ppc_md.hpte_remove(hpte_group);
1382 #ifdef CONFIG_DEBUG_PAGEALLOC
1383 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1386 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1387 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1388 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1391 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1393 /* Don't create HPTE entries for bad address */
1397 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1399 mmu_linear_psize, mmu_kernel_ssize);
1402 spin_lock(&linear_map_hash_lock);
1403 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1404 linear_map_hash_slots[lmi] = ret | 0x80;
1405 spin_unlock(&linear_map_hash_lock);
1408 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1410 unsigned long hash, hidx, slot;
1411 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1412 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1414 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1415 spin_lock(&linear_map_hash_lock);
1416 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1417 hidx = linear_map_hash_slots[lmi] & 0x7f;
1418 linear_map_hash_slots[lmi] = 0;
1419 spin_unlock(&linear_map_hash_lock);
1420 if (hidx & _PTEIDX_SECONDARY)
1422 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1423 slot += hidx & _PTEIDX_GROUP_IX;
1424 ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize,
1425 mmu_kernel_ssize, 0);
1428 void kernel_map_pages(struct page *page, int numpages, int enable)
1430 unsigned long flags, vaddr, lmi;
1433 local_irq_save(flags);
1434 for (i = 0; i < numpages; i++, page++) {
1435 vaddr = (unsigned long)page_address(page);
1436 lmi = __pa(vaddr) >> PAGE_SHIFT;
1437 if (lmi >= linear_map_hash_count)
1440 kernel_map_linear_page(vaddr, lmi);
1442 kernel_unmap_linear_page(vaddr, lmi);
1444 local_irq_restore(flags);
1446 #endif /* CONFIG_DEBUG_PAGEALLOC */
1448 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1449 phys_addr_t first_memblock_size)
1451 /* We don't currently support the first MEMBLOCK not mapping 0
1452 * physical on those processors
1454 BUG_ON(first_memblock_base != 0);
1456 /* On LPAR systems, the first entry is our RMA region,
1457 * non-LPAR 64-bit hash MMU systems don't have a limitation
1458 * on real mode access, but using the first entry works well
1459 * enough. We also clamp it to 1G to avoid some funky things
1460 * such as RTAS bugs etc...
1462 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1464 /* Finally limit subsequent allocations */
1465 memblock_set_current_limit(ppc64_rma_size);